Annotation of sys/dev/ic/wdcvar.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: wdcvar.h,v 1.41 2007/05/08 16:07:03 deraadt Exp $ */
2: /* $NetBSD: wdcvar.h,v 1.17 1999/04/11 20:50:29 bouyer Exp $ */
3:
4: /*-
5: * Copyright (c) 1998 The NetBSD Foundation, Inc.
6: * All rights reserved.
7: *
8: * This code is derived from software contributed to The NetBSD Foundation
9: * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer.
10: *
11: * Redistribution and use in source and binary forms, with or without
12: * modification, are permitted provided that the following conditions
13: * are met:
14: * 1. Redistributions of source code must retain the above copyright
15: * notice, this list of conditions and the following disclaimer.
16: * 2. Redistributions in binary form must reproduce the above copyright
17: * notice, this list of conditions and the following disclaimer in the
18: * documentation and/or other materials provided with the distribution.
19: * 3. All advertising materials mentioning features or use of this software
20: * must display the following acknowledgement:
21: * This product includes software developed by the NetBSD
22: * Foundation, Inc. and its contributors.
23: * 4. Neither the name of The NetBSD Foundation nor the names of its
24: * contributors may be used to endorse or promote products derived
25: * from this software without specific prior written permission.
26: *
27: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37: * POSSIBILITY OF SUCH DAMAGE.
38: */
39:
40: #ifndef _DEV_IC_WDCVAR_H_
41: #define _DEV_IC_WDCVAR_H_
42:
43: #include <sys/timeout.h>
44:
45: struct channel_queue { /* per channel queue (may be shared) */
46: TAILQ_HEAD(xferhead, wdc_xfer) sc_xfer;
47: };
48:
49: struct channel_softc_vtbl;
50:
51:
52: #define WDC_OPTION_PROBE_VERBOSE 0x10000
53:
54: struct channel_softc { /* Per channel data */
55: struct channel_softc_vtbl *_vtbl;
56:
57: /* Our location */
58: int channel;
59: /* Our controller's softc */
60: struct wdc_softc *wdc;
61: /* Our registers */
62: bus_space_tag_t cmd_iot;
63: bus_space_handle_t cmd_ioh;
64: bus_space_tag_t ctl_iot;
65: bus_space_handle_t ctl_ioh;
66: /* data32{iot,ioh} are only used for 32 bit xfers */
67: bus_space_tag_t data32iot;
68: bus_space_handle_t data32ioh;
69: /* Our state */
70: int ch_flags;
71: #define WDCF_ACTIVE 0x01 /* channel is active */
72: #define WDCF_ONESLAVE 0x02 /* slave-only channel */
73: #define WDCF_IRQ_WAIT 0x10 /* controller is waiting for irq */
74: #define WDCF_DMA_WAIT 0x20 /* controller is waiting for DMA */
75: #define WDCF_VERBOSE_PROBE 0x40 /* verbose probe */
76: u_int8_t ch_status; /* copy of status register */
77: u_int8_t ch_prev_log_status; /* previous logged value of status reg */
78: u_int8_t ch_log_idx;
79: u_int8_t ch_error; /* copy of error register */
80: /* per-drive infos */
81: struct ata_drive_datas ch_drive[2];
82:
83: /*
84: * channel queues. May be the same for all channels, if hw channels
85: * are not independent.
86: */
87: struct channel_queue *ch_queue;
88: struct timeout ch_timo;
89: };
90:
91: /*
92: * Disk Controller register definitions.
93: */
94: #define _WDC_REGMASK 7
95: #define _WDC_AUX 8
96: #define _WDC_RDONLY 16
97: #define _WDC_WRONLY 32
98: enum wdc_regs {
99: wdr_error = _WDC_RDONLY | 1,
100: wdr_precomp = _WDC_WRONLY | 1,
101: wdr_features = _WDC_WRONLY | 1,
102: wdr_seccnt = 2,
103: wdr_ireason = 2,
104: wdr_sector = 3,
105: wdr_lba_lo = 3,
106: wdr_cyl_lo = 4,
107: wdr_lba_mi = 4,
108: wdr_cyl_hi = 5,
109: wdr_lba_hi = 5,
110: wdr_sdh = 6,
111: wdr_status = _WDC_RDONLY | 7,
112: wdr_command = _WDC_WRONLY | 7,
113: wdr_altsts = _WDC_RDONLY | _WDC_AUX,
114: wdr_ctlr = _WDC_WRONLY | _WDC_AUX
115: };
116:
117: #define WDC_NREG 8 /* number of command registers */
118: #define WDC_NSHADOWREG 2 /* number of command "shadow" registers */
119:
120: struct channel_softc_vtbl {
121: u_int8_t (*read_reg)(struct channel_softc *, enum wdc_regs reg);
122: void (*write_reg)(struct channel_softc *, enum wdc_regs reg,
123: u_int8_t var);
124: void (*lba48_write_reg)(struct channel_softc *, enum wdc_regs reg,
125: u_int16_t var);
126:
127: void (*read_raw_multi_2)(struct channel_softc *,
128: void *data, unsigned int nbytes);
129: void (*write_raw_multi_2)(struct channel_softc *,
130: void *data, unsigned int nbytes);
131:
132: void (*read_raw_multi_4)(struct channel_softc *,
133: void *data, unsigned int nbytes);
134: void (*write_raw_multi_4)(struct channel_softc *,
135: void *data, unsigned int nbytes);
136: };
137:
138:
139: #define CHP_READ_REG(chp, a) ((chp)->_vtbl->read_reg)(chp, a)
140: #define CHP_WRITE_REG(chp, a, b) ((chp)->_vtbl->write_reg)(chp, a, b)
141: #define CHP_LBA48_WRITE_REG(chp, a, b) \
142: ((chp)->_vtbl->lba48_write_reg)(chp, a, b)
143:
144: #define CHP_READ_RAW_MULTI_2(chp, a, b) \
145: ((chp)->_vtbl->read_raw_multi_2)(chp, a, b)
146: #define CHP_WRITE_RAW_MULTI_2(chp, a, b) \
147: ((chp)->_vtbl->write_raw_multi_2)(chp, a, b)
148: #define CHP_READ_RAW_MULTI_4(chp, a, b) \
149: ((chp)->_vtbl->read_raw_multi_4)(chp, a, b)
150: #define CHP_WRITE_RAW_MULTI_4(chp, a, b) \
151: ((chp)->_vtbl->write_raw_multi_4)(chp, a, b)
152:
153: struct wdc_softc { /* Per controller state */
154: struct device sc_dev;
155: /* mandatory fields */
156: int cap;
157: /* Capabilities supported by the controller */
158: #define WDC_CAPABILITY_DATA16 0x0001 /* can do 16-bit data access */
159: #define WDC_CAPABILITY_DATA32 0x0002 /* can do 32-bit data access */
160: #define WDC_CAPABILITY_MODE 0x0004 /* controller knows its PIO/DMA modes */
161: #define WDC_CAPABILITY_DMA 0x0008 /* DMA */
162: #define WDC_CAPABILITY_UDMA 0x0010 /* Ultra-DMA/33 */
163: #define WDC_CAPABILITY_HWLOCK 0x0020 /* Needs to lock HW */
164: #define WDC_CAPABILITY_ATA_NOSTREAM 0x0040 /* Don't use stream funcs on ATA */
165: #define WDC_CAPABILITY_ATAPI_NOSTREAM 0x0080 /* Don't use stream f on ATAPI */
166: #define WDC_CAPABILITY_NO_EXTRA_RESETS 0x0100 /* only reset once */
167: #define WDC_CAPABILITY_PREATA 0x0200 /* ctrl can be a pre-ata one */
168: #define WDC_CAPABILITY_IRQACK 0x0400 /* callback to ack interrupt */
169: #define WDC_CAPABILITY_SINGLE_DRIVE 0x800 /* Don't proble second drive */
170: #define WDC_CAPABILITY_NO_ATAPI_DMA 0x1000 /* Don't do DMA with ATAPI */
171: #define WDC_CAPABILITY_SATA 0x2000 /* SATA controller */
172: u_int8_t PIO_cap; /* highest PIO mode supported */
173: u_int8_t DMA_cap; /* highest DMA mode supported */
174: u_int8_t UDMA_cap; /* highest UDMA mode supported */
175: int nchannels; /* Number of channels on this controller */
176: struct channel_softc **channels; /* channels-specific datas (array) */
177: u_int16_t quirks; /* per-device oddities */
178: #define WDC_QUIRK_NOSHORTDMA 0x0001 /* can't do short DMA transfers */
179:
180: #if 0
181: /*
182: * The reference count here is used for both IDE and ATAPI devices.
183: */
184: struct scsipi_adapter sc_atapi_adapter;
185: #endif
186:
187: /* if WDC_CAPABILITY_DMA set in 'cap' */
188: void *dma_arg;
189: int (*dma_init)(void *, int, int, void *, size_t,
190: int);
191: void (*dma_start)(void *, int, int);
192: int (*dma_finish)(void *, int, int, int);
193: /* flags passed to DMA functions */
194: #define WDC_DMA_READ 0x01
195: #define WDC_DMA_IRQW 0x02
196: #define WDC_DMA_LBA48 0x04
197: int dma_status; /* status return from dma_finish() */
198: #define WDC_DMAST_NOIRQ 0x01 /* missing IRQ */
199: #define WDC_DMAST_ERR 0x02 /* DMA error */
200: #define WDC_DMAST_UNDER 0x04 /* DMA underrun */
201:
202: /* if WDC_CAPABILITY_HWLOCK set in 'cap' */
203: int (*claim_hw)(void *, int);
204: void (*free_hw)(void *);
205:
206: /* if WDC_CAPABILITY_MODE set in 'cap' */
207: void (*set_modes)(struct channel_softc *);
208:
209: /* if WDC_CAPABILITY_IRQACK set in 'cap' */
210: void (*irqack)(struct channel_softc *);
211:
212: void (*reset)(struct channel_softc *);
213:
214: /* Driver callback to probe for drives */
215: void (*drv_probe)(struct channel_softc *);
216: };
217:
218: /*
219: * Description of a command to be handled by a controller.
220: * These commands are queued in a list.
221: */
222: struct atapi_return_args;
223:
224: struct wdc_xfer {
225: volatile u_int c_flags;
226: #define C_ATAPI 0x0002 /* xfer is ATAPI request */
227: #define C_TIMEOU 0x0004 /* xfer processing timed out */
228: #define C_NEEDDONE 0x0010 /* need to call upper-level done */
229: #define C_POLL 0x0020 /* cmd is polled */
230: #define C_DMA 0x0040 /* cmd uses DMA */
231: #define C_SENSE 0x0080 /* cmd is a internal command */
232: #define C_MEDIA_ACCESS 0x0100 /* is a media access command */
233: #define C_POLL_MACHINE 0x0200 /* machine has a poll hander */
234:
235: /* Informations about our location */
236: struct channel_softc *chp;
237: u_int8_t drive;
238:
239: /* Information about the current transfer */
240: void *cmd; /* wdc, ata or scsipi command structure */
241: void *databuf;
242: int c_bcount; /* byte count left */
243: int c_skip; /* bytes already transferred */
244: TAILQ_ENTRY(wdc_xfer) c_xferchain;
245: LIST_ENTRY(wdc_xfer) free_list;
246: void (*c_start)(struct channel_softc *, struct wdc_xfer *);
247: int (*c_intr)(struct channel_softc *, struct wdc_xfer *, int);
248: void (*c_kill_xfer)(struct channel_softc *, struct wdc_xfer *);
249:
250: /* Used by ATAPISCSI */
251: volatile int endticks;
252: struct timeout atapi_poll_to;
253: void (*next)(struct channel_softc *, struct wdc_xfer *, int,
254: struct atapi_return_args *);
255: void (*c_done)(struct channel_softc *, struct wdc_xfer *, int,
256: struct atapi_return_args *);
257:
258: /* Used for tape devices */
259: int transfer_len;
260: };
261:
262: /*
263: * Public functions which can be called by ATA or ATAPI specific parts,
264: * or bus-specific backends.
265: */
266:
267: int wdcprobe(struct channel_softc *);
268: void wdcattach(struct channel_softc *);
269: int wdcdetach(struct channel_softc *, int);
270: int wdcactivate(struct device *, enum devact);
271: int wdcintr(void *);
272: void wdc_exec_xfer(struct channel_softc *, struct wdc_xfer *);
273: struct wdc_xfer *wdc_get_xfer(int); /* int = WDC_NOSLEEP/CANSLEEP */
274: #define WDC_CANSLEEP 0x00
275: #define WDC_NOSLEEP 0x01
276: void wdc_free_xfer(struct channel_softc *, struct wdc_xfer *);
277: void wdcstart(struct channel_softc *);
278: int wdcreset(struct channel_softc *, int);
279: #define VERBOSE 1
280: #define SILENT 0 /* wdcreset will not print errors */
281: int wdc_wait_for_status(struct channel_softc *, int, int, int);
282: int wdc_dmawait(struct channel_softc *, struct wdc_xfer *, int);
283: void wdcbit_bucket(struct channel_softc *, int);
284:
285: void wdccommand(struct channel_softc *, u_int8_t, u_int8_t, u_int16_t,
286: u_int8_t, u_int8_t, u_int8_t, u_int8_t);
287: void wdccommandext(struct channel_softc *, u_int8_t, u_int8_t, u_int64_t,
288: u_int16_t);
289: void wdccommandshort(struct channel_softc *, int, int);
290: void wdctimeout(void *arg);
291: void wdc_do_reset(struct channel_softc *);
292:
293: int wdc_addref(struct channel_softc *);
294: void wdc_delref(struct channel_softc *);
295:
296: /*
297: * ST506 spec says that if READY or SEEKCMPLT go off, then the read or write
298: * command is aborted.
299: */
300: #define wdcwait(chp, status, mask, timeout) ((wdc_wait_for_status((chp), (status), (mask), (timeout)) >= 0) ? 0 : -1)
301: #define wait_for_drq(chp, timeout) wdcwait((chp), WDCS_DRQ, WDCS_DRQ, (timeout))
302: #define wait_for_unbusy(chp, timeout) wdcwait((chp), 0, 0, (timeout))
303: #define wait_for_ready(chp, timeout) wdcwait((chp), WDCS_DRDY, \
304: WDCS_DRDY, (timeout))
305:
306: /* ATA/ATAPI specs says a device can take 31s to reset */
307: #define WDC_RESET_WAIT 31000
308:
309: void wdc_disable_intr(struct channel_softc *);
310: void wdc_enable_intr(struct channel_softc *);
311: int wdc_select_drive(struct channel_softc *, int, int);
312: void wdc_set_drive(struct channel_softc *, int drive);
313: void wdc_output_bytes(struct ata_drive_datas *drvp, void *, unsigned int);
314: void wdc_input_bytes(struct ata_drive_datas *drvp, void *, unsigned int);
315:
316: void wdc_print_current_modes(struct channel_softc *);
317:
318: int wdc_ioctl(struct ata_drive_datas *, u_long, caddr_t, int, struct proc *);
319:
320: u_int8_t wdc_default_read_reg(struct channel_softc *,
321: enum wdc_regs);
322: void wdc_default_write_reg(struct channel_softc *,
323: enum wdc_regs, u_int8_t);
324: void wdc_default_lba48_write_reg(struct channel_softc *,
325: enum wdc_regs, u_int16_t);
326: void wdc_default_read_raw_multi_2(struct channel_softc *,
327: void *, unsigned int);
328: void wdc_default_write_raw_multi_2(struct channel_softc *,
329: void *, unsigned int);
330: void wdc_default_read_raw_multi_4(struct channel_softc *,
331: void *, unsigned int);
332: void wdc_default_write_raw_multi_4(struct channel_softc *,
333: void *, unsigned int);
334:
335: #endif /* !_DEV_IC_WDCVAR_H_ */
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