Annotation of sys/dev/ic/wdcreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: wdcreg.h,v 1.16 2006/05/07 21:15:47 miod Exp $ */
2: /* $NetBSD: wdcreg.h,v 1.22 1999/03/07 14:02:54 bouyer Exp $ */
3:
4: /*-
5: * Copyright (c) 1991 The Regents of the University of California.
6: * All rights reserved.
7: *
8: * This code is derived from software contributed to Berkeley by
9: * William Jolitz.
10: *
11: * Redistribution and use in source and binary forms, with or without
12: * modification, are permitted provided that the following conditions
13: * are met:
14: * 1. Redistributions of source code must retain the above copyright
15: * notice, this list of conditions and the following disclaimer.
16: * 2. Redistributions in binary form must reproduce the above copyright
17: * notice, this list of conditions and the following disclaimer in the
18: * documentation and/or other materials provided with the distribution.
19: * 3. Neither the name of the University nor the names of its contributors
20: * may be used to endorse or promote products derived from this software
21: * without specific prior written permission.
22: *
23: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
24: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
27: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33: * SUCH DAMAGE.
34: *
35: * @(#)wdreg.h 7.1 (Berkeley) 5/9/91
36: */
37:
38: #ifndef _DEV_IC_WDCREG_H_
39: #define _DEV_IC_WDCREG_H_
40:
41: /*
42: * Controller register (wdr_ctlr)
43: */
44: #define WDCTL_4BIT 0x08 /* use four head bits (wd1003) */
45: #define WDCTL_RST 0x04 /* reset the controller */
46: #define WDCTL_IDS 0x02 /* disable controller interrupts */
47:
48: /*
49: * Status bits.
50: */
51: #define WDCS_BSY 0x80 /* busy */
52: #define WDCS_DRDY 0x40 /* drive ready */
53: #define WDCS_DWF 0x20 /* drive write fault */
54: #define WDCS_DSC 0x10 /* drive seek complete */
55: #define WDCS_DRQ 0x08 /* data request */
56: #define WDCS_CORR 0x04 /* corrected data */
57: #define WDCS_IDX 0x02 /* index */
58: #define WDCS_ERR 0x01 /* error */
59: #define WDCS_BITS "\020\010BSY\007DRDY\006DWF\005DSC\004DRQ\003CORR\002IDX\001ERR"
60:
61: /*
62: * Error bits.
63: */
64: #define WDCE_BBK 0x80 /* bad block detected */
65: #define WDCE_CRC 0x80 /* CRC error (Ultra-DMA only) */
66: #define WDCE_UNC 0x40 /* uncorrectable data error */
67: #define WDCE_MC 0x20 /* media changed */
68: #define WDCE_IDNF 0x10 /* id not found */
69: #define WDCE_MCR 0x08 /* media change requested */
70: #define WDCE_ABRT 0x04 /* aborted command */
71: #define WDCE_TK0NF 0x02 /* track 0 not found */
72: #define WDCE_AMNF 0x01 /* address mark not found */
73:
74: /*
75: * Commands for Disk Controller.
76: */
77: #define WDCC_NOP 0x00 /* NOP - Always fail with "aborted command" */
78: #define WDCC_RECAL 0x10 /* disk restore code -- resets cntlr */
79:
80: #define WDCC_READ 0x20 /* disk read code */
81: #define WDCC_WRITE 0x30 /* disk write code */
82: #define WDCC__LONG 0x02 /* modifier -- access ecc bytes */
83: #define WDCC__NORETRY 0x01 /* modifier -- no retries */
84:
85: #define WDCC_FORMAT 0x50 /* disk format code */
86: #define WDCC_DIAGNOSE 0x90 /* controller diagnostic */
87: #define WDCC_IDP 0x91 /* initialize drive parameters */
88:
89: #define WDCC_READMULTI 0xc4 /* read multiple */
90: #define WDCC_WRITEMULTI 0xc5 /* write multiple */
91: #define WDCC_SETMULTI 0xc6 /* set multiple mode */
92:
93: #define WDCC_READDMA 0xc8 /* read with DMA */
94: #define WDCC_WRITEDMA 0xca /* write with DMA */
95:
96: #define WDCC_ACKMC 0xdb /* acknowledge media change */
97: #define WDCC_LOCK 0xde /* lock drawer */
98: #define WDCC_UNLOCK 0xdf /* unlock drawer */
99:
100: #define WDCC_FLUSHCACHE 0xe7 /* Flush cache */
101: #define WDCC_IDENTIFY 0xec /* read parameters from controller */
102: #define SET_FEATURES 0xef /* set features */
103:
104: #define WDCC_IDLE 0xe3 /* set idle timer & enter idle mode */
105: #define WDCC_IDLE_IMMED 0xe1 /* enter idle mode */
106: #define WDCC_SLEEP 0xe6 /* enter sleep mode */
107: #define WDCC_STANDBY 0xe2 /* set standby timer & enter standby mode */
108: #define WDCC_STANDBY_IMMED 0xe0 /* enter standby mode */
109: #define WDCC_CHECK_PWR 0xe5 /* check power mode */
110:
111: #define WDCC_READ_EXT 0x24 /* read 48-bit addressing */
112: #define WDCC_WRITE_EXT 0x34 /* write 48-bit addressing */
113:
114: #define WDCC_READMULTI_EXT 0x29 /* read multiple 48-bit addressing */
115: #define WDCC_WRITEMULTI_EXT 0x39 /* write multiple 48-bit addressing */
116:
117: #define WDCC_READDMA_EXT 0x25 /* read 48-bit addressing with DMA */
118: #define WDCC_WRITEDMA_EXT 0x35 /* write 48-bit addressing with DMA */
119:
120: #define WDCC_FLUSHCACHE_EXT 0xea /* 48-bit addressing flush cache */
121:
122: /* security mode commands */
123: #define WDCC_SEC_SET_PASSWORD 0xf1 /* set user or master password */
124: #define WDCC_SEC_UNLOCK 0xf2 /* authenticate */
125: #define WDCC_SEC_ERASE_PREPARE 0xf3
126: #define WDCC_SEC_ERASE_UNIT 0xf4 /* erase all user data */
127: #define WDCC_SEC_FREEZE_LOCK 0xf5 /* prevent password changes */
128: #define WDCC_SEC_DISABLE_PASSWORD 0xf6
129:
130: /* Subcommands for SET_FEATURES (features register ) */
131: #define WDSF_8BIT_PIO_EN 0x01 /* Enable 8bit PIO (CFA featureset) */
132: #define WDSF_EN_WR_CACHE 0x02
133: #define WDSF_SET_MODE 0x03
134: #define WDSF_REASSIGN_EN 0x04 /* Obsolete in ATA-6 */
135: #define WDSF_APM_EN 0x05 /* Enable Adv. Power Management */
136: #define WDSF_PUIS_EN 0x06 /* Enable Power-Up In Standby */
137: #define WDSF_PUIS_SPINUP 0x07 /* Power-Up In Standby spin-up */
138: #define WDSF_CFA_MODE1_EN 0x0A /* Enable CFA power mode 1 */
139: #define WDSF_RMSN_DS 0x31 /* Disable Removable Media Status */
140: #define WDSF_RETRY_DS 0x33 /* Obsolete in ATA-6 */
141: #define WDSF_AAM_EN 0x42 /* Enable Autom. Acoustic Management */
142: #define WDSF_SET_CACHE_SGMT 0x54 /* Obsolete in ATA-6 */
143: #define WDSF_READAHEAD_DS 0x55 /* Disable read look-ahead */
144: #define WDSF_RLSE_EN 0x5D /* Enable release interrupt */
145: #define WDSF_SRV_EN 0x5E /* Enable SERVICE interrupt */
146: #define WDSF_POD_DS 0x66
147: #define WDSF_ECC_DS 0x77
148: #define WDSF_8BIT_PIO_DS 0x81 /* Disable 8bit PIO (CFA featureset) */
149: #define WDSF_WRITE_CACHE_DS 0x82
150: #define WDSF_REASSIGN_DS 0x84
151: #define WDSF_APM_DS 0x85 /* Disable Adv. Power Management */
152: #define WDSF_PUIS_DS 0x86 /* Disable Power-Up In Standby */
153: #define WDSF_ECC_EN 0x88
154: #define WDSF_CFA_MODE1_DS 0x8A /* Disable CFA power mode 1 */
155: #define WDSF_RMSN_EN 0x95 /* Enable Removable Media Status */
156: #define WDSF_RETRY_EN 0x99 /* Obsolete in ATA-6 */
157: #define WDSF_SET_CURRENT 0x9A /* Obsolete in ATA-6 */
158: #define WDSF_READAHEAD_EN 0xAA
159: #define WDSF_PREFETCH_SET 0xAB /* Obsolete in ATA-6 */
160: #define WDSF_AAM_DS 0xC2 /* Disable Autom. Acoustic Management */
161: #define WDSF_POD_EN 0xCC
162: #define WDSF_RLSE_DS 0xDD /* Disable release interrupt */
163: #define WDSF_SRV_DS 0xDE /* Disable SERVICE interrupt */
164:
165: /* parameters uploaded to device/heads register */
166: #define WDSD_IBM 0xa0 /* forced to 512 byte sector, ecc */
167: #define WDSD_CHS 0x00 /* cylinder/head/sector addressing */
168: #define WDSD_LBA 0x40 /* logical block addressing */
169:
170: /* Commands for ATAPI devices */
171: #define ATAPI_CHECK_POWER_MODE 0xe5
172: #define ATAPI_EXEC_DRIVE_DIAGS 0x90
173: #define ATAPI_IDLE_IMMEDIATE 0xe1
174: #define ATAPI_NOP 0x00
175: #define ATAPI_PKT_CMD 0xa0
176: #define ATAPI_IDENTIFY_DEVICE 0xa1
177: #define ATAPI_SOFT_RESET 0x08
178: #define ATAPI_DEVICE_RESET 0x08 /* ATA/ATAPI-5 name for soft reset */
179: #define ATAPI_SLEEP 0xe6
180: #define ATAPI_STANDBY_IMMEDIATE 0xe0
181: #define ATAPI_SMART 0xB0 /* SMART operations */
182: #define ATAPI_SETMAX 0xF9 /* Set Max Address */
183: #define ATAPI_WRITEEXT 0x34 /* Write sectors Ext */
184: #define ATAPI_SETMAXEXT 0x37 /* Set Max Address Ext */
185: #define ATAPI_WRITEMULTIEXT 0x39 /* Write Multi Ext */
186:
187: /* Bytes used by ATAPI_PACKET_COMMAND ( feature register) */
188: #define ATAPI_PKT_CMD_FTRE_DMA 0x01
189: #define ATAPI_PKT_CMD_FTRE_OVL 0x02
190:
191: /* ireason */
192: #define WDCI_CMD 0x01 /* command(1) or data(0) */
193: #define WDCI_IN 0x02 /* transfer to(1) or from(0) the host */
194: #define WDCI_RELEASE 0x04 /* bus released until completion */
195:
196: #define PHASE_CMDOUT (WDCS_DRQ | WDCI_CMD)
197: #define PHASE_DATAIN (WDCS_DRQ | WDCI_IN)
198: #define PHASE_DATAOUT WDCS_DRQ
199: #define PHASE_COMPLETED (WDCI_IN | WDCI_CMD)
200: #define PHASE_ABORTED 0
201:
202: #endif /* !_DEV_IC_WDCREG_H_ */
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