Annotation of sys/dev/ic/uhareg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: uhareg.h,v 1.4 2003/11/16 20:30:06 avsm Exp $ */
2: /* $NetBSD: uhareg.h,v 1.2 1996/09/01 00:54:41 mycroft Exp $ */
3:
4: /*
5: * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: * 3. All advertising materials mentioning features or use of this software
16: * must display the following acknowledgement:
17: * This product includes software developed by Charles M. Hannum.
18: * 4. The name of the author may not be used to endorse or promote products
19: * derived from this software without specific prior written permission.
20: *
21: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31: */
32:
33: /*
34: * Ported for use with the UltraStor 14f by Gary Close (gclose@wvnvms.wvnet.edu)
35: * Slight fixes to timeouts to run with the 34F
36: * Thanks to Julian Elischer for advice and help with this port.
37: *
38: * Originally written by Julian Elischer (julian@tfs.com)
39: * for TRW Financial Systems for use under the MACH(2.5) operating system.
40: *
41: * TRW Financial Systems, in accordance with their agreement with Carnegie
42: * Mellon University, makes this software available to CMU to distribute
43: * or use in any manner that they see fit as long as this message is kept with
44: * the software. For this reason TFS also grants any other persons or
45: * organisations permission to use or modify this software.
46: *
47: * TFS supplies this software to be publicly redistributed
48: * on the understanding that TFS is not responsible for the correct
49: * functioning of this software in any circumstances.
50: *
51: * commenced: Sun Sep 27 18:14:01 PDT 1992
52: * slight mod to make work with 34F as well: Wed Jun 2 18:05:48 WST 1993
53: */
54:
55: typedef u_long physaddr;
56: typedef u_long physlen;
57:
58: /************************** board definitions *******************************/
59: /*
60: * I/O Port Interface
61: */
62: #define U14_LMASK 0x0000 /* local doorbell mask reg */
63: #define U14_LINT 0x0001 /* local doorbell int/stat reg */
64: #define U14_SMASK 0x0002 /* system doorbell mask reg */
65: #define U14_SINT 0x0003 /* system doorbell int/stat reg */
66: #define U14_ID 0x0004 /* product id reg (2 ports) */
67: #define U14_CONFIG 0x0006 /* config reg (2 ports) */
68: #define U14_OGMPTR 0x0008 /* outgoing mail ptr (4 ports) */
69: #define U14_ICMPTR 0x000c /* incoming mail ptr (4 ports) */
70:
71: #define U24_CONFIG 0x0005 /* config reg (3 ports) */
72: #define U24_LMASK 0x000c /* local doorbell mask reg */
73: #define U24_LINT 0x000d /* local doorbell int/stat reg */
74: #define U24_SMASK 0x000e /* system doorbell mask reg */
75: #define U24_SINT 0x000f /* system doorbell int/stat reg */
76: #define U24_OGMCMD 0x0016 /* outgoing commands */
77: #define U24_OGMPTR 0x0017 /* outgoing mail ptr (4 ports) */
78: #define U24_ICMCMD 0x001b /* incoming commands */
79: #define U24_ICMPTR 0x001c /* incoming mail ptr (4 ports) */
80:
81: /*
82: * UHA_LMASK bits (read only)
83: */
84: #define UHA_LDIE 0x80 /* local doorbell int enabled */
85: #define UHA_SRSTE 0x40 /* soft reset enabled */
86: #define UHA_ABORTEN 0x10 /* abort MSCP enabled */
87: #define UHA_OGMINTEN 0x01 /* outgoing mail interrupt enabled */
88:
89: /*
90: * UHA_LINT bits (read only)
91: */
92: #define U14_LDIP 0x80 /* local doorbell int pending */
93: #define U24_LDIP 0x02 /* local doorbell int pending */
94:
95: /*
96: * UHA_LINT bits (write only)
97: */
98: #define U14_OGMFULL 0x01 /* outgoing mailbox is full */
99: #define U14_ABORT 0x10 /* abort MSCP */
100:
101: #define U24_OGMFULL 0x02 /* outgoing mailbox is full */
102:
103: #define UHA_SBRST 0x40 /* scsi bus reset */
104: #define UHA_ADRST 0x80 /* adapter soft reset */
105: #define UHA_ASRST 0xc0 /* adapter and scsi reset */
106:
107: /*
108: * UHA_SMASK bits (read/write)
109: */
110: #define UHA_ENSINT 0x80 /* enable system doorbell interrupt */
111: #define UHA_EN_ABORT_COMPLETE 0x10 /* enable abort MSCP complete int */
112: #define UHA_ENICM 0x01 /* enable ICM interrupt */
113:
114: /*
115: * UHA_SINT bits (read)
116: */
117: #define U14_SDIP 0x80 /* system doorbell int pending */
118: #define U24_SDIP 0x02 /* system doorbell int pending */
119:
120: #define UHA_ABORT_SUCC 0x10 /* abort MSCP successful */
121: #define UHA_ABORT_FAIL 0x18 /* abort MSCP failed */
122:
123: /*
124: * UHA_SINT bits (write)
125: */
126: #define U14_ICM_ACK 0x01 /* acknowledge ICM and clear */
127: #define U24_ICM_ACK 0x02 /* acknowledge ICM and clear */
128:
129: #define UHA_ABORT_ACK 0x18 /* acknowledge status and clear */
130:
131: /*
132: * U14_CONFIG bits (read only)
133: */
134: #define U14_DMA_CH5 0x0000 /* DMA channel 5 */
135: #define U14_DMA_CH6 0x4000 /* 6 */
136: #define U14_DMA_CH7 0x8000 /* 7 */
137: #define U14_DMA_MASK 0xc000
138: #define U14_IRQ15 0x0000 /* IRQ 15 */
139: #define U14_IRQ14 0x1000 /* 14 */
140: #define U14_IRQ11 0x2000 /* 11 */
141: #define U14_IRQ10 0x3000 /* 10 */
142: #define U14_IRQ_MASK 0x3000
143: #define U14_HOSTID_MASK 0x0007
144:
145: /*
146: * U24_CONFIG bits (read only)
147: */
148: #define U24_MAGIC1 0x08
149: #define U24_IRQ15 0x10
150: #define U24_IRQ14 0x20
151: #define U24_IRQ11 0x40
152: #define U24_IRQ10 0x80
153: #define U24_IRQ_MASK 0xf0
154:
155: #define U24_MAGIC2 0x04
156:
157: #define U24_HOSTID_MASK 0x07
158:
159: /*
160: * EISA registers (offset from slot base)
161: */
162: #define EISA_VENDOR 0x0c80 /* vendor ID (2 ports) */
163: #define EISA_MODEL 0x0c82 /* model number (2 ports) */
164: #define EISA_CONTROL 0x0c84
165: #define EISA_RESET 0x04
166: #define EISA_ERROR 0x02
167: #define EISA_ENABLE 0x01
168:
169: /*
170: * host_stat error codes
171: */
172: #define UHA_NO_ERR 0x00 /* No error supposedly */
173: #define UHA_SBUS_ABORT_ERR 0x84 /* scsi bus abort error */
174: #define UHA_SBUS_TIMEOUT 0x91 /* scsi bus selection timeout */
175: #define UHA_SBUS_OVER_UNDER 0x92 /* scsi bus over/underrun */
176: #define UHA_BAD_SCSI_CMD 0x96 /* illegal scsi command */
177: #define UHA_AUTO_SENSE_ERR 0x9b /* auto request sense err */
178: #define UHA_SBUS_RES_ERR 0xa3 /* scsi bus reset error */
179: #define UHA_BAD_SG_LIST 0xff /* invalid scatter gath list */
180:
181: #define UHA_NSEG 33 /* number of dma segments supported */
182:
183: struct uha_dma_seg {
184: physaddr seg_addr;
185: physlen seg_len;
186: };
187:
188: struct uha_mscp {
189: u_char opcode:3;
190: #define UHA_HAC 0x01 /* host adapter command */
191: #define UHA_TSP 0x02 /* target scsi pass through command */
192: #define UHA_SDR 0x04 /* scsi device reset */
193: u_char xdir:2; /* xfer direction */
194: #define UHA_SDET 0x00 /* determined by scsi command */
195: #define UHA_SDIN 0x01 /* scsi data in */
196: #define UHA_SDOUT 0x02 /* scsi data out */
197: #define UHA_NODATA 0x03 /* no data xfer */
198: u_char dcn:1; /* disable disconnect for this command */
199: u_char ca:1; /* cache control */
200: u_char sgth:1; /* scatter gather flag */
201: u_char target:3;
202: u_char chan:2; /* scsi channel (always 0 for 14f) */
203: u_char lun:3;
204: physaddr data_addr;
205: physlen data_length;
206: physaddr link_addr;
207: u_char link_id;
208: u_char sg_num; /* number of scat gath segs */
209: /*in s-g list if sg flag is */
210: /*set. starts at 1, 8bytes per */
211: u_char req_sense_length;
212: u_char scsi_cmd_length;
213: struct scsi_generic scsi_cmd;
214: u_char host_stat;
215: u_char target_stat;
216: physaddr sense_ptr; /* if 0 no auto sense */
217:
218: struct uha_dma_seg uha_dma[UHA_NSEG];
219: struct scsi_sense_data mscp_sense;
220: /*-----------------end of hardware supported fields----------------*/
221: TAILQ_ENTRY(uha_mscp) chain;
222: struct uha_mscp *nexthash;
223: long hashkey;
224: struct scsi_xfer *xs; /* the scsi_xfer for this cmd */
225: int flags;
226: #define MSCP_ALLOC 0x01
227: #define MSCP_ABORT 0x02
228: int timeout;
229: } __packed;
230:
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