Annotation of sys/dev/ic/trm.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: trm.h,v 1.1 2002/02/18 01:55:30 krw Exp $
! 2: * ------------------------------------------------------------
! 3: * O.S : OpenBSD
! 4: * File Name : trm.h
! 5: * Device Driver for Tekram DC395U/UW/F,DC315/U
! 6: * PCI SCSI Bus Master Host Adapter
! 7: * (SCSI chip set used Tekram ASIC TRM-S1040)
! 8: *
! 9: * (C)Copyright 1995-1999 Tekram Technology Co., Ltd.
! 10: * (C)Copyright 2001-2002 Ashley R. Martens and Kenneth R Westerback
! 11: * ------------------------------------------------------------
! 12: * Redistribution and use in source and binary forms, with or without
! 13: * modification, are permitted provided that the following conditions
! 14: * are met:
! 15: * 1. Redistributions of source code must retain the above copyright
! 16: * notice, this list of conditions and the following disclaimer.
! 17: * 2. Redistributions in binary form must reproduce the above copyright
! 18: * notice, this list of conditions and the following disclaimer in the
! 19: * documentation and/or other materials provided with the distribution.
! 20: * 3. The name of the author may not be used to endorse or promote products
! 21: * derived from this software without specific prior written permission.
! 22: *
! 23: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
! 24: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
! 25: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
! 26: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
! 27: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
! 28: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
! 29: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
! 30: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
! 31: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
! 32: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
! 33: * ------------------------------------------------------------
! 34: */
! 35:
! 36: #ifndef _TRM_H
! 37: #define _TRM_H
! 38:
! 39: /*
! 40: * ------------------------------------------------------------
! 41: * Segment Entry
! 42: * ------------------------------------------------------------
! 43: */
! 44: struct SGentry
! 45: {
! 46: u_int32_t address;
! 47: u_int32_t length;
! 48: };
! 49:
! 50: /*
! 51: * -----------------------------------------------------------------------
! 52: * feature of chip set MAX value
! 53: * -----------------------------------------------------------------------
! 54: */
! 55:
! 56: #define TRM_MAX_ADAPTER_NUM 4
! 57: #define TRM_MAX_TARGETS 16
! 58: #define TRM_MAX_LUNS 8
! 59: #define TRM_MAX_SG_LISTENTRY 32
! 60: #define TRM_MAX_CMD_PER_LUN 32
! 61: #define TRM_MAX_SRB_CNT TRM_MAX_CMD_PER_LUN*4
! 62: #define TRM_MAX_PHYSG_BYTE ((TRM_MAX_SG_LISTENTRY - 1) << PGSHIFT)
! 63: #define TRM_MAX_SYNC_OFFSET 15
! 64: #define TRM_SEL_TIMEOUT 153 /* 250 ms selection timeout (@40MHz) */
! 65:
! 66: /*
! 67: *-----------------------------------------------------------------------
! 68: * SCSI Request Block
! 69: *-----------------------------------------------------------------------
! 70: */
! 71: struct trm_scsi_req_q
! 72: {
! 73: TAILQ_ENTRY(trm_scsi_req_q) link;
! 74: bus_dmamap_t dmamapxfer;
! 75: u_int32_t PhysSRB;
! 76: u_int32_t SRBTotalXferLength;
! 77: u_int32_t SRBSGPhyAddr; /* a segment starting address */
! 78:
! 79: u_int16_t SRBState; /* State machine */
! 80: #define TRM_FREE 0x0000
! 81: #define TRM_WAIT 0x0001
! 82: #define TRM_READY 0x0002
! 83: #define TRM_MSGOUT 0x0004 /*arbitration+msg_out 1st byte */
! 84: #define TRM_EXTEND_MSGIN 0x0010
! 85: #define TRM_COMMAND 0x0020
! 86: #define TRM_START 0x0040 /*arbitration+msg_out+command_out */
! 87: #define TRM_DISCONNECTED 0x0080
! 88: #define TRM_DATA_XFER 0x0100
! 89: #define TRM_XFERPAD 0x0200
! 90: #define TRM_STATUS 0x0400
! 91: #define TRM_COMPLETED 0x0800
! 92: #define TRM_ABORT_SENT 0x1000
! 93: #define TRM_UNEXPECT_RESEL 0x8000
! 94:
! 95: u_int8_t AdaptStatus;
! 96: #define TRM_STATUS_GOOD 0x00
! 97: #define TRM_SELECTION_TIMED_OUT 0x11
! 98: #define TRM_OVER_UNDER_RUN 0x12
! 99: #define TRM_UNEXP_BUS_FREE 0x13
! 100: #define TRM_TARGET_PHASE_F 0x14
! 101: #define TRM_INVALID_CCB_OP 0x16
! 102: #define TRM_LINK_CCB_BAD 0x17
! 103: #define TRM_BAD_TARGET_DIR 0x18
! 104: #define TRM_DUPLICATE_CCB 0x19
! 105: #define TRM_BAD_CCB_OR_SG 0x1A
! 106: #define TRM_ABORT 0xFF
! 107:
! 108: u_int8_t CmdBlock[12];
! 109:
! 110: u_int8_t ScsiCmdLen;
! 111: u_int8_t ScsiPhase;
! 112:
! 113: u_int8_t SRBFlag;
! 114: #define TRM_AUTO_REQSENSE 0x01
! 115: #define TRM_SCSI_TIMED_OUT 0x02
! 116: #define TRM_PARITY_ERROR 0x04
! 117: #define TRM_ON_GOING_SRB 0x08
! 118: #define TRM_ON_WAITING_SRB 0x10
! 119:
! 120: u_int8_t SRBSGCount;
! 121: u_int8_t SRBSGIndex;
! 122: u_int8_t TagNumber;
! 123: #define TRM_NO_TAG 0x00
! 124:
! 125: u_int8_t TargetStatus; /* SCSI status codes + Tekram: */
! 126: #define TRM_SCSI_UNEXP_BUS_FREE 0xFD /* Unexpect Bus Free */
! 127: #define TRM_SCSI_BUS_RST_DETECTED 0xFE /* Scsi Bus Reset detected */
! 128: #define TRM_SCSI_SELECT_TIMEOUT 0xFF /* Selection Time out */
! 129:
! 130: struct trm_dcb *pSRBDCB;
! 131:
! 132: struct SGentry SegmentX[TRM_MAX_SG_LISTENTRY];
! 133:
! 134: struct scsi_xfer *xs;
! 135:
! 136: struct scsi_sense_data scsisense;
! 137: u_int32_t scsisensePhyAddr;
! 138: };
! 139:
! 140: TAILQ_HEAD(SRB_HEAD, trm_scsi_req_q);
! 141:
! 142: /*
! 143: *-----------------------------------------------------------------------
! 144: * Device Control Block
! 145: *-----------------------------------------------------------------------
! 146: */
! 147: struct trm_dcb
! 148: {
! 149: u_int32_t TagMask;
! 150:
! 151: u_int16_t DCBFlag;
! 152: #define TRM_WIDE_NEGO_ENABLE 0x0001
! 153: #define TRM_DOING_WIDE_NEGO 0x0002
! 154: #define TRM_WIDE_NEGO_DONE 0x0004
! 155: #define TRM_SYNC_NEGO_ENABLE 0x0008
! 156: #define TRM_DOING_SYNC_NEGO 0x0010
! 157: #define TRM_USE_TAG_QUEUING 0x0020
! 158: #define TRM_QUEUE_FULL 0x0040
! 159: #define TRM_WIDE_NEGO_16BIT 0x0080
! 160: #define TRM_QUIRKS_VALID 0x0100
! 161: #define TRM_BAD_DCB 0x0200
! 162:
! 163: u_int8_t DevMode; /* trm_target_nvram.NvmTarCfg0 */
! 164:
! 165: u_int8_t MaxNegoPeriod; /* Maximum allow sync period */
! 166: u_int8_t SyncPeriod; /* Current sync period */
! 167: u_int8_t SyncOffset; /* Current sync offset */
! 168:
! 169: u_int8_t target; /* SCSI Target ID */
! 170: u_int8_t lun; /* SCSI Logical Unit Number */
! 171:
! 172: u_int8_t IdentifyMsg;
! 173:
! 174: struct scsi_link *sc_link;
! 175: struct trm_scsi_req_q *pActiveSRB;
! 176: };
! 177:
! 178: /*
! 179: *-----------------------------------------------------------------------
! 180: * Adapter Control Block
! 181: *-----------------------------------------------------------------------
! 182: */
! 183: struct trm_softc
! 184: {
! 185: struct device sc_device;
! 186:
! 187: bus_space_handle_t sc_iohandle;
! 188: bus_space_tag_t sc_iotag;
! 189: bus_dma_tag_t sc_dmatag;
! 190: bus_dmamap_t sc_dmamap_control; /* map the control structures */
! 191:
! 192: u_int16_t sc_AdapterUnit; /* nth Adapter this driver */
! 193:
! 194: u_int8_t sc_AdaptSCSIID; /* Adapter SCSI Target ID */
! 195: u_int8_t sc_TagMaxNum;
! 196:
! 197: u_int8_t sc_config;
! 198: #define HCC_WIDE_CARD 0x20
! 199: #define HCC_SCSI_RESET 0x10
! 200: #define HCC_PARITY 0x08
! 201: #define HCC_AUTOTERM 0x04
! 202: #define HCC_LOW8TERM 0x02
! 203: #define HCC_UP8TERM 0x01
! 204:
! 205: u_int8_t sc_Flag;
! 206: #define RESET_DEV 0x01
! 207: #define RESET_DETECT 0x02
! 208: #define RESET_DONE 0x04
! 209:
! 210: u_int8_t MsgCnt;
! 211: u_int8_t MsgBuf[6];
! 212:
! 213: /*
! 214: *----------------------------------
! 215: * Link to the generic SCSI driver
! 216: *----------------------------------
! 217: */
! 218: struct scsi_adapter sc_adapter;
! 219: struct scsi_link sc_link;
! 220:
! 221: struct SRB_HEAD freeSRB;
! 222: struct SRB_HEAD goingSRB;
! 223: struct SRB_HEAD waitingSRB;
! 224:
! 225: struct trm_dcb *pActiveDCB;
! 226: struct trm_dcb *pDCB[TRM_MAX_TARGETS][TRM_MAX_LUNS];
! 227:
! 228: struct trm_scsi_req_q *SRB;
! 229: };
! 230:
! 231: /*
! 232: * The SEEPROM structure for TRM_S1040
! 233: */
! 234: struct trm_target_nvram
! 235: {
! 236: u_int8_t NvmTarCfg0; /* Target configuration byte 0 */
! 237: #define TRM_WIDE 0x20 /* Wide negotiate */
! 238: #define TRM_TAG_QUEUING 0x10 /* Enable SCSI tag queuing */
! 239: #define TRM_SEND_START 0x08 /* Send start command SPINUP */
! 240: #define TRM_DISCONNECT 0x04 /* Enable SCSI disconnect */
! 241: #define TRM_SYNC 0x02 /* Sync negotiation */
! 242: #define TRM_PARITY 0x01 /* (it should be defined at NAC ) */
! 243:
! 244: u_int8_t NvmTarPeriod; /* Target period */
! 245: u_int8_t NvmTarCfg2; /* Target configuration byte 2 */
! 246: u_int8_t NvmTarCfg3; /* Target configuration byte 3 */
! 247: };
! 248:
! 249: struct trm_adapter_nvram
! 250: {
! 251: u_int8_t NvramSubVendorID[2]; /*0,1 Sub Vendor ID */
! 252: u_int8_t NvramSubSysID[2]; /*2,3 Sub System ID */
! 253: u_int8_t NvramSubClass; /*4 Sub Class */
! 254: u_int8_t NvramVendorID[2]; /*5,6 Vendor ID */
! 255: u_int8_t NvramDeviceID[2]; /*7,8 Device ID */
! 256: u_int8_t NvramReserved; /*9 Reserved */
! 257: struct trm_target_nvram NvramTarget[TRM_MAX_TARGETS]; /* 10 */
! 258: u_int8_t NvramScsiId; /*74 Host Adapter SCSI ID */
! 259: u_int8_t NvramChannelCfg; /*75 Channel configuration */
! 260: #define NAC_SCANLUN 0x20 /* Include LUN as BIOS device */
! 261: #define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */
! 262: #define NAC_GREATER_1G 0x02 /* > 1G support enable */
! 263: #define NAC_GT2DRIVES 0x01 /* Support more than 2 drives */
! 264: u_int8_t NvramDelayTime; /*76 Power on delay time */
! 265: u_int8_t NvramMaxTag; /*77 Maximum tags */
! 266: u_int8_t NvramReserved0; /*78 */
! 267: u_int8_t NvramBootTarget; /*79 */
! 268: u_int8_t NvramBootLun; /*80 */
! 269: u_int8_t NvramReserved1; /*81 */
! 270: u_int16_t Reserved[22]; /*82,..125 */
! 271: u_int16_t NvramCheckSum; /*126,127 */
! 272: };
! 273:
! 274: /*
! 275: * The PCI configuration register offsets for the TRM_S1040, and
! 276: * the associated bit definitions.
! 277: */
! 278:
! 279: #define TRM_S1040_ID 0x00 /* Vendor and Device ID */
! 280: #define TRM_S1040_COMMAND 0x04 /* PCI command register */
! 281: #define TRM_S1040_IOBASE 0x10 /* I/O Space base address */
! 282: #define TRM_S1040_ROMBASE 0x30 /* Expansion ROM Base Address */
! 283: #define TRM_S1040_INTLINE 0x3C /* Interrupt line */
! 284:
! 285: #define TRM_S1040_SCSI_STATUS 0x80 /* SCSI Status (R) */
! 286: #define COMMANDPHASEDONE 0x2000 /* SCSI command phase done */
! 287: #define SCSIXFERDONE 0x0800 /* SCSI SCSI transfer done */
! 288: #define SCSIXFERCNT_2_ZERO 0x0100 /* SCSI SCSI transfer count to zero */
! 289: #define SCSIINTERRUPT 0x0080 /* SCSI interrupt pending */
! 290: #define COMMANDABORT 0x0040 /* SCSI command abort */
! 291: #define SEQUENCERACTIVE 0x0020 /* SCSI sequencer active */
! 292: #define PHASEMISMATCH 0x0010 /* SCSI phase mismatch */
! 293: #define PARITYERROR 0x0008 /* SCSI parity error */
! 294: #define PHASEMASK 0x0007 /* Phase MSG/CD/IO */
! 295: #define PH_DATA_OUT 0x00 /* Data out phase */
! 296: #define PH_DATA_IN 0x01 /* Data in phase */
! 297: #define PH_COMMAND 0x02 /* Command phase */
! 298: #define PH_STATUS 0x03 /* Status phase */
! 299: #define PH_BUS_FREE 0x05 /* Invalid phase used as bus free */
! 300: #define PH_MSG_OUT 0x06 /* Message out phase */
! 301: #define PH_MSG_IN 0x07 /* Message in phase */
! 302: #define TRM_S1040_SCSI_CONTROL 0x80 /* SCSI Control (W) */
! 303: #define DO_CLRATN 0x0400 /* Clear ATN */
! 304: #define DO_SETATN 0x0200 /* Set ATN */
! 305: #define DO_CMDABORT 0x0100 /* Abort SCSI command */
! 306: #define DO_RSTMODULE 0x0010 /* Reset SCSI chip */
! 307: #define DO_RSTSCSI 0x0008 /* Reset SCSI bus */
! 308: #define DO_CLRFIFO 0x0004 /* Clear SCSI transfer FIFO */
! 309: #define DO_DATALATCH 0x0002 /* Enable SCSI bus data latch */
! 310: #define DO_HWRESELECT 0x0001 /* Enable hardware reselection */
! 311: #define TRM_S1040_SCSI_FIFOCNT 0x82 /* SCSI FIFO Counter 5bits(R) */
! 312: #define TRM_S1040_SCSI_SIGNAL 0x83 /* SCSI low level signal (R/W) */
! 313: #define TRM_S1040_SCSI_INTSTATUS 0x84 /* SCSI Interrupt Status (R) */
! 314: #define INT_SCAM 0x80 /* SCAM selection interrupt */
! 315: #define INT_SELECT 0x40 /* Selection interrupt */
! 316: #define INT_SELTIMEOUT 0x20 /* Selection timeout interrupt */
! 317: #define INT_DISCONNECT 0x10 /* Bus disconnected interrupt */
! 318: #define INT_RESELECTED 0x08 /* Reselected interrupt */
! 319: #define INT_SCSIRESET 0x04 /* SCSI reset detected interrupt */
! 320: #define INT_BUSSERVICE 0x02 /* Bus service interrupt */
! 321: #define INT_CMDDONE 0x01 /* SCSI command done interrupt */
! 322: #define TRM_S1040_SCSI_OFFSET 0x84 /* SCSI Offset Count (W) */
! 323: /*
! 324: * Bit Name Definition
! 325: * 07-05 0 RSVD Reversed. Always 0.
! 326: * 04 0 OFFSET4 Reversed for LVDS. Always 0.
! 327: * 03-00 0 OFFSET[03:00] Offset number from 0 to 15
! 328: */
! 329: #define TRM_S1040_SCSI_SYNC 0x85 /* SCSI Synchronous Control (R/W) */
! 330: #define LVDS_SYNC 0x20 /* Enable LVDS synchronous */
! 331: #define WIDE_SYNC 0x10 /* Enable WIDE synchronous */
! 332: #define ALT_SYNC 0x08 /* Enable Fast-20 alternate synchronous */
! 333: /*
! 334: * SYNCM 7 6 5 4 3 2 1 0
! 335: * Name RSVD RSVD LVDS WIDE ALTPERD PERIOD2 PERIOD1 PERIOD0
! 336: * Default 0 0 0 0 0 0 0 0
! 337: *
! 338: *
! 339: * Bit Name Definition
! 340: * --- ---- ----------
! 341: * 07-06 0 RSVD Reversed. Always read 0
! 342: * 05 0 LVDS Reversed. Always read 0
! 343: * 04 0 WIDE/WSCSI Enable wide (16-bits) SCSI transfer.
! 344: * 03 0 ALTPERD/ALTPD Alternate (Sync./Period) mode.
! 345: *
! 346: * @@ When this bit is set,
! 347: * the synchronous period bits 2:0
! 348: * in the Synchronous Mode register
! 349: * are used to transfer data
! 350: * at the Fast-20 rate.
! 351: * @@ When this bit is reset,
! 352: * the synchronous period bits 2:0
! 353: * in the Synchronous Mode Register
! 354: * are used to transfer data
! 355: * at the Fast-40 rate.
! 356: *
! 357: * 02-00 0 PERIOD[2:0]/SXPD[02:00] Synchronous SCSI Transfer Rate.
! 358: * These 3 bits specify
! 359: * the Synchronous SCSI Transfer Rate
! 360: * for Fast-20 and Fast-10.
! 361: * These bits are also reset
! 362: * by a SCSI Bus reset.
! 363: *
! 364: * For Fast-10 bit ALTPD = 0 and LVDS = 0
! 365: * and bit2,bit1,bit0 is defined as follows :
! 366: *
! 367: * 000 100ns, 10.0 Mbytes/s
! 368: * 001 150ns, 6.6 Mbytes/s
! 369: * 010 200ns, 5.0 Mbytes/s
! 370: * 011 250ns, 4.0 Mbytes/s
! 371: * 100 300ns, 3.3 Mbytes/s
! 372: * 101 350ns, 2.8 Mbytes/s
! 373: * 110 400ns, 2.5 Mbytes/s
! 374: * 111 450ns, 2.2 Mbytes/s
! 375: *
! 376: * For Fast-20 bit ALTPD = 1 and LVDS = 0
! 377: * and bit2,bit1,bit0 is defined as follows :
! 378: *
! 379: * 000 50ns, 20.0 Mbytes/s
! 380: * 001 75ns, 13.3 Mbytes/s
! 381: * 010 100ns, 10.0 Mbytes/s
! 382: * 011 125ns, 8.0 Mbytes/s
! 383: * 100 150ns, 6.6 Mbytes/s
! 384: * 101 175ns, 5.7 Mbytes/s
! 385: * 110 200ns, 5.0 Mbytes/s
! 386: * 111 250ns, 4.0 Mbytes/s
! 387: *
! 388: * For Fast-40 bit ALTPD = 0 and LVDS = 1
! 389: * and bit2,bit1,bit0 is defined as follows :
! 390: *
! 391: * 000 25ns, 40.0 Mbytes/s
! 392: * 001 50ns, 20.0 Mbytes/s
! 393: * 010 75ns, 13.3 Mbytes/s
! 394: * 011 100ns, 10.0 Mbytes/s
! 395: * 100 125ns, 8.0 Mbytes/s
! 396: * 101 150ns, 6.6 Mbytes/s
! 397: * 110 175ns, 5.7 Mbytes/s
! 398: * 111 200ns, 5.0 Mbytes/s
! 399: */
! 400: #define TRM_S1040_SCSI_TARGETID 0x86 /* SCSI Target ID (R/W) */
! 401: #define TRM_S1040_SCSI_IDMSG 0x87 /* SCSI Identify Message (R) */
! 402: #define TRM_S1040_SCSI_HOSTID 0x87 /* SCSI Host ID (W) */
! 403: #define TRM_S1040_SCSI_COUNTER 0x88 /* SCSI Transfer Counter 24bits(R/W) */
! 404: #define TRM_S1040_SCSI_INTEN 0x8C /* SCSI Interrupt Enable (R/W) */
! 405: #define EN_SCAM 0x80 /* Enable SCAM selection interrupt */
! 406: #define EN_SELECT 0x40 /* Enable selection interrupt */
! 407: #define EN_SELTIMEOUT 0x20 /* Enable selection timeout interrupt */
! 408: #define EN_DISCONNECT 0x10 /* Enable bus disconnected interrupt */
! 409: #define EN_RESELECTED 0x08 /* Enable reselected interrupt */
! 410: #define EN_SCSIRESET 0x04 /* Enable SCSI reset detected interrupt*/
! 411: #define EN_BUSSERVICE 0x02 /* Enable bus service interrupt */
! 412: #define EN_CMDDONE 0x01 /* Enable SCSI command done interrupt */
! 413: #define TRM_S1040_SCSI_CONFIG0 0x8D /* SCSI Configuration 0 (R/W) */
! 414: #define PHASELATCH 0x40 /* Enable phase latch */
! 415: #define INITIATOR 0x20 /* Enable initiator mode */
! 416: #define PARITYCHECK 0x10 /* Enable parity check */
! 417: #define BLOCKRST 0x01 /* Disable SCSI reset1 */
! 418: #define TRM_S1040_SCSI_CONFIG1 0x8E /* SCSI Configuration 1 (R/W) */
! 419: #define ACTIVE_NEGPLUS 0x10 /* Enhance active negation */
! 420: #define FILTER_DISABLE 0x08 /* Disable SCSI data filter */
! 421: #define ACTIVE_NEG 0x02 /* Enable active negation */
! 422: #define TRM_S1040_SCSI_CONFIG2 0x8F /* SCSI Configuration 2 (R/W) */
! 423: #define TRM_S1040_SCSI_COMMAND 0x90 /* SCSI Command (R/W) */
! 424: #define SCMD_COMP 0x12 /* Command complete */
! 425: #define SCMD_SEL_ATN 0x60 /* Selection with ATN */
! 426: #define SCMD_SEL_ATN3 0x64 /* Selection with ATN3 */
! 427: #define SCMD_SEL_ATNSTOP 0xB8 /* Selection with ATN and Stop */
! 428: #define SCMD_FIFO_OUT 0xC0 /* SCSI FIFO transfer out */
! 429: #define SCMD_DMA_OUT 0xC1 /* SCSI DMA transfer out */
! 430: #define SCMD_FIFO_IN 0xC2 /* SCSI FIFO transfer in */
! 431: #define SCMD_DMA_IN 0xC3 /* SCSI DMA transfer in */
! 432: #define SCMD_MSGACCEPT 0xD8 /* Message accept */
! 433: /*
! 434: * Code Command Description
! 435: *
! 436: * 02 Enable reselection with FIFO
! 437: * 40 Select without ATN with FIFO
! 438: * 60 Select with ATN with FIFO
! 439: * 64 Select with ATN3 with FIFO
! 440: * A0 Select with ATN and stop with FIFO
! 441: * C0 Transfer information out with FIFO
! 442: * C1 Transfer information out with DMA
! 443: * C2 Transfer information in with FIFO
! 444: * C3 Transfer information in with DMA
! 445: * 12 Initiator command complete with FIFO
! 446: * 50 Initiator transfer information out sequence without ATN with FIFO
! 447: * 70 Initiator transfer information out sequence with ATN with FIFO
! 448: * 74 Initiator transfer information out sequence with ATN3 with FIFO
! 449: * 52 Initiator transfer information in sequence without ATN with FIFO
! 450: * 72 Initiator transfer information in sequence with ATN with FIFO
! 451: * 76 Initiator transfer information in sequence with ATN3 with FIFO
! 452: * 90 Initiator transfer information out command complete with FIFO
! 453: * 92 Initiator transfer information in command complete with FIFO
! 454: * D2 Enable selection
! 455: * 08 Reselection
! 456: * 48 Disconnect command with FIFO
! 457: * 88 Terminate command with FIFO
! 458: * C8 Target command complete with FIFO
! 459: * 18 SCAM Arbitration/ Selection
! 460: * 5A Enable reselection
! 461: * 98 Select without ATN with FIFO
! 462: * B8 Select with ATN with FIFO
! 463: * D8 Message Accepted
! 464: * 58 NOP
! 465: */
! 466: #define TRM_S1040_SCSI_TIMEOUT 0x91 /* SCSI Time Out Value (R/W) */
! 467: #define TRM_S1040_SCSI_FIFO 0x98 /* SCSI FIFO (R/W) */
! 468: #define TRM_S1040_SCSI_TCR0 0x9C /* SCSI Target Control 0 (R/W) */
! 469: #define TCR0_WIDE_NEGO_DONE 0x8000 /* Wide nego done */
! 470: #define TCR0_SYNC_NEGO_DONE 0x4000 /* Synchronous nego done */
! 471: #define TCR0_ENABLE_LVDS 0x2000 /* Enable LVDS synchronous */
! 472: #define TCR0_ENABLE_WIDE 0x1000 /* Enable WIDE synchronous */
! 473: #define TCR0_ENABLE_ALT 0x0800 /* Enable alternate synchronous */
! 474: #define TCR0_PERIOD_MASK 0x0700 /* Transfer rate */
! 475: #define TCR0_DO_WIDE_NEGO 0x0080 /* Do wide NEGO */
! 476: #define TCR0_DO_SYNC_NEGO 0x0040 /* Do sync NEGO */
! 477: #define TCR0_DISCONNECT_EN 0x0020 /* Disconnection enable */
! 478: #define TCR0_OFFSET_MASK 0x001F /* Offset number */
! 479: #define TRM_S1040_SCSI_TCR1 0x9E /* SCSI Target Control 1 (R/W) */
! 480: #define MAXTAG_MASK 0x7F00 /* Maximum tags (127) */
! 481: #define NON_TAG_BUSY 0x0080 /* Non tag command active */
! 482: #define ACTTAG_MASK 0x007F /* Active tags */
! 483:
! 484: #define TRM_S1040_DMA_COMMAND 0xA0 /* DMA Command (R/W) */
! 485: #define XFERDATAIN 0x0103 /* Transfer data in */
! 486: #define XFERDATAOUT 0x0102 /* Transfer data out */
! 487: #define TRM_S1040_DMA_FIFOCNT 0xA1 /* DMA FIFO Counter (R) */
! 488: #define TRM_S1040_DMA_CONTROL 0xA1 /* DMA Control (W) */
! 489: #define STOPDMAXFER 0x08 /* Stop DMA transfer */
! 490: #define ABORTXFER 0x04 /* Abort DMA transfer */
! 491: #define CLRXFIFO 0x02 /* Clear DMA transfer FIFO */
! 492: #define STARTDMAXFER 0x01 /* Start DMA transfer */
! 493: #define TRM_S1040_DMA_STATUS 0xA3 /* DMA Interrupt Status (R/W) */
! 494: #define XFERPENDING 0x80 /* Transfer pending */
! 495: #define DMAXFERCOMP 0x02 /* Bus Master XFER Complete status */
! 496: #define SCSICOMP 0x01 /* SCSI complete interrupt */
! 497: #define TRM_S1040_DMA_INTEN 0xA4 /* DMA Interrupt Enable (R/W) */
! 498: #define EN_SCSIINTR 0x01 /* Enable SCSI complete interrupt */
! 499: #define TRM_S1040_DMA_CONFIG 0xA6 /* DMA Configuration (R/W) */
! 500: #define DMA_ENHANCE 0x8000 /* Enable DMA enhance feature */
! 501: #define TRM_S1040_DMA_XCNT 0xA8 /* DMA Transfer Counter (R/W) */
! 502: #define TRM_S1040_DMA_CXCNT 0xAC /* DMA Current Transfer Counter (R) */
! 503: #define TRM_S1040_DMA_XLOWADDR 0xB0 /* DMA Transfer Physical Low Address */
! 504: #define TRM_S1040_DMA_XHIGHADDR 0xB4 /* DMA Transfer Physical High Address */
! 505:
! 506: #define TRM_S1040_GEN_CONTROL 0xD4 /* Global Control */
! 507: #define EN_EEPROM 0x10 /* Enable EEPROM programming */
! 508: #define AUTOTERM 0x04 /* Enable Auto SCSI terminator */
! 509: #define LOW8TERM 0x02 /* Enable Lower 8 bit SCSI terminator */
! 510: #define UP8TERM 0x01 /* Enable Upper 8 bit SCSI terminator */
! 511: #define TRM_S1040_GEN_STATUS 0xD5 /* Global Status */
! 512: #define GTIMEOUT 0x80 /* Global timer reach 0 */
! 513: #define CON5068 0x10 /* External 50/68 pin connected */
! 514: #define CON68 0x08 /* Internal 68 pin connected */
! 515: #define CON50 0x04 /* Internal 50 pin connected */
! 516: #define WIDESCSI 0x02 /* Wide SCSI card */
! 517: #define TRM_S1040_GEN_NVRAM 0xD6 /* Serial NON-VOLATILE RAM port */
! 518: #define NVR_BITOUT 0x08 /* Serial data out */
! 519: #define NVR_BITIN 0x04 /* Serial data in */
! 520: #define NVR_CLOCK 0x02 /* Serial clock */
! 521: #define NVR_SELECT 0x01 /* Serial select */
! 522: #define TRM_S1040_GEN_EDATA 0xD7 /* Parallel EEPROM data port */
! 523: #define TRM_S1040_GEN_EADDRESS 0xD8 /* Parallel EEPROM address */
! 524: #define TRM_S1040_GEN_TIMER 0xDB /* Global timer */
! 525:
! 526: int trm_Interrupt(void *);
! 527: int trm_init(struct trm_softc *, int);
! 528:
! 529: #endif /* trm_h */
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