Annotation of sys/dev/ic/tcic2reg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: tcic2reg.h,v 1.2 2003/10/21 18:58:50 jmc Exp $ */
2: /* $NetBSD: tcic2reg.h,v 1.1 1999/03/23 20:04:14 bad Exp $ */
3:
4: /*-
5: * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
6: * All rights reserved.
7: *
8: * This code is derived from software contributed to The NetBSD Foundation
9: * by Christoph Badura.
10: *
11: * Redistribution and use in source and binary forms, with or without
12: * modification, are permitted provided that the following conditions
13: * are met:
14: * 1. Redistributions of source code must retain the above copyright
15: * notice, this list of conditions and the following disclaimer.
16: * 2. Redistributions in binary form must reproduce the above copyright
17: * notice, this list of conditions and the following disclaimer in the
18: * documentation and/or other materials provided with the distribution.
19: * 3. All advertising materials mentioning features or use of this software
20: * must display the following acknowledgement:
21: * This product includes software developed by the NetBSD
22: * Foundation, Inc. and its contributors.
23: * 4. Neither the name of The NetBSD Foundation nor the names of its
24: * contributors may be used to endorse or promote products derived
25: * from this software without specific prior written permission.
26: *
27: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37: * POSSIBILITY OF SUCH DAMAGE.
38: */
39:
40: /*
41: * All information is from the Databook DB86082 TCIC PC Card Controller for
42: * Notebook PCs -- Hardware Design Guide, March 22, 1994.
43: */
44:
45: #ifndef _TCIC2REG_H
46: #define _TCIC2REG_H
47: #define TCIC_IOSIZE 16
48:
49: /* TCIC primary registers */
50: #define TCIC_R_DATA 0 /* Data register, 16 bit */
51: #define TCIC_R_ADDR 2 /* Address register, 32 bit */
52: #define TCIC_R_ADDR2 (TCIC_R_ADDR+2) /* high word of addr. reg. */
53: #define TCIC_R_SCTRL 6 /* Socket control reg., 8 bit */
54: #define TCIC_R_SSTAT 7 /* Socket status reg., 8 bit */
55: #define TCIC_R_MODE 8 /* Mode register, 8 bit */
56: #define TCIC_R_PWR 9 /* Power control reg., 8 bit */
57: #define TCIC_R_EDC 0xA /* Error detect code, 16 bit */
58: #define TCIC_R_ICSR 0xC /* Interrupt ctrl/status, 8 bit */
59: #define TCIC_R_IENA 0xD /* Interrupt enable, 8 bit */
60: #define TCIC_R_AUX 0xE /* Auxiliary Register, 16 bit */
61:
62: /*
63: * TCIC auxiliary registers.
64: * These are all 16 bit registers.
65: * They are accessed by selecting the appropriate index in
66: * bits 7:5 of the mode register.
67: */
68: #define TCIC_AR_MASK 0xe0 /* for masking the mode reg. */
69: #define TCIC_AR_TCTL 0x00 /* timing control register */
70: #define TCIC_AR_PCTL 0x20 /* programming pulse ctrl. */
71: #define TCIC_AR_WCTL 0x40 /* wait state control */
72: #define TCIC_AR_EXTERN 0x60 /* external access */
73: #define TCIC_AR_PDATA 0x80 /* programming data */
74: #define TCIC_AR_SYSCFG 0xA0 /* system configuration */
75: #define TCIC_AR_ILOCK 0xC0 /* interlock control/status */
76: #define TCIC_AR_TEST 0xE0 /* test */
77:
78: /*
79: * TCIC indirect registers.
80: * These are all 16 bit.
81: * They are accessed by selecting the appropriate address in
82: * bits 9:0 of the address register with indirect register access mode
83: * enabled.
84: */
85: #define TCIC_WR_MEM_BASE 0x100 /* base address */
86: #define TCIC_WR_MEM_SHFT 3 /* log2 size of one reg set */
87: #define TCIC_WR_MEXT_N(n) ((TCIC_WR_MEM_BASE+((n)<<TCIC_WR_MEM_SHFT))+0)
88: #define TCIC_WR_MBASE_N(n) ((TCIC_WR_MEM_BASE+((n)<<TCIC_WR_MEM_SHFT))+2)
89: #define TCIC_WR_MMAP_N(n) ((TCIC_WR_MEM_BASE+((n)<<TCIC_WR_MEM_SHFT))+4)
90: #define TCIC_WR_MCTL_N(n) ((TCIC_WR_MEM_BASE+((n)<<TCIC_WR_MEM_SHFT))+6)
91:
92: #define TCIC_WR_IO_BASE 0x200 /* base address */
93: #define TCIC_WR_IO_SHFT 2 /* log2 size of one reg set */
94: #define TCIC_WR_IBASE_N(n) ((TCIC_WR_IO_BASE+((n)<<TCIC_WR_IO_SHFT))+0)
95: #define TCIC_WR_ICTL_N(n) ((TCIC_WR_IO_BASE+((n)<<TCIC_WR_IO_SHFT))+2)
96:
97: #define TCIC_IR_SCF_BASE 0 /* base address */
98: #define TCIC_IR_SCF_SHFT 3 /* log2 size of one reg set */
99: #define TCIC_IR_SCF1_N(n) ((TCIC_IR_SCF_BASE+((n)<<TCIC_IR_SCF_SHFT))+0)
100: #define TCIC_IR_SCF2_N(n) ((TCIC_IR_SCF_BASE+((n)<<TCIC_IR_SCF_SHFT))+2)
101:
102:
103: /* Bits in the ADDR2 register */
104: #define TCIC_SS_SHIFT 12 /* location of socket select bits */
105: #define TCIC_SS_MASK (7<<(TCIC_SS_SHIFT)) /* socket select mask */
106:
107: #define TCIC_ADDR2_REG (1 << 15) /* select REG space */
108: #define TCIC_ADDR2_SS_SHFT TCIC_SS_SHIFT /* select sockets the usual way */
109: #define TCIC_ADDR2_SS_MASK TCIC_SS_MASK /* ditto */
110: #define TCIC_ADDR2_INDREG (1 << 11) /* access indirect registers
111: * (not card data)
112: */
113: #define TCIC_ADDR2_IO (1 << 10) /* select I/O cycles, readback
114: * card /IORD, /IOWR in diag-
115: * nostic mode.
116: */
117:
118: /* Bits in address register */
119: #define TCIC_ADDR_REG (u_int32_t) TCIC_ADDR2_REG << 16) /* OR with this for REG space */
120: #define TCIC_ADDR_SS_SHFT ((u_int32_t) TCIC_ADDR2_SS_SHFT + 16)
121: /* shift count, cast so that
122: * you'll get the right type
123: * if you use it but forget
124: * to cast the left arg.
125: */
126: #define TCIC_ADDR_SS_MASK ((u_int32_t) TCIC_ADDR2_SS_MASK << 16)
127: #define TCIC_ADDR_INDREG ((u_int32_t) TCIC_ADDR2_INDREG << 16)
128: #define TCIC_ADDR_IO ((u_int32_t) TCIC_ADDR2_IO << 16)
129:
130: #define TCIC_ADDR_SPACE_SIZE ((u_int32_t) 1 << 26)
131: #define TCIC_ADDR_MASK (ADDR_SPACE_SIZE - 1)
132:
133: /* The following bits are defined in diagnostic mode */
134: #define TCIC_ADDR_DIAG_NREG ((u_int32_t) 1 << 31) /* inverted! */
135: #define TCIC_ADDR_DIAG_NCEH ((u_int32_t) 1 << 30)
136: #define TCIC_ADDR_DIAG_NCEL ((u_int32_t) 1 << 29)
137: #define TCIC_ADDR_DIAG_NCWR ((u_int32_t) 1 << 28)
138: #define TCIC_ADDR_DIAG_NCRD ((u_int32_t) 1 << 27)
139: #define TCIC_ADDR_DIAG_CRESET ((u_int32_t) 1 << 26)
140:
141: /* Bits in socket control register */
142: #define TCIC_SCTRL_ENA (1 << 0) /* enable access to card */
143: #define TCIC_SCTRL_INCMODE (3 << 3) /* mask for increment mode: */
144: #define TCIC_SCTRL_INCMODE_AUTO (3 << 3) /* auto-increment mode */
145: #define TCIC_SCTRL_INCMODE_HOLD (0 << 3) /* byte hold mode */
146: #define TCIC_SCTRL_INCMODE_WORD (1 << 3) /* word hold mode */
147: #define TCIC_SCTRL_INCMODE_REG (2 << 3) /* reg-space increment mode */
148: #define TCIC_SCTRL_EDCSUM (1 << 5) /* if set, use checksum (not CRC) */
149: #define TCIC_SCTRL_RESET (1 << 7) /* internal software reset */
150: #define TCIC_SCTRL_RSVD 0x46 /* reserved bits, MBZ */
151:
152: /* Bits in the socket status register */
153: #define TCIC_SSTAT_6US (1<<0) /* 6 usec have elapsed */
154: #define TCIC_SSTAT_10US (1<<1) /* 10 usec have elapsed */
155: #define TCIC_SSTAT_PROGTIME (1<<2) /* programming pulse timeout */
156: #define TCIC_SSTAT_LBAT1 (1<<3) /* low battery 1 */
157: #define TCIC_SSTAT_LBAT2 (1<<4) /* low battery 2 */
158: #define TCIC_SSTAT_BATOK (0<<3) /* battery is OK */
159: #define TCIC_SSTAT_BATBAD1 (1<<3) /* battery is low */
160: #define TCIC_SSTAT_BATLO (2<<3) /* battery is getting low */
161: #define TCIC_SSTAT_BATBAD2 (3<<3) /* battery is low */
162: #define TCIC_SSTAT_RDY (1<<5) /* card is ready (not busy) */
163: #define TCIC_SSTAT_WP (1<<6) /* card is write-protected */
164: #define TCIC_SSTAT_CD (1<<7) /* card present */
165: #define TCIC_SSTAT_STAT_MASK 0xf8
166:
167: /* Mode register contents (R_MODE) */
168: #define TCIC_MODE_PGMMASK (0x1F) /* the programming mode bits */
169: #define TCIC_MODE_NORMAL (0) /* normal mode */
170: #define TCIC_MODE_PGMWR (1 << 0) /* assert /WR */
171: #define TCIC_MODE_PGMRD (1 << 1) /* assert /RD */
172: #define TCIC_MODE_PGMCE (1 << 2) /* assert /CEx */
173: #define TCIC_MODE_PGMDBW (1 << 3) /* databus in write mode */
174: #define TCIC_MODE_PGMWORD (1 << 4) /* word programming mode */
175:
176: /* Power control register contents (R_PWR) */
177: #define TCIC_PWR_VCC_SHFT (0) /* the VCC ctl shift */
178: #define TCIC_PWR_VCC_MASK (3 << TCIC_PWR_VCC_SHFT)
179:
180: #define TCIC_PWR_VPP_SHFT (3) /* the VPP ctl shift */
181: #define TCIC_PWR_VPP_MASK (3 << TCIC_PWR_VPP_SHFT)
182: #define TCIC_PWR_ENA (1 << 5) /* on 084, successors, this
183: * must be set to turn on
184: * power.
185: */
186: #define TCIC_PWR_VCC5V (1 << 2) /* enable +5 (not +3) */
187: #if 0
188: #define TCIC_PWR_VOFF_POFF (0) /* turn off VCC, VPP */
189: #define TCIC_PWR_VON_PVCC (1) /* turn on VCC, VPP=VCC */
190: #define TCIC_PWR_VON_PVPP (2) /* turn on VCC, VPP=12V */
191: #define TCIC_PWR_VON_POFF (3) /* turn on VCC, VPP=0V */
192: #endif
193: #define TCIC_PWR_VCC_N(n) (1<<((n))) /* VCCSEL for socket n */
194: #define TCIC_PWR_VPP_N(n) (1<<(3+(n))) /* VPPSEL for socket n */
195:
196: #define TCIC_PWR_CLIMENA (1 << 6) /* the current-limit enable */
197: #define TCIC_PWR_CLIMSTAT (1 << 7) /* current limit sense (r/o) */
198:
199: /* Bits in the icsr register. */
200: #define TCIC_ICSR_IOCHK (1<<7) /* I/O check */
201: #define TCIC_ICSR_CDCHG (1<<6) /* card status change, see SSTAT */
202: #define TCIC_ICSR_ERR (1<<5) /* error condition */
203: #define TCIC_ICSR_PROGTIME (1<<4) /* program timer ding */
204: #define TCIC_ICSR_ILOCK (1<<3) /* interlock change */
205: #define TCIC_ICSR_STOPCPU (1<<2) /* Stop CPU was asserted */
206: #define TCIC_ICSR_SET (1<<1) /* (w/o) enable writes that set bits */
207: #define TCIC_ICSR_CLEAR (1<<0) /* (w/o) enable writes that clear */
208: #define TCIC_ICSR_JAM (TCIC_ICSR_SET|TCIC_ICSR_CLEAR)
209: /* jam value into ICSR */
210:
211: /* bits in the interrupt enable register */
212: #define TCIC_IENA_CDCHG (1 << 6) /* enable INT when ICSR_CDCHG is set */
213: #define TCIC_IENA_ERR (1 << 5) /* enable INT when ICSR_ERR is set */
214: #define TCIC_IENA_PROGTIME (1 << 4) /* enable INT when ICSR_PROGTIME " */
215: #define TCIC_IENA_ILOCK (1 << 3) /* enable INT when ICSR_ILOCK is set */
216: #define TCIC_IENA_CFG_MASK (3 << 0) /* select the bits for IRQ config: */
217: #define TCIC_IENA_CFG_OFF (0 << 0) /* IRQ is high-impedance */
218: #define TCIC_IENA_CFG_OD (1 << 0) /* IRQ is active low, open drain. */
219: #define TCIC_IENA_CFG_LOW (2 << 0) /* IRQ is active low, totem pole */
220: #define TCIC_IENA_CFG_HIGH (3 << 0) /* IRQ is active high, totem pole */
221: #define TCIC_IENA_RSVD 0x84 /* reserved bits, MBZ */
222:
223:
224: /*
225: * Bits in the auxiliary registers
226: */
227:
228: /* Bits in the timing control register (AR_TCTL) */
229: #define TCIC_TCTL_6US_SHFT (0) /* the shift count for the 6 us ctr */
230: #define TCIC_TCTL_10US_SHFT (8) /* the shift count for the 10 us ctr */
231: #define TCIC_TCTL_6US_MASK (0xFF << TCIC_TCTL_6US_SHFT)
232: #define TCIC_TCTL_10US_MASK (0xFF << TCIC_TCTL_10US_SHFT)
233:
234: #define TCIC_R_TCTL_6US (TCIC_R_AUX + 0) /* the byte access handle */
235: #define TCIC_R_TCTL_10US (TCIC_R_AUX + 1) /* the byte access handle */
236:
237: /* Bits in the programming pulse register (AR_PCTL) */
238: #define TCIC_R_PULSE_LO (TCIC_R_AUX + 0)
239: #define TCIC_R_PULSE_HI (TCIC_R_AUX + 1)
240:
241: /* Bits in the wait state control register (AR_WCTL) */
242: #define TCIC_WAIT_COUNT_MASK (0x1F) /* the count of 1/2 wait states */
243: #define TCIC_WAIT_COUNT_SHFT (0) /* the wait-count shift */
244: #define TCIC_WAIT_SYNC (1 << 5) /* set for synch, clear for asynch cycles */
245: #define TCIC_WAIT_ASYNC (0)
246:
247: #define TCIC_WAIT_SENSE (1 << 6) /* select rising (1) or falling (0)
248: * edge of wait clock as reference
249: * edge.
250: */
251: #define TCIC_WAIT_SRC (1 << 7) /* select constant clock (0) or bus
252: * clock (1) as the timing source
253: */
254:
255: /* Some derived constants */
256: #define TCIC_WAIT_BCLK (1 * TCIC_WAIT_SRC)
257: #define TCIC_WAIT_CCLK (0 * TCIC_WAIT_SRC)
258: #define TCIC_WAIT_RISING (1 * TCIC_WAIT_SENSE)
259: #define TCIC_WAIT_FALLING (0 * TCIC_WAIT_SENSE)
260:
261: /* high byte */
262: #define TCIC_WCTL_WR (1 << 8) /* control: pulse write */
263: #define TCIC_WCTL_RD (1 << 9) /* control: pulse read */
264: #define TCIC_WCTL_CE (1 << 10) /* control: pulse chip ena */
265: #define TCIC_WCTL_LLBAT1 (1 << 11) /* status: latched LBAT1 */
266: #define TCIC_WCTL_LLBAT2 (1 << 12) /* status: latched LBAT2 */
267: #define TCIC_WCTL_LRDY (1 << 13) /* status: latched RDY */
268: #define TCIC_WCTL_LWP (1 << 14) /* status: latched WP */
269: #define TCIC_WCTL_LCD (1 << 15) /* status: latched CD */
270:
271: /* The same thing, from a byte perspective */
272: #define TCIC_R_WCTL_WAIT (TCIC_R_AUX + 0) /* the wait state control byte */
273: #define TCIC_R_WCTL_XCSR (TCIC_R_AUX + 1) /* extended control/status */
274:
275: #define TCIC_XCSR_WR (1 << 0) /* control: pulse write */
276: #define TCIC_XCSR_RD (1 << 1) /* control: pulse read */
277: #define TCIC_XCSR_CE (1 << 2) /* control: pulse chip ena */
278: #define TCIC_XCSR_LLBAT1 (1 << 3) /* status: latched LBAT1 */
279: #define TCIC_XCSR_LLBAT2 (1 << 4) /* status: latched LBAT2 */
280: #define TCIC_XCSR_LRDY (1 << 5) /* status: latched RDY */
281: #define TCIC_XCSR_LWP (1 << 6) /* status: latched WP */
282: #define TCIC_XCSR_LCD (1 << 7) /* status: latched CD */
283: #define TCIC_XCSR_STAT_MASK 0xf8
284:
285: /* Bits in the programming data register (AR_PDATA) */
286: #define TCIC_R_PDATA_LO (TCIC_R_AUX + 0)
287: #define TCIC_R_PDATA_HI (TCIC_R_AUX + 1)
288:
289: /* Bits in the system configuration register (AR_SYSCFG) */
290: /*
291: * The bottom four bits specify the steering of the socket IRQ. On
292: * the 2N, the socket IRQ is (by default) pointed at the dedicated
293: * pin.
294: */
295: #define TCIC_SYSCFG_IRQ_MASK (0xF) /* mask for this bit field. */
296: #define TCIC_SYSCFG_SSIRQDFLT (0) /* default: use SKTIRQ (2/N)
297: * disable (2/P)
298: */
299: #define TCIC_SYSCFG_SSIRQ (0x1) /* use SKTIRQ (explicit) (2/N)
300: * do not use (2/P)
301: */
302: #define TCIC_SYSCFG_SIRQ3 (0x3) /* use IRQ3 */
303: #define TCIC_SYSCFG_SIRQ4 (0x4) /* use IRQ4 */
304: #define TCIC_SYSCFG_SIRQ5 (0x5) /* use IRQ5 (2/N) */
305: #define TCIC_SYSCFG_SIRQ6 (0x6) /* use IRQ6 (2/N) */
306: #define TCIC_SYSCFG_SIRQ7 (0x7) /* use IRQ7 (2/N) */
307: #define TCIC_SYSCFG_SIRQ10 (0xA) /* use IRQ10 */
308: #define TCIC_SYSCFG_SIRQ14 (0xE) /* use IRQ14 */
309:
310: #define TCIC_SYSCFG_MCSFULL (1 << 4)
311: /*
312: * If set, use full address (a[12:23]) for MCS16 generation.
313: * If clear, run in ISA-compatible mode (only using a[17:23]).
314: * With many chip sets, the TCIC-2/N's timing will will allow full
315: * address decoding to be used rather than limiting us to LA[17:23];
316: * thus we can get around the ISA spec which limits the granularity
317: * of bus sizing to 128K blocks.
318: */
319: #define TCIC_SYSCFG_IO1723 (1 << 5)
320: /*
321: * Flag indicating that LA[17:23] can be trusted to be zero during a
322: * true I/O cycle. Setting this bit will allow us to reduce power
323: * consumption further by eliminating I/O address broadcasts for
324: * memory cycles.
325: *
326: * Unfortunately, you cannot trust LA[17:23] to be zero on all systems,
327: * because the ISA specs do not require that LA[17:23] be zero when an
328: * alternate bus master runs an I/O cycle. However, on a palmtop or
329: * notebook, it is a good guess.
330: */
331:
332: #define TCIC_SYSCFG_MCSXB (1 << 6)
333: /*
334: * If set, assume presence of an external buffer for MCS16: operate
335: * the driver as a totem-pole output.
336: *
337: * If clear, run in pseudo-ISA mode; output is open drain. But note
338: * that on the 082 the output buffers cannot drive a 300-ohm
339: * load.
340: */
341: #define TCIC_SYSCFG_ICSXB (1 << 7)
342: /*
343: * If set, assume presence of an external buffer for IOCS16*; operate
344: * the buffer as a totem-pole output.
345: *
346: * If clear, run in pseudo-ISA mode; output is open drain. But note
347: * that on the 082 the output buffers cannot drive a 300-ohm
348: * load.
349: */
350: #define TCIC_SYSCFG_NOPDN (1 << 8)
351: /*
352: * If set, disable the auto power-down sequencing. The chip will
353: * run card cycles somewhat more quickly (though perhaps not
354: * significantly so); but it will dissipate significantly more power.
355: *
356: * If clear, the low-power operating modes are enabled. This
357: * causes the part to go into low-power mode automatically at
358: * system reset.
359: */
360: #define TCIC_SYSCFG_MPSEL_SHFT (9)
361: #define TCIC_SYSCFG_MPSEL_MASK (7 << 9)
362: /*
363: * This field controls the operation of the multipurpose pin on the
364: * 86082. It has the following codes:
365: */
366: #define TCIC_SYSCFG_MPSEL_OFF (0 << TCIC_SYSCFG_MPSEL_SHFT)
367: /*
368: * This is the reset state; it indicates that the Multi-purpose
369: * pin is not used. The pin will be held in a high-impedance
370: * state. It can be read by monitoring SYSCFG_MPSENSE.
371: */
372: #define TCIC_SYSCFG_MPSEL_NEEDCLK (1 << TCIC_SYSCFG_MPSEL_SHFT)
373: /*
374: * NMULTI is an output.
375: * External indication that CCLK or BCLK are needed in order
376: * to complete an internal operation. External logic can use
377: * this to control the clocks coming to the chip.
378: */
379: #define TCIC_SYSCFG_MPSEL_MIO (2 << TCIC_SYSCFG_MPSEL_SHFT)
380: /*
381: * NMULTI is an input; it is an unambiguous M/IO signal, issued
382: * with timing similar to the LA[] lines.
383: */
384: #define TCIC_SYSCFG_MPSEL_EXTSEL (3 << TCIC_SYSCFG_MPSEL_SHFT)
385: /*
386: * NMULTI is an output; it is the external register select
387: * pulse, generated whenever software attempts to access
388: * aux register AR_EXTRN. Of course, the 86082 will ignore
389: * writes to AR_EXTRN, and will float the data bus if
390: * the CPU reads from AR_EXTRN.
391: */
392:
393: /* (4 << TCIC_SYSCFG_MPSEL_SHFT) is reserved */
394:
395: #define TCIC_SYSCFG_MPSEL_RI (5 << TCIC_SYSCFG_MPSEL_SHFT)
396: /*
397: * NMULTI is an output; it indicates a RI (active-going)
398: * transition has occurred lately on a an appropriately-
399: * configured socket. The output is active low.
400: */
401: /*
402: * Codes 4, 6 and 7 are reserved, and must NOT be output. It is
403: * indeed possibly hazardous to your system to encode values in
404: * this field that do not match your hardware!
405: */
406:
407: /* 1 << 12 reserved */
408:
409: #define TCIC_SYSCFG_MPSENSE (1 << 13)
410: /*
411: * This bit, when read, returns the sense of the multi-purpose pin.
412: */
413:
414: #define TCIC_SYSCFG_AUTOBUSY (1 << 14)
415: /*
416: * This bit, when set, causes the busy led to be gated with the
417: * SYSCFG_ACC bit. When clear, the busy led reflects whether the
418: * socket is actually enabled. If AUTOBUSY is set and ACC is clear,
419: * then the busy light will be off, even if a socket is enabled.
420: * If AUTOBUSY is clear, then the busy light will be on if either
421: * socket is enabled.
422: *
423: * Note, that when in a programming mode, you should either clear this
424: * bit (causing the busy light to be on whenever the socket is enabled)
425: * or set both this bit and the ACC bit (causing the light to be on
426: * all the time).
427: *
428: * On the '084 and '184, this bit is per-socket.
429: */
430:
431: #define TCIC_SYSCFG_ACC (1<<15)
432: /*
433: * This bit will be set automatically by the hardware whenever the CPU
434: * accesses data on a card. It can be cleared under software control.
435: *
436: * In AUTOBUSY mode, it has the additional effect of turning on the
437: * busy light.
438: *
439: * Since we'll tristate the command lines as the card is going out of
440: * the socket, and since the shared lines idle low, there's no real
441: * danger if the busy light is off even though the socket is enabled.
442: *
443: * On the '084 and '184, this bit is per-socket.
444: */
445:
446:
447: /* Bits in the ilock aux. register. */
448: #define TCIC_ILOCK_OUT (1 << 0) /* interlock output
449: * per-socket on x84
450: */
451: #define TCIC_ILOCK_SENSE (1 << 1) /* (r/o) interlock sense
452: * 0 -> /cilock not asserted;
453: * 1 -> /cilock is asserted.
454: * per-socket on x84.
455: */
456: #define TCIC_ILOCK_CRESET (1 << 2) /* card reset output level(S) */
457: #define TCIC_ILOCK_CRESENA (1 << 3) /* enable card reset output (S) */
458: #define TCIC_ILOCK_CWAIT (1 << 4) /* enable card wait (S) */
459: #define TCIC_ILOCK_CWAITSNS (1 << 5) /* (r/o) sense current state of wait
460: * 0 -> /cwait not asserted;
461: * 1 -> /cwait is asserted
462: * (S)
463: */
464: /* The shift count & mask for the hold-time control */
465: #define TCIC_ILOCK_HOLD_SHIFT 6 /* shift count for the hold-time ctl (G) */
466: #define TCIC_ILOCK_HOLD_MASK (3 << TCIC_ILOCK_HOLD_SHIFT)
467:
468: /*
469: * Quick hold mode waits until we observe that the strobe is high,
470: * guaranteeing 10ns or so of hold time.
471: */
472: #define TCIC_ILOCK_HOLD_QUICK (0 << TCIC_ILOCK_HOLD_SHIFT)
473:
474: /*
475: * CCLK hold mode waits (asynchronously) for an edge on CCLK. Minimum is 1
476: * CCLK + epsilon; maximum is 2 CCLKs + epsilon.
477: *
478: * for the 86081 & '82, this mode enables the multi-step
479: * sequencer that generates setup and hold times based on CCLK. This
480: * is the recommended mode of operation for the '81 and '82.
481: *
482: */
483: #define TCIC_ILOCK_HOLD_CCLK (3 << TCIC_ILOCK_HOLD_SHIFT)
484:
485: /* The following bits are only present on the x84 and later parts */
486: #define TCIC_ILOCK_INPACK (1 << 11) /* (r/o, S) this bit is a diagnostic
487: * read-back for card input
488: * acknowledge.
489: * The sense is inverted from
490: * the level at the pin.
491: */
492: #define TCIC_ILOCK_CP0 (1 << 12) /* (r/o, S) this bit is a diagnostic
493: * monitor for card present pin 0.
494: * The sense is inverted from the
495: * level at the pin.
496: */
497: #define TCIC_ILOCK_CP1 (1 << 13) /* (r/o, S) this bit is a diagnostic
498: * monitor for card present pin 1.
499: * The sense is inverted from the
500: * level at the pin.
501: */
502: #define TCIC_ILOCK_VS1 (1 << 14) /* (r/o, S) this bit is the primary
503: * monitor for Card Voltage Sense
504: * pin 1.
505: * The sense is inverted from the
506: * level at the pin.
507: */
508: #define TCIC_ILOCK_VS2 (1 << 15) /* (r/o, S) this bit is the primary
509: * monitor for Card Voltage Sense
510: * pin 2.
511: * The sense is inverted from the
512: * level at the pin.
513: */
514: /*
515: * Silicon Version Register
516: *
517: * In diagnostic mode, the high byte of the interlock register is defined
518: * as the silicon identity byte.
519: *
520: * In order to read this byte, the chip must be placed in diagnostic
521: * mode by setting bit 15 of the TESTDIAG register. (This may or may
522: * not be enforced by the silicon.)
523: *
524: * The layout is:
525: *
526: * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
527: * m <-------ID-------> <----ILOCK---->
528: *
529: * The fields are:
530: *
531: * m Always reset.
532: *
533: * ID This field is one of the following:
534: *
535: * 0x02 the db86082
536: * 0x03 the db86082a
537: * 0x04 the db86084
538: * 0x05 the DB86072ES, (Engineering Sample)
539: * 0x07 the db86082bES, (Engineering Sample)
540: * 0x08 the db86084a
541: * 0x14 the DB86184
542: * 0x15 the DB86072, (Production)
543: * 0x17 the db86082b, (Production)
544: */
545:
546: /*
547: * Defines for Chip IDs described above.
548: *
549: * Use the following convention for defining TCIC_CHIPID_DBxxxxxY:
550: *
551: * TCIC_CHIPID_DBxxxxx_1 The First step of chip.
552: * TCIC_CHIPID_DBxxxxxA The Second step of chip.
553: * TCIC_CHIPID_DBxxxxxB The Third step of chip.
554: * TCIC_CHIPID_DBxxxxx... The ... step of chip.
555: *
556: * TCIC_CHIPID_DBxxxxx"step of chip"_ES An Engineering Sample of chip.
557: *
558: */
559: #define TCIC_CHIPID_DB86082_1 (0x02)
560: #define TCIC_CHIPID_DB86082A (0x03)
561: #define TCIC_CHIPID_DB86082B_ES (0x07)
562: #define TCIC_CHIPID_DB86082B (0x17)
563:
564: #define TCIC_CHIPID_DB86084_1 (0x04)
565: #define TCIC_CHIPID_DB86084A (0x08)
566:
567: #define TCIC_CHIPID_DB86184_1 (0x14)
568:
569: #define TCIC_CHIPID_DB86072_1_ES (0x05)
570: #define TCIC_CHIPID_DB86072_1 (0x15)
571:
572:
573: /* the high order bits (in diag mode) give the chip version */
574: #define TCIC_R_ILOCK_ID (TCIC_R_AUX + 1)
575:
576: #define TCIC_ILOCKTEST_ID_SHFT 8 /* the shift count */
577: #define TCIC_ILOCKTEST_ID_MASK (0x7F << TCIC_ILOCKTEST_ID_SHFT)
578: /* the mask for the field */
579: /*
580: * Use the following convention for defining TCIC_ILOCKTEST_DBxxxxxY:
581: *
582: * TCIC_ILOCKTEST_DBxxxxx_1 The First step of chip.
583: * TCIC_ILOCKTEST_DBxxxxxA The Second step of chip.
584: * TCIC_ILOCKTEST_DBxxxxxB The Third step of chip.
585: * TCIC_ILOCKTEST_DBxxxxx... The ... step of chip.
586: *
587: * TCIC_ILOCKTEST_DBxxxxx"step of chip"_ES An Engineering Sample of chip.
588: *
589: */
590: #define TCIC_ILOCKTEST_TCIC2N_1 ((TCIC_CHIPID_DB86082_1) << TCIC_ILOCKTEST_ID_SHFT)
591: #define TCIC_ILOCKTEST_DB86082_1 TCIC_ILOCKTEST_TCIC2N_1
592: #define TCIC_ILOCKTEST_TCIC2N_2 ((TCIC_CHIPID_DB86082A) << TCIC_ILOCKTEST_ID_SHFT)
593: #define TCIC_ILOCKTEST_DB86082A TCIC_ILOCKTEST_TCIC2N_2
594: #define TCIC_ILOCKTEST_TCIC2N_3 ((TCIC_CHIPID_DB86082B_ES) << TCIC_ILOCKTEST_ID_SHFT)
595: #define TCIC_ILOCKTEST_DB86082B_ES TCIC_ILOCKTEST_TCIC2N_3
596:
597: #define TCIC_ILOCKTEST_DB86082B ((TCIC_CHIPID_DB86082B) << TCIC_ILOCKTEST_ID_SHFT)
598:
599: #define TCIC_ILOCKTEST_DB86084_1 ((TCIC_CHIPID_DB86084_1) << TCIC_ILOCKTEST_ID_SHFT)
600: #define TCIC_ILOCKTEST_DB86084A ((TCIC_CHIPID_DB86084A) << TCIC_ILOCKTEST_ID_SHFT)
601:
602: #define TCIC_ILOCKTEST_DB86184_1 ((TCIC_CHIPID_DB86184_1) << TCIC_ILOCKTEST_ID_SHFT)
603:
604: #define TCIC_ILOCKTEST_DB86072_1 ((TCIC_CHIPID_DB86072_1) << TCIC_ILOCKTEST_ID_SHFT)
605: #define TCIC_ILOCKTEST_DB86072_1_ES ((TCIC_CHIPID_DB86072_1_ES) << TCIC_ILOCKTEST_ID_SHFT)
606:
607:
608: /* Bits in the test control register (AR_TEST) */
609: #define TCIC_R_TEST (TCIC_R_AUX + 0)
610: #define TCIC_TEST_AEN (1 << 0) /* force card AEN */
611: #define TCIC_TEST_CEN (1 << 1) /* force card CEN */
612: #define TCIC_TEST_CTR (1 << 2) /* test programming pulse, address ctrs */
613: #define TCIC_TEST_ENA (1 << 3) /* force card-present (for test), and
614: * special VPP test mode
615: */
616: #define TCIC_TEST_IO (1 << 4) /* feed back some I/O signals
617: * internally.
618: */
619: #define TCIC_TEST_OUT1 (1 << 5) /* force special address output mode */
620: #define TCIC_TEST_ZPB (1 << 6) /* enter ZPB test mode */
621: #define TCIC_TEST_WAIT (1 << 7) /* force-enable WAIT pin */
622: #define TCIC_TEST_PCTR (1 << 8) /* program counter in read-test mode */
623: #define TCIC_TEST_VCTL (1 << 9) /* force-enable power-supply controls */
624: #define TCIC_TEST_EXTA (1 << 10) /* external access doesn't override
625: || internal decoding.
626: */
627: #define TCIC_TEST_DRIVECDB (1 << 11) /* drive the card data bus all the time */
628: #define TCIC_TEST_ISTP (1 << 12) /* turn off CCLK to the interrupt CSR */
629: #define TCIC_TEST_BSTP (1 << 13) /* turn off BCLK internal to the chip */
630: #define TCIC_TEST_CSTP (1 << 14) /* turn off CCLK except to int CSR */
631: #define TCIC_TEST_DIAG (1 << 15) /* enable diagnostic read-back mode */
632:
633: /* Bits in the SCF1 register */
634: #define TCIC_SCF1_IRQ_MASK (0xF) /* mask for this bit field */
635: #define TCIC_SCF1_IRQOFF (0) /* disable */
636: #define TCIC_SCF1_SIRQ (0x1) /* use SKTIRQ (2/N) */
637: #define TCIC_SCF1_IRQ3 (0x3) /* use IRQ3 */
638: #define TCIC_SCF1_IRQ4 (0x4) /* use IRQ4 */
639: #define TCIC_SCF1_IRQ5 (0x5) /* use IRQ5 */
640: #define TCIC_SCF1_IRQ6 (0x6) /* use IRQ6 */
641: #define TCIC_SCF1_IRQ7 (0x7) /* use IRQ7 */
642: #define TCIC_SCF1_IRQ9 (0x9) /* use IRQ9 */
643: #define TCIC_SCF1_IRQ10 (0xA) /* use IRQ10 */
644: #define TCIC_SCF1_IRQ11 (0xB) /* use IRQ11 */
645: #define TCIC_SCF1_IRQ12 (0xC) /* use IRQ12 */
646: #define TCIC_SCF1_IRQ14 (0xE) /* use IRQ14 */
647: #define TCIC_SCF1_IRQ15 (0xF) /* use IRQ15 */
648:
649: /* XXX doc bug? -chb */
650: #define TCIC_SCF1_IRQOD (1 << 4)
651: #define TCIC_SCF1_IRQOC (0) /* selected IRQ is
652: * open-collector, and active
653: * low; otherwise it's totem-
654: * pole and active hi.
655: */
656: #define TCIC_SCF1_PCVT (1 << 5) /* convert level-mode IRQ
657: * to pulse mode, or stretch
658: * pulses from card.
659: */
660: #define TCIC_SCF1_IRDY (1 << 6) /* interrupt from RDY (not
661: * from /IREQ). Used with
662: * ATA drives.
663: */
664: #define TCIC_SCF1_ATA (1 << 7) /* Special ATA drive mode.
665: * CEL/H become CE1/2 in
666: * the IDE sense; CEL is
667: * activated for even window
668: * matches, and CEH for
669: * odd window matches.
670: */
671: #define TCIC_SCF1_DMA_SHIFT 8 /* offset to DMA selects; */
672: #define TCIC_SCF1_DMA_MASK (0x7 << IRSCFG_DMA_SHIFT)
673:
674: #define TCIC_SCF1_DMAOFF (0 << IRSCFG_DMA_SHIFT) /* disable DMA */
675: #define TCIC_SCF1_DREQ2 (2 << IRSCFG_DMA_SHIFT) /* enable DMA on DRQ2 */
676:
677: #define TCIC_SCF1_IOSTS (1 << 11) /* enable I/O status mode;
678: * allows CIORD/CIOWR to
679: * become low-Z.
680: */
681: #define TCIC_SCF1_SPKR (1 << 12) /* enable SPKR output from
682: * this card
683: */
684: #define TCIC_SCF1_FINPACK (1 << 13) /* force card input
685: * acknowledge during I/O
686: * cycles. Has no effect
687: * if no windows map to card
688: */
689: #define TCIC_SCF1_DELWR (1 << 14) /* force -all- data to
690: * meet 60ns setup time
691: * ("DELay WRite")
692: */
693: #define TCIC_SCF1_HD7IDE (1 << 15) /* Enable special IDE
694: * data register mode: odd
695: * byte addresses in odd
696: * I/O windows will not
697: * drive HD7.
698: */
699:
700: /* Bits in the scrf2 register */
701: #define TCIC_SCF2_RI (1 << 0) /* enable RI pin from STSCHG
702: * (2/N)
703: `*/
704: #define TCIC_SCF2_IDBR (1 << 1) /* force I/O data bus routing
705: * for this socket, regardless
706: * of cycle type. (2/N)
707: `*/
708: #define TCIC_SCF2_MDBR (1 << 2) /* force memory window data
709: * bus routing for this
710: * socket, regardless of cycle
711: * type. (2/N)
712: */
713: #define TCIC_SCF2_MLBAT1 (1 << 3) /* disable status change
714: * ints from LBAT1 (or
715: * "STSCHG"
716: */
717: #define TCIC_SCF2_MLBAT2 (1 << 4) /* disable status change
718: * ints from LBAT2 (or "SPKR")
719: */
720: #define TCIC_SCF2_MRDY (1 << 5) /* disable status change ints
721: * from RDY/BSY (or /IREQ).
722: * note that you get ints on
723: * both high- and low-going
724: * edges if this is enabled.
725: */
726: #define TCIC_SCF2_MWP (1 << 6) /* disable status-change ints
727: * from WP (or /IOIS16).
728: * If you're using status
729: * change ints, you better set
730: * this once an I/O window is
731: * enabled, before accessing
732: * it.
733: */
734: #define TCIC_SCF2_MCD (1 << 7) /* disable status-change ints
735: * from Card Detect.
736: */
737:
738: /*
739: * note that these bits match the top 5 bits of the socket status register
740: * in order and sense.
741: */
742: #define TCIC_SCF2_DMASRC_MASK (0x3 << 8) /* mask for this bit field */
743: /*-- DMA Source --*/
744: #define TCIC_SCF2_DRQ_BVD2 (0x0 << 8) /* BVD2 */
745: #define TCIC_SCF2_DRQ_IOIS16 (0x1 << 8) /* IOIS16 */
746: #define TCIC_SCF2_DRQ_INPACK (0x2 << 8) /* INPACK */
747: #define TCIC_SCF2_DRQ_FORCE (0x3 << 8) /* Force it */
748:
749: #define TCIC_SCFS2_RSVD (0xFC00) /* top 6 bits are RFU */
750:
751: /* Bits in the MBASE window registers */
752: #define TCIC_MBASE_4K (1 << 14) /* window size is 4K */
753: #define TCIC_MBASE_ADDR_MASK 0x0fff /* bits holding the address */
754:
755: /* Bits in the MMAP window registers */
756: #define TCIC_MMAP_ATTR (1 << 15) /* map attr or common space */
757: #define TCIC_MMAP_ADDR_MASK 0x3fff /* bits holding the address */
758:
759: /* Bits in the MCTL window registers */
760: #define TCIC_MCTL_ENA (1 << 15) /* enable this window */
761: #define TCIC_MCTL_SS_SHIFT 12
762: #define TCIC_MCTL_SS_MASK (7 << TCIC_MCTL_SS_SHIFT) /* which socket does this window map to */
763: #define TCIC_MCTL_B8 (1 << 11) /* 8/16 bit access select */
764: #define TCIC_MCTL_EDC (1 << 10) /* do EDC calc. on access */
765: #define TCIC_MCTL_KE (1 << 9) /* accesses are cacheable */
766: #define TCIC_MCTL_ACC (1 << 8) /* window has been accessed */
767: #define TCIC_MCTL_WP (1 << 7) /* window is write protected */
768: #define TCIC_MCTL_QUIET (1 << 6) /* enable quiet socket mode */
769: #define TCIC_MCTL_WSCNT_MASK 0x0f /* wait state counter */
770:
771: /* Bits in the ICTL window registers */
772: #define TCIC_ICTL_ENA (1 << 15) /* enable this windo */
773: #define TCIC_ICTL_SS_SHIFT 12
774: #define TCIC_ICTL_SS_MASK (7 << TCIC_ICTL_SS_SHIFT) /* which socket does this window map to */
775: #define TCIC_ICTL_AUTOSZ 0 /* auto size 8/16 bit acc. */
776: #define TCIC_ICTL_B8 (1 << 11) /* all accesses 8 bit */
777: #define TCIC_ICTL_B16 (1 << 10) /* all accesses 16 bit */
778: #define TCIC_ICTL_ATA (3 << 10) /* special ATA mode */
779: #define TCIC_ICTL_TINY (1 << 9) /* window size 1 byte */
780: #define TCIC_ICTL_ACC (1 << 8) /* window has been accessed */
781: #define TCIC_ICTL_1K (1 << 7) /* only 10 bits io decoding */
782: #define TCIC_ICTL_QUIET (1 << 6) /* enable quiet socket mode */
783: #define TCIC_ICTL_PASS16 (1 << 5) /* pass all 16 bits to card */
784: #define TCIC_ICTL_WSCNT_MASK 0x0f /* wait state counter */
785:
786: /* Various validity tests */
787: /*
788: * From Databook sample source:
789: * MODE_AR_SYSCFG must have, with j = ***read*** (***, R_AUX)
790: * and k = (j>>9)&7:
791: * if (k&4) k == 5
792: * And also:
793: * j&0x0f is none of 2, 8, 9, b, c, d, f
794: * if (j&8) must have (j&3 == 2)
795: * Can't have j==2
796: */
797: #if 0
798: /* this is from the Databook sample code and apparently is wrong */
799: #define INVALID_AR_SYSCFG(x) ((((x)&0x1000) && (((x)&0x0c00) != 0x0200)) \
800: || (((((x)&0x08) == 0) || (((x)&0x03) == 2)) \
801: && ((x) != 0x02)))
802: #else
803: #define INVALID_AR_SYSCFG(x) ((((x)&0x0800) && (((x)&0x0600) != 0x0100)) \
804: || ((((((x)&0x08) == 0) && (((x)&0x03) == 2)) \
805: || (((x)&0x03) == 2)) \
806: && ((x) != 0x02)))
807: #endif
808: /* AR_ILOCK must have bits 6 and 7 the same: */
809: #define INVALID_AR_ILOCK(x) (((x)&0xc0)==0 || (((x)&0xc0)==0xc0))
810:
811: /* AR_TEST has some reserved bits: */
812: #define INVALID_AR_TEST(x) (((x)&0154) != 0)
813:
814:
815: #define TCIC_IO_WINS 2
816: #define TCIC_MAX_MEM_WINS 5
817:
818: /*
819: * Memory window addresses refer to bits A23-A12 of the ISA system memory
820: * address. This is a shift of 12 bits. The LSB contains A19-A12, and the
821: * MSB contains A23-A20, plus some other bits.
822: */
823:
824: #define TCIC_MEM_SHIFT 12
825: #define TCIC_MEM_PAGESIZE (1<<TCIC_MEM_SHIFT)
826:
827: #endif /* _TCIC2REG_H */
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