Annotation of sys/dev/ic/smc83c170reg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: smc83c170reg.h,v 1.1 2005/05/10 01:16:32 brad Exp $ */
2: /* $NetBSD: smc83c170reg.h,v 1.9 2003/11/08 16:08:13 tsutsui Exp $ */
3:
4: /*-
5: * Copyright (c) 1998 The NetBSD Foundation, Inc.
6: * All rights reserved.
7: *
8: * This code is derived from software contributed to The NetBSD Foundation
9: * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
10: * NASA Ames Research Center.
11: *
12: * Redistribution and use in source and binary forms, with or without
13: * modification, are permitted provided that the following conditions
14: * are met:
15: * 1. Redistributions of source code must retain the above copyright
16: * notice, this list of conditions and the following disclaimer.
17: * 2. Redistributions in binary form must reproduce the above copyright
18: * notice, this list of conditions and the following disclaimer in the
19: * documentation and/or other materials provided with the distribution.
20: * 3. All advertising materials mentioning features or use of this software
21: * must display the following acknowledgement:
22: * This product includes software developed by the NetBSD
23: * Foundation, Inc. and its contributors.
24: * 4. Neither the name of The NetBSD Foundation nor the names of its
25: * contributors may be used to endorse or promote products derived
26: * from this software without specific prior written permission.
27: *
28: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
29: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
30: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
31: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
32: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38: * POSSIBILITY OF SUCH DAMAGE.
39: */
40:
41: #ifndef _DEV_IC_SMC83C170REG_H_
42: #define _DEV_IC_SMC83C170REG_H_
43:
44: /*
45: * Register description for the Standard Microsystems Corp. 83C170
46: * Ethernet PCI Integrated Controller (EPIC/100).
47: */
48:
49: /*
50: * EPIC transmit descriptor. Must be 4-byte aligned.
51: */
52: struct epic_txdesc {
53: u_int32_t et_txstatus; /* transmit status; see below */
54: u_int32_t et_bufaddr; /* buffer address */
55: u_int32_t et_control; /* control word; see below */
56: u_int32_t et_nextdesc; /* next descriptor pointer */
57: };
58:
59: /* et_txstatus */
60: #define TXSTAT_TXLENGTH_SHIFT 16 /* TX length in higher 16bits */
61: #define TXSTAT_TXLENGTH(x) ((x) << TXSTAT_TXLENGTH_SHIFT)
62:
63: #define ET_TXSTAT_OWNER 0x8000 /* NIC owns descriptor */
64: #define ET_TXSTAT_COLLMASK 0x1f00 /* collisions */
65: #define ET_TXSTAT_DEFERRING 0x0080 /* deferring due to jabber */
66: #define ET_TXSTAT_OOWCOLL 0x0040 /* out of window collision */
67: #define ET_TXSTAT_CDHB 0x0020 /* collision detect heartbeat */
68: #define ET_TXSTAT_UNDERRUN 0x0010 /* DMA underrun */
69: #define ET_TXSTAT_CARSENSELOST 0x0008 /* carrier lost */
70: #define ET_TXSTAT_TXWITHCOLL 0x0004 /* encountered collisions during tx */
71: #define ET_TXSTAT_NONDEFERRED 0x0002 /* transmitted without deferring */
72: #define ET_TXSTAT_PACKETTX 0x0001 /* packet transmitted successfully */
73:
74: #define TXSTAT_COLLISIONS(x) (((x) & ET_TXSTAT_COLLMASK) >> 8)
75:
76: /* et_control */
77: #define TXCTL_BUFLENGTH_MASK 0x0000ffff /* buf length in lower 16bits */
78: #define TXCTL_BUFLENGTH(x) ((x) & TXCTL_BUFLENGTH_MASK)
79:
80: #define ET_TXCTL_LASTDESC 0x00100000 /* last descriptor in frame */
81: #define ET_TXCTL_NOCRC 0x00080000 /* disable CRC generation */
82: #define ET_TXCTL_IAF 0x00040000 /* interrupt after frame */
83: #define ET_TXCTL_LFFORM 0x00020000 /* alternate fraglist format */
84: #define ET_TXCTL_FRAGLIST 0x00010000 /* descriptor points to fraglist */
85:
86: /*
87: * EPIC receive descriptor. Must be 4-byte aligned.
88: */
89: struct epic_rxdesc {
90: u_int32_t er_rxstatus; /* receive status; see below */
91: u_int32_t er_bufaddr; /* buffer address */
92: u_int32_t er_control; /* control word; see below */
93: u_int32_t er_nextdesc; /* next descriptor pointer */
94: };
95:
96: /* er_rxstatus */
97: #define RXSTAT_RXLENGTH_SHIFT 16 /* TX length in higher 16bits */
98: #define RXSTAT_RXLENGTH(x) ((x) >> RXSTAT_RXLENGTH_SHIFT)
99:
100: #define ER_RXSTAT_OWNER 0x8000 /* NIC owns descriptor */
101: #define ER_RXSTAT_HDRCOPIED 0x4000 /* rx status posted after hdr copy */
102: #define ER_RXSTAT_FRAGLISTERR 0x2000 /* ran out of frags to copy frame */
103: #define ER_RXSTAT_NETSTATVALID 0x1000 /* length and status are valid */
104: #define ER_RXSTAT_RCVRDIS 0x0040 /* receiver disabled */
105: #define ER_RXSTAT_BCAST 0x0020 /* broadcast address recognized */
106: #define ER_RXSTAT_MCAST 0x0010 /* multicast address recognized */
107: #define ER_RXSTAT_MISSEDPKT 0x0008 /* missed packet */
108: #define ER_RXSTAT_CRCERROR 0x0004 /* EPIC or MII asserted CRC error */
109: #define ER_RXSTAT_ALIGNERROR 0x0002 /* frame not byte-aligned */
110: #define ER_RXSTAT_PKTINTACT 0x0001 /* packet received without error */
111:
112: /* er_control */
113: #define RXCTL_BUFLENGTH_MASK 0x0000ffff /* buf length in lower 16bits */
114: #define RXCTL_BUFLENGTH(x) ((x) & RXCTL_BUFLENGTH_MASK)
115:
116: #define ER_RXCTL_HEADER 0x00040000 /* descriptor is for hdr copy */
117: #define ER_RXCTL_LFFORM 0x00020000 /* alternate fraglist format */
118: #define ER_RXCTL_FRAGLIST 0x00010000 /* descriptor points to fraglist */
119:
120: /*
121: * This is not really part of the register description, but we need
122: * to define the number of transmit fragments *somewhere*.
123: */
124: #define EPIC_NFRAGS 16 /* maximum number of frags in list */
125:
126: /*
127: * EPIC fraglist descriptor.
128: */
129: struct epic_fraglist {
130: u_int32_t ef_nfrags; /* number of frags in list */
131: struct {
132: u_int32_t ef_addr; /* address of frag */
133: u_int32_t ef_length; /* length of frag */
134: } ef_frags[EPIC_NFRAGS];
135: };
136:
137: /*
138: * EPIC control registers.
139: */
140:
141: #define EPIC_COMMAND 0x00 /* COMMAND */
142: #define COMMAND_TXUGO 0x00000080 /* start tx after underrun */
143: #define COMMAND_STOP_RDMA 0x00000040 /* stop rx dma */
144: #define COMMAND_STOP_TDMA 0x00000020 /* stop tx dma */
145: #define COMMAND_NEXTFRAME 0x00000010 /* move onto next rx frame */
146: #define COMMAND_RXQUEUED 0x00000008 /* queue a rx descriptor */
147: #define COMMAND_TXQUEUED 0x00000004 /* queue a tx descriptor */
148: #define COMMAND_START_RX 0x00000002 /* start receiver */
149: #define COMMAND_STOP_RX 0x00000001 /* stop receiver */
150:
151: #define EPIC_INTSTAT 0x04 /* INTERRUPT STATUS */
152: #define INTSTAT_PTA 0x08000000 /* PCI target abort */
153: #define INTSTAT_PMA 0x04000000 /* PCI master abort */
154: #define INTSTAT_APE 0x02000000 /* PCI address parity error */
155: #define INTSTAT_DPE 0x01000000 /* PCI data parity error */
156: #define INTSTAT_RSV 0x00800000 /* rx status valid */
157: #define INTSTAT_RCTS 0x00400000 /* rx copy threshold status */
158: #define INTSTAT_RBE 0x00200000 /* rx buffers empty */
159: #define INTSTAT_TCIP 0x00100000 /* tx copy in progress */
160: #define INTSTAT_RCIP 0x00080000 /* rx copy in progress */
161: #define INTSTAT_TXIDLE 0x00040000 /* transmit idle */
162: #define INTSTAT_RXIDLE 0x00020000 /* receive idle */
163: #define INTSTAT_INT_ACTV 0x00010000 /* interrupt active */
164: #define INTSTAT_GP2_INT 0x00008000 /* gpio2 low (PHY event) */
165: #define INTSTAT_FATAL_INT 0x00001000 /* fatal error occurred */
166: #define INTSTAT_RCT 0x00000800 /* rx copy threshold crossed */
167: #define INTSTAT_PREI 0x00000400 /* preemptive interrupt */
168: #define INTSTAT_CNT 0x00000200 /* counter overflow */
169: #define INTSTAT_TXU 0x00000100 /* transmit underrun */
170: #define INTSTAT_TQE 0x00000080 /* transmit queue empty */
171: #define INTSTAT_TCC 0x00000040 /* transmit chain complete */
172: #define INTSTAT_TXC 0x00000020 /* transmit complete */
173: #define INTSTAT_RXE 0x00000010 /* receive error */
174: #define INTSTAT_OVW 0x00000008 /* rx buffer overflow */
175: #define INTSTAT_RQE 0x00000004 /* receive queue empty */
176: #define INTSTAT_HCC 0x00000002 /* header copy complete */
177: #define INTSTAT_RCC 0x00000001 /* receive copy complete */
178:
179: #define EPIC_INTMASK 0x08 /* INTERRUPT MASK */
180: /* Bits 0-15 enable the corresponding interrupt in INTSTAT. */
181:
182: #define EPIC_GENCTL 0x0c /* GENERAL CONTROL */
183: #define GENCTL_RESET_PHY 0x00004000 /* reset PHY */
184: #define GENCTL_SOFT1 0x00002000 /* software use */
185: #define GENCTL_SOFT0 0x00001000 /* software use */
186: #define GENCTL_MEM_READ_CTL1 0x00000800 /* PCI memory control */
187: #define GENCTL_MEM_READ_CTL0 0x00000400 /* (see below) */
188: #define GENCTL_RX_FIFO_THRESH1 0x00000200 /* rx fifo thresh */
189: #define GENCTL_RX_FIFO_THRESH0 0x00000100 /* (see below) */
190: #define GENCTL_BIG_ENDIAN 0x00000020 /* big endian mode */
191: #define GENCTL_ONECOPY 0x00000010 /* auto-NEXTFRAME */
192: #define GENCTL_POWERDOWN 0x00000008 /* powersave sleep mode */
193: #define GENCTL_SOFTINT 0x00000004 /* software-generated intr */
194: #define GENCTL_INTENA 0x00000002 /* interrupt enable */
195: #define GENCTL_SOFTRESET 0x00000001 /* initialize EPIC */
196:
197: /*
198: * Explanation of MEMORY READ CONTROL:
199: *
200: * These bits control which PCI command the transmit DMA will use when
201: * bursting data over the PCI bus. When CTL1 is set, the transmit DMA
202: * will use the PCI "memory read line" command. When CTL0 is set, the
203: * transmit DMA will use the PCI "memory read multiple" command. When
204: * neither bit is set, the transmit DMA will use the "memory read" command.
205: * Use of "memory read line" or "memory read multiple" may enhance
206: * performance on some systems.
207: */
208:
209: /*
210: * Explanation of RECEIVE FIFO THRESHOLD:
211: *
212: * Controls the level at which the PCI burst state machine begins to
213: * empty the receive FIFO. Default is "1/2 full" (0,1).
214: *
215: * 0,0 1/4 full 32 bytes
216: * 0,1 1/2 full 64 bytes
217: * 1,0 3/4 full 96 bytes
218: * 1,1 full 128 bytes
219: */
220:
221: #define EPIC_NVCTL 0x10 /* NON-VOLATILE CONTROL */
222: #define NVCTL_IPG_DLY_MASK 0x00000780 /* interpacket delay gap */
223: #define NVCTL_CB_MODE 0x00000040 /* CardBus mode */
224: #define NVCTL_GPIO2 0x00000020 /* general purpose i/o */
225: #define NVCTL_GPIO1 0x00000010 /* ... */
226: #define NVCTL_GPOE2 0x00000008 /* general purpose output ena */
227: #define NVCTL_GPOE1 0x00000004 /* ... */
228: #define NVCTL_CLKRUNSUPP 0x00000002 /* clock run supported */
229: #define NVCTL_ENAMEMMAP 0x00000001 /* enable memory map */
230:
231: #define NVCTL_IPG_DLY(x) (((x) & NVCTL_IPG_DLY_MASK) >> 7)
232:
233: #define EPIC_EECTL 0x14 /* EEPROM CONTROL */
234: #define EECTL_EEPROMSIZE 0x00000040 /* eeprom size; see below */
235: #define EECTL_EERDY 0x00000020 /* eeprom ready */
236: #define EECTL_EEDO 0x00000010 /* eeprom data out (from) */
237: #define EECTL_EEDI 0x00000008 /* eeprom data in (to) */
238: #define EECTL_EESK 0x00000004 /* eeprom clock */
239: #define EECTL_EECS 0x00000002 /* eeprom chip select */
240: #define EECTL_ENABLE 0x00000001 /* eeprom enable */
241:
242: /*
243: * Explanation of EEPROM SIZE:
244: *
245: * Indicates the size of the serial EEPROM:
246: *
247: * 1 16x16 or 64x16
248: * 0 128x16 or 256x16
249: */
250:
251: /*
252: * Serial EEPROM opcodes, including start bit:
253: */
254: #define EPIC_EEPROM_OPC_WRITE 0x05
255: #define EPIC_EEPROM_OPC_READ 0x06
256:
257: #define EPIC_PBLCNT 0x18 /* PBLCNT */
258: #define PBLCNT_MASK 0x0000003f /* programmable burst length */
259:
260: #define EPIC_TEST 0x1c /* TEST */
261: #define TEST_CLOCKTEST 0x00000008
262:
263: #define EPIC_CRCCNT 0x20 /* CRC ERROR COUNTER */
264: #define CRCCNT_MASK 0x0000000f /* crc errs since last read */
265:
266: #define EPIC_ALICNT 0x24 /* FRAME ALIGNMENT ERROR COUNTER */
267: #define ALICNT_MASK 0x0000000f /* align errs since last read */
268:
269: #define EPIC_MPCNT 0x28 /* MISSED PACKET COUNTER */
270: #define MPCNT_MASK 0x0000000f /* miss. pkts since last read */
271:
272: #define EPIC_RXFIFO 0x2c
273:
274: #define EPIC_MMCTL 0x30 /* MII MANAGEMENT INTERFACE CONTROL */
275: #define MMCTL_PHY_ADDR_MASK 0x00003e00 /* phy address field */
276: #define MMCTL_PHY_REG_ADDR_MASK 0x000001f0 /* phy register address field */
277: #define MMCTL_RESPONDER 0x00000008 /* phy responder */
278: #define MMCTL_WRITE 0x00000002 /* write to phy */
279: #define MMCTL_READ 0x00000001 /* read from phy */
280:
281: #define MMCTL_ARG(phy, reg, cmd) (((phy) << 9) | ((reg) << 4) | (cmd))
282:
283: #define EPIC_MMDATA 0x34 /* MII MANAGEMENT INTERFACE DATA */
284: #define MMDATA_MASK 0x0000ffff /* MII frame data */
285:
286: #define EPIC_MIICFG 0x38 /* MII CONFIGURATION */
287: #define MIICFG_ALTDIR 0x00000080 /* alternate direction */
288: #define MIICFG_ALTDATA 0x00000040 /* alternate data */
289: #define MIICFG_ALTCLOCK 0x00000020 /* alternate clock source */
290: #define MIICFG_ENASER 0x00000010 /* enable serial manag intf */
291: #define MIICFG_PHYPRESENT 0x00000008 /* phy present on MII */
292: #define MIICFG_LINKSTATUS 0x00000004 /* 694 link status */
293: #define MIICFG_ENABLE 0x00000002 /* enable 694 */
294: #define MIICFG_SERMODEENA 0x00000001 /* serial mode enable */
295:
296: #define EPIC_IPG 0x3c /* INTERPACKET GAP */
297: #define IPG_INTERFRAME_MASK 0x00007f00 /* interframe gap time */
298: #define IPG_INTERPKT_MASK 0x000000ff /* interpacket gap time */
299:
300: #define EPIC_LAN0 0x40 /* LAN ADDRESS */
301:
302: #define EPIC_LAN1 0x44
303:
304: #define EPIC_LAN2 0x48
305:
306: #define LANn_MASK 0x0000ffff
307:
308: /*
309: * Explanation of LAN ADDRESS registers:
310: *
311: * LAN address is described as:
312: *
313: * 0000 [n1][n0][n3][n2] | 0000 [n5][n4][n7][n6] | 0000 [n9][n8][n11][n10]
314: *
315: * n == one nibble, mapped as follows:
316: *
317: * LAN0 [15-12] n3
318: * LAN0 [11-8] n2
319: * LAN0 [7-4] n1
320: * LAN0 [3-0] n0
321: * LAN1 [15-12] n7
322: * LAN1 [11-8] n6
323: * LAN1 [7-4] n5
324: * LAN1 [3-0] n4
325: * LAN2 [15-12] n11
326: * LAN2 [11-8] n10
327: * LAN2 [7-4] n9
328: * LAN2 [3-0] n8
329: *
330: * The LAN address is automatically recalled from the EEPROM after a
331: * hard reseet.
332: */
333:
334: #define EPIC_IDCHK 0x4c /* BOARD ID/CHECKSUM */
335: #define IDCHK_ID_MASK 0x0000ff00 /* board ID */
336: #define IDCHK_CKSUM_MASK 0x000000ff /* checksum (should be 0xff) */
337:
338: #define EPIC_MC0 0x50 /* MULTICAST ADDRESS HASH TABLE */
339:
340: #define EPIC_MC1 0x54
341:
342: #define EPIC_MC2 0x58
343:
344: #define EPIC_MC3 0x5c
345:
346: /*
347: * Explanation of MULTICAST ADDRESS HASH TABLE registers:
348: *
349: * Bits in the hash table are encoded as follows:
350: *
351: * MC0 [15-0]
352: * MC1 [31-16]
353: * MC2 [47-32]
354: * MC3 [53-48]
355: */
356:
357: #define EPIC_RXCON 0x60 /* RECEIVE CONTROL */
358: #define RXCON_EXTBUFSIZESEL1 0x00000200 /* ext buf size; see below */
359: #define RXCON_EXTBUFSIZESEL0 0x00000100 /* ... */
360: #define RXCON_EARLYRXENABLE 0x00000080 /* early receive enable */
361: #define RXCON_MONITORMODE 0x00000040 /* monitor mode */
362: #define RXCON_PROMISCMODE 0x00000020 /* promiscuous mode */
363: #define RXCON_RXINVADDR 0x00000010 /* rx inv individual addr */
364: #define RXCON_RXMULTICAST 0x00000008 /* receive multicast */
365: #define RXCON_RXBROADCAST 0x00000004 /* receive broadcast */
366: #define RXCON_RXRUNT 0x00000002 /* receive runt frames */
367: #define RXCON_SAVEERRPKTS 0x00000001 /* save errored packets */
368:
369: /*
370: * Explanation of EXTERNAL BUFFER SIZE SELECT:
371: *
372: * 0,0 external buffer access is disabled
373: * 0,1 16k
374: * 1,0 32k
375: * 1,1 128k
376: */
377:
378: #define EPIC_RXSTAT 0x64 /* RECEIVE STATUS */
379:
380: #define EPIC_RXCNT 0x68
381:
382: #define EPIC_RXTEST 0x6c
383:
384: #define EPIC_TXCON 0x70 /* TRANSMIT CONTROL */
385: #define TXCON_SLOTTIME_MASK 0x000000f8 /* slot time */
386: #define TXCON_LOOPBACK_D2 0x00000004 /* loopback mode bit 2 */
387: #define TXCON_LOOPBACK_D1 0x00000002 /* loopback mode bit 1 */
388: #define TXCON_EARLYTX_ENABLE 0x00000001 /* early transmit enable */
389:
390: /*
391: * Explanation of LOOPBACK MODE BIT:
392: *
393: * 0,0 normal operation
394: * 0,1 internal loopback (before PHY)
395: * 1,0 external loopback (after PHY)
396: * 1,1 full duplex - decouples transmit and receive blocks
397: */
398:
399: #define EPIC_TXSTAT 0x74 /* TRANSMIT STATUS */
400:
401: #define EPIC_TDPAR 0x78
402:
403: #define EPIC_TXTEST 0x7c
404:
405: #define EPIC_PRFDAR 0x80
406:
407: #define EPIC_PRCDAR 0x84 /* PCI RECEIVE CURRENT DESCRIPTOR ADDR */
408:
409: #define EPIC_PRHDAR 0x88
410:
411: #define EPIC_PRFLAR 0x8c
412:
413: #define EPIC_PRDLGTH 0x90
414:
415: #define EPIC_PRFCNT 0x94
416:
417: #define EPIC_PRLCAR 0x98
418:
419: #define EPIC_PRLPAR 0x9c
420:
421: #define EPIC_PREFAR 0xa0
422:
423: #define EPIC_PRSTAT 0xa4 /* PCI RECEIVE DMA STATUS */
424:
425: #define EPIC_PRBUF 0xa8
426:
427: #define EPIC_RDNCAR 0xac
428:
429: #define EPIC_PRCPTHR 0xb0 /* PCI RECEIVE COPY THRESHOLD */
430:
431: #define EPIC_ROMDATA 0xb4
432:
433: #define EPIC_PREEMPR 0xbc
434:
435: #define EPIC_PTFDAR 0xc0
436:
437: #define EPIC_PTCDAR 0xc4 /* PCI TRANSMIT CURRENT DESCRIPTOR ADDR */
438:
439: #define EPIC_PTHDAR 0xc8
440:
441: #define EPIC_PTFLAR 0xcc
442:
443: #define EPIC_PTDLGTH 0xd0
444:
445: #define EPIC_PTFCNT 0xd4
446:
447: #define EPIC_PTLCAR 0xd8
448:
449: #define EPIC_ETXTHR 0xdc /* EARLY TRANSMIT THRESHOLD */
450:
451: #define EPIC_PTETXC 0xe0
452:
453: #define EPIC_PTSTAT 0xe4
454:
455: #define EPIC_PTBUF 0xe8
456:
457: #define EPIC_PTFDAR2 0xec
458:
459: #define EPIC_FEVTR 0xf0 /* FEVTR (CardBus) */
460:
461: #define EPIC_FEVTRMSKR 0xf4 /* FEVTRMSKR (CardBus) */
462:
463: #define EPIC_FPRSTSTR 0xf8 /* FPRSTR (CardBus) */
464:
465: #define EPIC_FFRCEVTR 0xfc /* PPRCEVTR (CardBus) */
466:
467: /*
468: * EEPROM format:
469: *
470: * Word Bits Description
471: * ---- ---- -----------
472: * 0 7-0 LAN Address Byte 0
473: * 0 15-8 LAN Address Byte 1
474: * 1 7-0 LAN Address Byte 2
475: * 1 15-8 LAN Address Byte 3
476: * 2 7-0 LAN Address Byte 4
477: * 2 15-8 LAN Address Byte 5
478: * 3 7-0 Board ID
479: * 3 15-8 Checksum
480: * 4 5-0 Non-Volatile Control Register Contents
481: * 5 7-0 PCI Minimum Grant Desired Setting
482: * 5 15-8 PCI Maximum Latency Desired Setting
483: * 6 15-0 Subsystem Vendor ID
484: * 7 14-0 Subsystem ID
485: */
486:
487: #endif /* _DEV_IC_SMC83C170REG_H_ */
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