Annotation of sys/dev/ic/s3_617.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: s3_617.h,v 1.2 2001/07/04 09:03:04 niklas Exp $ */
! 2:
! 3: /*
! 4: * Copyright (c) 1998 Constantine Paul Sapuntzakis
! 5: * All rights reserved
! 6: *
! 7: * Author: Constantine Paul Sapuntzakis (csapuntz@cvs.openbsd.org)
! 8: *
! 9: * Redistribution and use in source and binary forms, with or without
! 10: * modification, are permitted provided that the following conditions
! 11: * are met:
! 12: * 1. Redistributions of source code must retain the above copyright
! 13: * notice, this list of conditions and the following disclaimer.
! 14: * 2. Redistributions in binary form must reproduce the above copyright
! 15: * notice, this list of conditions and the following disclaimer in the
! 16: * documentation and/or other materials provided with the distribution.
! 17: * 3. The author's name or those of the contributors may be used to
! 18: * endorse or promote products derived from this software without
! 19: * specific prior written permission.
! 20: *
! 21: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR(S) AND CONTRIBUTORS
! 22: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
! 23: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
! 24: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
! 25: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
! 26: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
! 27: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
! 28: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
! 29: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
! 30: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
! 31: * POSSIBILITY OF SUCH DAMAGE.
! 32: */
! 33:
! 34: /*
! 35: * PCI BIOS Configuration area ports
! 36: */
! 37:
! 38: enum {
! 39: SV_SB_PORTBASE_SLOT = 0x10,
! 40: SV_ENHANCED_PORTBASE_SLOT = 0x14,
! 41: SV_FM_PORTBASE_SLOT = 0x18,
! 42: SV_MIDI_PORTBASE_SLOT = 0x1c,
! 43: SV_GAME_PORTBASE_SLOT = 0x20
! 44: };
! 45:
! 46: /*
! 47: * Enhanced CODEC registers
! 48: * These are offset from the base specified in the PCI configuration area
! 49: */
! 50: enum { SV_CODEC_CONTROL = 0,
! 51: SV_CODEC_INTMASK = 1,
! 52: SV_CODEC_STATUS = 2,
! 53: SV_CODEC_IADDR = 4,
! 54: SV_CODEC_IDATA = 5 };
! 55:
! 56:
! 57: /*
! 58: * DMA Configuration register
! 59: */
! 60:
! 61: enum {
! 62: SV_DMAA_CONFIG_OFF = 0x40,
! 63: SV_DMAC_CONFIG_OFF = 0x48
! 64: };
! 65:
! 66: enum {
! 67: SV_DMA_CHANNEL_ENABLE = 0x1,
! 68: SV_DMAA_EXTENDED_ADDR = 0x8,
! 69: SV_DMA_PORTBASE_MASK = 0xFFFFFFF0
! 70: };
! 71:
! 72:
! 73: enum {
! 74: SV_DMA_ADDR0 = 0,
! 75: SV_DMA_ADDR1 = 1,
! 76: SV_DMA_ADDR2 = 2,
! 77: SV_DMA_ADDR3 = 3,
! 78: SV_DMA_COUNT0 = 4,
! 79: SV_DMA_COUNT1 = 5,
! 80: SV_DMA_COUNT2 = 6,
! 81: SV_DMA_CMDSTATUS = 8,
! 82: SV_DMA_MODE = 0xB,
! 83: SV_DMA_MASTERCLEAR = 0xD,
! 84: SV_DMA_MASK = 0xF
! 85: };
! 86:
! 87:
! 88: /*
! 89: * DMA Mode (see reg 0xB)
! 90: */
! 91:
! 92: enum {
! 93: SV_DMA_MODE_IOR_MASK = 0x0C,
! 94: SV_DMA_MODE_IOW_MASK = 0x0C,
! 95: SV_DMA_MODE_IOR = 0x04,
! 96: SV_DMA_MODE_IOW = 0x08,
! 97: SV_DMA_MODE_AUTOINIT = 0x10
! 98: };
! 99:
! 100: #define SET_FIELD(reg, field) ((reg & ~(field##_MASK)) | field)
! 101: #define GET_FIELD(reg, field) (reg & ~(field##_MASK))
! 102:
! 103: enum {
! 104: SV_CTL_ENHANCED = 1,
! 105: SV_CTL_FWS = 0x08,
! 106: SV_CTL_INTA = 0x20,
! 107: SV_CTL_RESET = 0x80
! 108: };
! 109:
! 110: enum {
! 111: SV_INTMASK_DMAA = 0x1,
! 112: SV_INTMASK_DMAC = 0x4,
! 113: SV_INTMASK_SINT = 0x8,
! 114: SV_INTMASK_UD = 0x40,
! 115: SV_INTMASK_MIDI = 0x80
! 116: };
! 117:
! 118: enum {
! 119: SV_INTSTATUS_DMAA = 0x1,
! 120: SV_INTSTATUS_DMAC = 0x4,
! 121: SV_INTSTATUS_SINT = 0x8,
! 122: SV_INTSTATUS_UD = 0x40,
! 123: SV_INTSTATUS_MIDI = 0x80
! 124: };
! 125:
! 126: enum {
! 127: SV_IADDR_MASK = 0x3f,
! 128: SV_IADDR_MCE = 0x40,
! 129: /* TRD = DMA Transfer request disable */
! 130: SV_IADDR_TRD = 0x80
! 131: };
! 132:
! 133:
! 134: enum {
! 135: SV_LEFT_ADC_INPUT_CONTROL = 0x0,
! 136: SV_RIGHT_ADC_INPUT_CONTROL = 0x1,
! 137: SV_LEFT_AUX1_INPUT_CONTROL = 0x2,
! 138: SV_RIGHT_AUX1_INPUT_CONTROL = 0x3,
! 139: SV_LEFT_CD_INPUT_CONTROL = 0x4,
! 140: SV_RIGHT_CD_INPUT_CONTROL = 0x5,
! 141: SV_LEFT_LINE_IN_INPUT_CONTROL = 0x6,
! 142: SV_RIGHT_LINE_IN_INPUT_CONTROL = 0x7,
! 143: SV_MIC_INPUT_CONTROL = 0x8,
! 144: SV_GAME_PORT_CONTROL = 0x9,
! 145: SV_LEFT_SYNTH_INPUT_CONTROL = 0x0A,
! 146: SV_RIGHT_SYNTH_INPUT_CONTROL = 0x0B,
! 147: SV_LEFT_AUX2_INPUT_CONTROL = 0x0C,
! 148: SV_RIGHT_AUX2_INPUT_CONTROL = 0x0D,
! 149: SV_LEFT_MIXER_OUTPUT_CONTROL = 0x0E,
! 150: SV_RIGHT_MIXER_OUTPUT_CONTROL = 0x0F,
! 151: SV_LEFT_PCM_INPUT_CONTROL = 0x10,
! 152: SV_RIGHT_PCM_INPUT_CONTROL = 0x11,
! 153: SV_DMA_DATA_FORMAT = 0x12,
! 154: SV_PLAY_RECORD_ENABLE = 0x13,
! 155: SV_UP_DOWN_CONTROL = 0x14,
! 156: SV_REVISION_LEVEL = 0x15,
! 157: SV_MONITOR_CONTROL = 0x16,
! 158: SV_DMAA_COUNT1 = 0x18,
! 159: SV_DMAA_COUNT0 = 0x19,
! 160: SV_DMAC_COUNT1 = 0x1C,
! 161: SV_DMAC_COUNT0 = 0x1d,
! 162: SV_PCM_SAMPLE_RATE_0 = 0x1e,
! 163: SV_PCM_SAMPLE_RATE_1 = 0x1f,
! 164: SV_SYNTH_SAMPLE_RATE_0 = 0x20,
! 165: SV_SYNTH_SAMPLE_RATE_1 = 0x21,
! 166: SV_ADC_CLOCK_SOURCE = 0x22,
! 167: SV_ADC_ALT_SAMPLE_RATE = 0x23,
! 168: SV_ADC_PLL_M = 0x24,
! 169: SV_ADC_PLL_N = 0x25,
! 170: SV_SYNTH_PLL_M = 0x26,
! 171: SV_SYNTH_PLL_N = 0x27,
! 172: SV_MPU401 = 0x2A,
! 173: SV_DRIVE_CONTROL = 0x2B,
! 174: SV_SRS_SPACE_CONTROL = 0x2c,
! 175: SV_SRS_CENTER_CONTROL = 0x2d,
! 176: SV_WAVETABLE_SOURCE_SELECT = 0x2e,
! 177: SV_ANALOG_POWER_DOWN_CONTROL = 0x30,
! 178: SV_DIGITAL_POWER_DOWN_CONTROL = 0x31
! 179: };
! 180:
! 181: enum {
! 182: SV_MUTE_BIT = 0x80,
! 183: SV_AUX1_MASK = 0x1F,
! 184: SV_CD_MASK = 0x1F,
! 185: SV_LINE_IN_MASK = 0x1F,
! 186: SV_MIC_MASK = 0x0F,
! 187: SV_SYNTH_MASK = 0x1F,
! 188: SV_AUX2_MASK = 0x1F,
! 189: SV_MIXER_OUT_MASK = 0x1F,
! 190: SV_PCM_MASK = 0x3F
! 191: };
! 192:
! 193: enum {
! 194: SV_DMAA_STEREO = 0x1,
! 195: SV_DMAA_FORMAT16 = 0x2,
! 196: SV_DMAC_STEREO = 0x10,
! 197: SV_DMAC_FORMAT16 = 0x20
! 198: };
! 199:
! 200: enum {
! 201: SV_PLAY_ENABLE = 0x1,
! 202: SV_RECORD_ENABLE = 0x2
! 203: };
! 204:
! 205: enum {
! 206: SV_PLL_R_SHIFT = 5
! 207: };
! 208:
! 209: /* ADC input source (registers 0 & 1) */
! 210: enum {
! 211: SV_REC_SOURCE_MASK = 0xE0,
! 212: SV_REC_SOURCE_SHIFT = 5,
! 213: SV_MIC_BOOST_BIT = 0x10,
! 214: SV_REC_GAIN_MASK = 0x0F,
! 215: SV_REC_CD = 1,
! 216: SV_REC_DAC = 2,
! 217: SV_REC_AUX2 = 3,
! 218: SV_REC_LINE = 4,
! 219: SV_REC_AUX1 = 5,
! 220: SV_REC_MIC = 6,
! 221: SV_REC_MIXER = 7
! 222: };
! 223:
! 224: /* SRS Space control register (reg 0x2C) */
! 225:
! 226: enum {
! 227: SV_SRS_SPACE_ONOFF = 0x80
! 228: };
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