Annotation of sys/dev/ic/rt2560reg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: rt2560reg.h,v 1.5 2006/11/13 20:06:38 damien Exp $ */
! 2:
! 3: /*-
! 4: * Copyright (c) 2005, 2006
! 5: * Damien Bergamini <damien.bergamini@free.fr>
! 6: *
! 7: * Permission to use, copy, modify, and distribute this software for any
! 8: * purpose with or without fee is hereby granted, provided that the above
! 9: * copyright notice and this permission notice appear in all copies.
! 10: *
! 11: * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
! 12: * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
! 13: * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
! 14: * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
! 15: * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
! 16: * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
! 17: * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
! 18: */
! 19:
! 20: #define RT2560_TX_RING_COUNT 48
! 21: #define RT2560_ATIM_RING_COUNT 4
! 22: #define RT2560_PRIO_RING_COUNT 16
! 23: #define RT2560_BEACON_RING_COUNT 1
! 24: #define RT2560_RX_RING_COUNT 32
! 25:
! 26: #define RT2560_TX_DESC_SIZE (sizeof (struct rt2560_tx_desc))
! 27: #define RT2560_RX_DESC_SIZE (sizeof (struct rt2560_rx_desc))
! 28:
! 29: #define RT2560_MAX_SCATTER 1
! 30:
! 31: /*
! 32: * Control and status registers.
! 33: */
! 34: #define RT2560_CSR0 0x0000 /* ASIC version number */
! 35: #define RT2560_CSR1 0x0004 /* System control */
! 36: #define RT2560_CSR3 0x000c /* STA MAC address 0 */
! 37: #define RT2560_CSR4 0x0010 /* STA MAC address 1 */
! 38: #define RT2560_CSR5 0x0014 /* BSSID 0 */
! 39: #define RT2560_CSR6 0x0018 /* BSSID 1 */
! 40: #define RT2560_CSR7 0x001c /* Interrupt source */
! 41: #define RT2560_CSR8 0x0020 /* Interrupt mask */
! 42: #define RT2560_CSR9 0x0024 /* Maximum frame length */
! 43: #define RT2560_SECCSR0 0x0028 /* WEP control */
! 44: #define RT2560_CSR11 0x002c /* Back-off control */
! 45: #define RT2560_CSR12 0x0030 /* Synchronization configuration 0 */
! 46: #define RT2560_CSR13 0x0034 /* Synchronization configuration 1 */
! 47: #define RT2560_CSR14 0x0038 /* Synchronization control */
! 48: #define RT2560_CSR15 0x003c /* Synchronization status */
! 49: #define RT2560_CSR16 0x0040 /* TSF timer 0 */
! 50: #define RT2560_CSR17 0x0044 /* TSF timer 1 */
! 51: #define RT2560_CSR18 0x0048 /* IFS timer 0 */
! 52: #define RT2560_CSR19 0x004c /* IFS timer 1 */
! 53: #define RT2560_CSR20 0x0050 /* WAKEUP timer */
! 54: #define RT2560_CSR21 0x0054 /* EEPROM control */
! 55: #define RT2560_CSR22 0x0058 /* CFP control */
! 56: #define RT2560_TXCSR0 0x0060 /* TX control */
! 57: #define RT2560_TXCSR1 0x0064 /* TX configuration */
! 58: #define RT2560_TXCSR2 0x0068 /* TX descriptor configuration */
! 59: #define RT2560_TXCSR3 0x006c /* TX ring base address */
! 60: #define RT2560_TXCSR4 0x0070 /* TX ATIM ring base address */
! 61: #define RT2560_TXCSR5 0x0074 /* TX PRIO ring base address */
! 62: #define RT2560_TXCSR6 0x0078 /* Beacon base address */
! 63: #define RT2560_TXCSR7 0x007c /* AutoResponder control */
! 64: #define RT2560_RXCSR0 0x0080 /* RX control */
! 65: #define RT2560_RXCSR1 0x0084 /* RX descriptor configuration */
! 66: #define RT2560_RXCSR2 0x0088 /* RX ring base address */
! 67: #define RT2560_PCICSR 0x008c /* PCI control */
! 68: #define RT2560_RXCSR3 0x0090 /* BBP ID 0 */
! 69: #define RT2560_TXCSR9 0x0094 /* OFDM TX BBP */
! 70: #define RT2560_ARSP_PLCP_0 0x0098 /* Auto Responder PLCP address */
! 71: #define RT2560_ARSP_PLCP_1 0x009c /* Auto Responder Basic Rate mask */
! 72: #define RT2560_CNT0 0x00a0 /* FCS error counter */
! 73: #define RT2560_CNT1 0x00ac /* PLCP error counter */
! 74: #define RT2560_CNT2 0x00b0 /* Long error counter */
! 75: #define RT2560_CNT3 0x00b8 /* CCA false alarm counter */
! 76: #define RT2560_CNT4 0x00bc /* RX FIFO Overflow counter */
! 77: #define RT2560_CNT5 0x00c0 /* Tx FIFO Underrun counter */
! 78: #define RT2560_PWRCSR0 0x00c4 /* Power mode configuration */
! 79: #define RT2560_PSCSR0 0x00c8 /* Power state transition time */
! 80: #define RT2560_PSCSR1 0x00cc /* Power state transition time */
! 81: #define RT2560_PSCSR2 0x00d0 /* Power state transition time */
! 82: #define RT2560_PSCSR3 0x00d4 /* Power state transition time */
! 83: #define RT2560_PWRCSR1 0x00d8 /* Manual power control/status */
! 84: #define RT2560_TIMECSR 0x00dc /* Timer control */
! 85: #define RT2560_MACCSR0 0x00e0 /* MAC configuration */
! 86: #define RT2560_MACCSR1 0x00e4 /* MAC configuration */
! 87: #define RT2560_RALINKCSR 0x00e8 /* Ralink RX auto-reset BBCR */
! 88: #define RT2560_BCNCSR 0x00ec /* Beacon interval control */
! 89: #define RT2560_BBPCSR 0x00f0 /* BBP serial control */
! 90: #define RT2560_RFCSR 0x00f4 /* RF serial control */
! 91: #define RT2560_LEDCSR 0x00f8 /* LED control */
! 92: #define RT2560_SECCSR3 0x00fc /* XXX not documented */
! 93: #define RT2560_DMACSR0 0x0100 /* Current RX ring address */
! 94: #define RT2560_DMACSR1 0x0104 /* Current Tx ring address */
! 95: #define RT2560_DMACSR2 0x0104 /* Current Priority ring address */
! 96: #define RT2560_DMACSR3 0x0104 /* Current ATIM ring address */
! 97: #define RT2560_TXACKCSR0 0x0110 /* XXX not documented */
! 98: #define RT2560_GPIOCSR 0x0120 /* */
! 99: #define RT2560_BBBPPCSR 0x0124 /* BBP Pin Control */
! 100: #define RT2560_FIFOCSR0 0x0128 /* TX FIFO pointer */
! 101: #define RT2560_FIFOCSR1 0x012c /* RX FIFO pointer */
! 102: #define RT2560_BCNOCSR 0x0130 /* Beacon time offset */
! 103: #define RT2560_RLPWCSR 0x0134 /* RX_PE Low Width */
! 104: #define RT2560_TESTCSR 0x0138 /* Test Mode Select */
! 105: #define RT2560_PLCP1MCSR 0x013c /* Signal/Service/Length of ACK @1M */
! 106: #define RT2560_PLCP2MCSR 0x0140 /* Signal/Service/Length of ACK @2M */
! 107: #define RT2560_PLCP5p5MCSR 0x0144 /* Signal/Service/Length of ACK @5.5M */
! 108: #define RT2560_PLCP11MCSR 0x0148 /* Signal/Service/Length of ACK @11M */
! 109: #define RT2560_ACKPCTCSR 0x014c /* ACK/CTS padload consume time */
! 110: #define RT2560_ARTCSR1 0x0150 /* ACK/CTS padload consume time */
! 111: #define RT2560_ARTCSR2 0x0154 /* ACK/CTS padload consume time */
! 112: #define RT2560_SECCSR1 0x0158 /* WEP control */
! 113: #define RT2560_BBPCSR1 0x015c /* BBP TX Configuration */
! 114:
! 115:
! 116: /* possible flags for register RXCSR0 */
! 117: #define RT2560_DISABLE_RX (1 << 0)
! 118: #define RT2560_DROP_CRC_ERROR (1 << 1)
! 119: #define RT2560_DROP_PHY_ERROR (1 << 2)
! 120: #define RT2560_DROP_CTL (1 << 3)
! 121: #define RT2560_DROP_NOT_TO_ME (1 << 4)
! 122: #define RT2560_DROP_TODS (1 << 5)
! 123: #define RT2560_DROP_VERSION_ERROR (1 << 6)
! 124:
! 125: /* possible flags for register CSR1 */
! 126: #define RT2560_RESET_ASIC (1 << 0)
! 127: #define RT2560_RESET_BBP (1 << 1)
! 128: #define RT2560_HOST_READY (1 << 2)
! 129:
! 130: /* possible flags for register CSR14 */
! 131: #define RT2560_ENABLE_TSF (1 << 0)
! 132: #define RT2560_ENABLE_TSF_SYNC(x) (((x) & 0x3) << 1)
! 133: #define RT2560_ENABLE_TBCN (1 << 3)
! 134: #define RT2560_ENABLE_BEACON_GENERATOR (1 << 6)
! 135:
! 136: /* possible flags for register CSR21 */
! 137: #define RT2560_C (1 << 1)
! 138: #define RT2560_S (1 << 2)
! 139: #define RT2560_D (1 << 3)
! 140: #define RT2560_Q (1 << 4)
! 141: #define RT2560_93C46 (1 << 5)
! 142:
! 143: #define RT2560_SHIFT_D 3
! 144: #define RT2560_SHIFT_Q 4
! 145:
! 146: /* possible flags for register TXCSR0 */
! 147: #define RT2560_KICK_TX (1 << 0)
! 148: #define RT2560_KICK_ATIM (1 << 1)
! 149: #define RT2560_KICK_PRIO (1 << 2)
! 150: #define RT2560_ABORT_TX (1 << 3)
! 151:
! 152: /* possible flags for register SECCSR0 */
! 153: #define RT2560_KICK_DECRYPT (1 << 0)
! 154:
! 155: /* possible flags for register SECCSR1 */
! 156: #define RT2560_KICK_ENCRYPT (1 << 0)
! 157:
! 158: /* possible flags for register CSR7 */
! 159: #define RT2560_BEACON_EXPIRE 0x00000001
! 160: #define RT2560_WAKEUP_EXPIRE 0x00000002
! 161: #define RT2560_ATIM_EXPIRE 0x00000004
! 162: #define RT2560_TX_DONE 0x00000008
! 163: #define RT2560_ATIM_DONE 0x00000010
! 164: #define RT2560_PRIO_DONE 0x00000020
! 165: #define RT2560_RX_DONE 0x00000040
! 166: #define RT2560_DECRYPTION_DONE 0x00000080
! 167: #define RT2560_ENCRYPTION_DONE 0x00000100
! 168:
! 169: #define RT2560_INTR_MASK \
! 170: (~(RT2560_BEACON_EXPIRE | RT2560_WAKEUP_EXPIRE | RT2560_TX_DONE | \
! 171: RT2560_PRIO_DONE | RT2560_RX_DONE | RT2560_DECRYPTION_DONE | \
! 172: RT2560_ENCRYPTION_DONE))
! 173:
! 174: /* Tx descriptor */
! 175: struct rt2560_tx_desc {
! 176: uint32_t flags;
! 177: #define RT2560_TX_BUSY (1 << 0)
! 178: #define RT2560_TX_VALID (1 << 1)
! 179:
! 180: #define RT2560_TX_RESULT_MASK 0x0000001c
! 181: #define RT2560_TX_SUCCESS (0 << 2)
! 182: #define RT2560_TX_SUCCESS_RETRY (1 << 2)
! 183: #define RT2560_TX_FAIL_RETRY (2 << 2)
! 184: #define RT2560_TX_FAIL_INVALID (3 << 2)
! 185: #define RT2560_TX_FAIL_OTHER (4 << 2)
! 186:
! 187: #define RT2560_TX_MORE_FRAG (1 << 8)
! 188: #define RT2560_TX_NEED_ACK (1 << 9)
! 189: #define RT2560_TX_TIMESTAMP (1 << 10)
! 190: #define RT2560_TX_OFDM (1 << 11)
! 191: #define RT2560_TX_CIPHER_BUSY (1 << 12)
! 192:
! 193: #define RT2560_TX_IFS_MASK 0x00006000
! 194: #define RT2560_TX_IFS_BACKOFF (0 << 13)
! 195: #define RT2560_TX_IFS_SIFS (1 << 13)
! 196: #define RT2560_TX_IFS_NEWBACKOFF (2 << 13)
! 197: #define RT2560_TX_IFS_NONE (3 << 13)
! 198:
! 199: #define RT2560_TX_LONG_RETRY (1 << 15)
! 200:
! 201: #define RT2560_TX_CIPHER_MASK 0xe0000000
! 202: #define RT2560_TX_CIPHER_NONE (0 << 29)
! 203: #define RT2560_TX_CIPHER_WEP40 (1 << 29)
! 204: #define RT2560_TX_CIPHER_WEP104 (2 << 29)
! 205: #define RT2560_TX_CIPHER_TKIP (3 << 29)
! 206: #define RT2560_TX_CIPHER_AES (4 << 29)
! 207:
! 208: uint32_t physaddr;
! 209: uint16_t wme;
! 210: #define RT2560_LOGCWMAX(x) (((x) & 0xf) << 12)
! 211: #define RT2560_LOGCWMIN(x) (((x) & 0xf) << 8)
! 212: #define RT2560_AIFSN(x) (((x) & 0x3) << 6)
! 213: #define RT2560_IVOFFSET(x) (((x) & 0x3f))
! 214:
! 215: uint16_t reserved1;
! 216: uint8_t plcp_signal;
! 217: uint8_t plcp_service;
! 218: #define RT2560_PLCP_LENGEXT 0x80
! 219:
! 220: uint8_t plcp_length_lo;
! 221: uint8_t plcp_length_hi;
! 222: uint32_t iv;
! 223: uint32_t eiv;
! 224: uint8_t key[IEEE80211_KEYBUF_SIZE];
! 225: uint32_t reserved2[2];
! 226: } __packed;
! 227:
! 228: /* Rx descriptor */
! 229: struct rt2560_rx_desc {
! 230: uint32_t flags;
! 231: #define RT2560_RX_BUSY (1 << 0)
! 232: #define RT2560_RX_CRC_ERROR (1 << 5)
! 233: #define RT2560_RX_OFDM (1 << 6)
! 234: #define RT2560_RX_PHY_ERROR (1 << 7)
! 235: #define RT2560_RX_CIPHER_BUSY (1 << 8)
! 236: #define RT2560_RX_ICV_ERROR (1 << 9)
! 237:
! 238: #define RT2560_RX_CIPHER_MASK 0xe0000000
! 239: #define RT2560_RX_CIPHER_NONE (0 << 29)
! 240: #define RT2560_RX_CIPHER_WEP40 (1 << 29)
! 241: #define RT2560_RX_CIPHER_WEP104 (2 << 29)
! 242: #define RT2560_RX_CIPHER_TKIP (3 << 29)
! 243: #define RT2560_RX_CIPHER_AES (4 << 29)
! 244:
! 245: uint32_t physaddr;
! 246: uint8_t rate;
! 247: uint8_t rssi;
! 248: uint8_t ta[IEEE80211_ADDR_LEN];
! 249: uint32_t iv;
! 250: uint32_t eiv;
! 251: uint8_t key[IEEE80211_KEYBUF_SIZE];
! 252: uint32_t reserved[2];
! 253: } __packed;
! 254:
! 255: #define RT2560_RF1 0
! 256: #define RT2560_RF2 2
! 257: #define RT2560_RF3 1
! 258: #define RT2560_RF4 3
! 259:
! 260: #define RT2560_RF1_AUTOTUNE 0x08000
! 261: #define RT2560_RF3_AUTOTUNE 0x00040
! 262:
! 263: #define RT2560_BBP_BUSY (1 << 15)
! 264: #define RT2560_BBP_WRITE (1 << 16)
! 265: #define RT2560_RF_20BIT (20 << 24)
! 266: #define RT2560_RF_BUSY (1 << 31)
! 267:
! 268: #define RT2560_RF_2522 0x00
! 269: #define RT2560_RF_2523 0x01
! 270: #define RT2560_RF_2524 0x02
! 271: #define RT2560_RF_2525 0x03
! 272: #define RT2560_RF_2525E 0x04
! 273: #define RT2560_RF_2526 0x05
! 274: /* dual-band RF */
! 275: #define RT2560_RF_5222 0x10
! 276:
! 277: #define RT2560_BBP_VERSION 0
! 278: #define RT2560_BBP_TX 2
! 279: #define RT2560_BBP_RX 14
! 280:
! 281: #define RT2560_BBP_ANTA 0x00
! 282: #define RT2560_BBP_DIVERSITY 0x01
! 283: #define RT2560_BBP_ANTB 0x02
! 284: #define RT2560_BBP_ANTMASK 0x03
! 285: #define RT2560_BBP_FLIPIQ 0x04
! 286:
! 287: #define RT2560_LED_MODE_DEFAULT 0
! 288: #define RT2560_LED_MODE_TXRX_ACTIVITY 1
! 289: #define RT2560_LED_MODE_SINGLE 2
! 290: #define RT2560_LED_MODE_ASUS 3
! 291:
! 292: #define RT2560_JAPAN_FILTER 0x8
! 293:
! 294: #define RT2560_EEPROM_CONFIG0 16
! 295: #define RT2560_EEPROM_BBP_BASE 19
! 296: #define RT2560_EEPROM_TXPOWER 35
! 297:
! 298: #define RT2560_EEPROM_DELAY 1 /* minimum hold time (microsecond) */
! 299:
! 300: /*
! 301: * control and status registers access macros
! 302: */
! 303: #define RAL_READ(sc, reg) \
! 304: bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
! 305:
! 306: #define RAL_WRITE(sc, reg, val) \
! 307: bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
! 308:
! 309: /*
! 310: * EEPROM access macro
! 311: */
! 312: #define RT2560_EEPROM_CTL(sc, val) do { \
! 313: RAL_WRITE((sc), RT2560_CSR21, (val)); \
! 314: DELAY(RT2560_EEPROM_DELAY); \
! 315: } while (/* CONSTCOND */0)
! 316:
! 317:
! 318: /*
! 319: * Default values for MAC registers; values taken from the reference driver.
! 320: */
! 321: #define RT2560_DEF_MAC \
! 322: { RT2560_PSCSR0, 0x00020002 }, \
! 323: { RT2560_PSCSR1, 0x00000002 }, \
! 324: { RT2560_PSCSR2, 0x00020002 }, \
! 325: { RT2560_PSCSR3, 0x00000002 }, \
! 326: { RT2560_TIMECSR, 0x00003f21 }, \
! 327: { RT2560_CSR9, 0x00000780 }, \
! 328: { RT2560_CSR11, 0x07041483 }, \
! 329: { RT2560_CNT3, 0x00000000 }, \
! 330: { RT2560_TXCSR1, 0x07614562 }, \
! 331: { RT2560_ARSP_PLCP_0, 0x8c8d8b8a }, \
! 332: { RT2560_ACKPCTCSR, 0x7038140a }, \
! 333: { RT2560_ARTCSR1, 0x1d21252d }, \
! 334: { RT2560_ARTCSR2, 0x1919191d }, \
! 335: { RT2560_RXCSR0, 0xffffffff }, \
! 336: { RT2560_RXCSR3, 0xb3aab3af }, \
! 337: { RT2560_PCICSR, 0x000003b8 }, \
! 338: { RT2560_PWRCSR0, 0x3f3b3100 }, \
! 339: { RT2560_GPIOCSR, 0x0000ff00 }, \
! 340: { RT2560_TESTCSR, 0x000000f0 }, \
! 341: { RT2560_PWRCSR1, 0x000001ff }, \
! 342: { RT2560_MACCSR0, 0x00213223 }, \
! 343: { RT2560_MACCSR1, 0x00235518 }, \
! 344: { RT2560_RLPWCSR, 0x00000040 }, \
! 345: { RT2560_RALINKCSR, 0x9a009a11 }, \
! 346: { RT2560_CSR7, 0xffffffff }, \
! 347: { RT2560_BBPCSR1, 0x82188200 }, \
! 348: { RT2560_TXACKCSR0, 0x00000020 }, \
! 349: { RT2560_SECCSR3, 0x0000e78f }
! 350:
! 351: /*
! 352: * Default values for BBP registers; values taken from the reference driver.
! 353: */
! 354: #define RT2560_DEF_BBP \
! 355: { 3, 0x02 }, \
! 356: { 4, 0x19 }, \
! 357: { 14, 0x1c }, \
! 358: { 15, 0x30 }, \
! 359: { 16, 0xac }, \
! 360: { 17, 0x48 }, \
! 361: { 18, 0x18 }, \
! 362: { 19, 0xff }, \
! 363: { 20, 0x1e }, \
! 364: { 21, 0x08 }, \
! 365: { 22, 0x08 }, \
! 366: { 23, 0x08 }, \
! 367: { 24, 0x80 }, \
! 368: { 25, 0x50 }, \
! 369: { 26, 0x08 }, \
! 370: { 27, 0x23 }, \
! 371: { 30, 0x10 }, \
! 372: { 31, 0x2b }, \
! 373: { 32, 0xb9 }, \
! 374: { 34, 0x12 }, \
! 375: { 35, 0x50 }, \
! 376: { 39, 0xc4 }, \
! 377: { 40, 0x02 }, \
! 378: { 41, 0x60 }, \
! 379: { 53, 0x10 }, \
! 380: { 54, 0x18 }, \
! 381: { 56, 0x08 }, \
! 382: { 57, 0x10 }, \
! 383: { 58, 0x08 }, \
! 384: { 61, 0x60 }, \
! 385: { 62, 0x10 }, \
! 386: { 75, 0xff }
! 387:
! 388: /*
! 389: * Default values for RF register R2 indexed by channel numbers; values taken
! 390: * from the reference driver.
! 391: */
! 392: #define RT2560_RF2522_R2 \
! 393: { \
! 394: 0x307f6, 0x307fb, 0x30800, 0x30805, 0x3080a, 0x3080f, 0x30814, \
! 395: 0x30819, 0x3081e, 0x30823, 0x30828, 0x3082d, 0x30832, 0x3083e \
! 396: }
! 397:
! 398: #define RT2560_RF2523_R2 \
! 399: { \
! 400: 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, \
! 401: 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 \
! 402: }
! 403:
! 404: #define RT2560_RF2524_R2 \
! 405: { \
! 406: 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, \
! 407: 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 \
! 408: }
! 409:
! 410: #define RT2560_RF2525_R2 \
! 411: { \
! 412: 0x20327, 0x20328, 0x20329, 0x2032a, 0x2032b, 0x2032c, 0x2032d, \
! 413: 0x2032e, 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20346 \
! 414: }
! 415:
! 416: #define RT2560_RF2525_HI_R2 \
! 417: { \
! 418: 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20344, 0x20345, \
! 419: 0x20346, 0x20347, 0x20348, 0x20349, 0x2034a, 0x2034b, 0x2034e \
! 420: }
! 421:
! 422: #define RT2560_RF2525E_R2 \
! 423: { \
! 424: 0x2044d, 0x2044e, 0x2044f, 0x20460, 0x20461, 0x20462, 0x20463, \
! 425: 0x20464, 0x20465, 0x20466, 0x20467, 0x20468, 0x20469, 0x2046b \
! 426: }
! 427:
! 428: #define RT2560_RF2526_HI_R2 \
! 429: { \
! 430: 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d, 0x0022d, \
! 431: 0x0022e, 0x0022e, 0x0022f, 0x0022d, 0x00240, 0x00240, 0x00241 \
! 432: }
! 433:
! 434: #define RT2560_RF2526_R2 \
! 435: { \
! 436: 0x00226, 0x00227, 0x00227, 0x00228, 0x00228, 0x00229, 0x00229, \
! 437: 0x0022a, 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d \
! 438: }
! 439:
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