Annotation of sys/dev/ic/oosiopreg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: oosiopreg.h,v 1.1 2004/03/12 00:04:57 miod Exp $ */
! 2: /* $NetBSD: oosiopreg.h,v 1.3 2003/11/02 11:07:45 wiz Exp $ */
! 3:
! 4: /*
! 5: * Copyright (c) 1990 The Regents of the University of California.
! 6: * All rights reserved.
! 7: *
! 8: * This code is derived from software contributed to Berkeley by
! 9: * Van Jacobson of Lawrence Berkeley Laboratory.
! 10: *
! 11: * Redistribution and use in source and binary forms, with or without
! 12: * modification, are permitted provided that the following conditions
! 13: * are met:
! 14: * 1. Redistributions of source code must retain the above copyright
! 15: * notice, this list of conditions and the following disclaimer.
! 16: * 2. Redistributions in binary form must reproduce the above copyright
! 17: * notice, this list of conditions and the following disclaimer in the
! 18: * documentation and/or other materials provided with the distribution.
! 19: * 3. Neither the name of the University nor the names of its contributors
! 20: * may be used to endorse or promote products derived from this software
! 21: * without specific prior written permission.
! 22: *
! 23: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
! 24: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
! 25: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
! 26: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
! 27: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
! 28: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
! 29: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
! 30: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
! 31: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
! 32: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
! 33: * SUCH DAMAGE.
! 34: *
! 35: * @(#)siopreg.h 7.3 (Berkeley) 2/5/91
! 36: */
! 37:
! 38: /*
! 39: * NCR 53C700 SCSI interface hardware description.
! 40: *
! 41: * From the Mach scsi driver for the 53C700 and amiga siop driver
! 42: */
! 43:
! 44: #define OOSIOP_SCNTL0 0x00 /* rw: SCSI control reg 0 */
! 45: #define OOSIOP_SCNTL1 0x01 /* rw: SCSI control reg 1 */
! 46: #define OOSIOP_SDID 0x02 /* rw: SCSI destination ID */
! 47: #define OOSIOP_SIEN 0x03 /* rw: SCSI interrupt enable */
! 48: #define OOSIOP_SCID 0x04 /* rw: SCSI Chip ID reg */
! 49: #define OOSIOP_SXFER 0x05 /* rw: SCSI Transfer reg */
! 50: #define OOSIOP_SODL 0x06 /* rw: SCSI Output Data Latch */
! 51: #define OOSIOP_SOCL 0x07 /* rw: SCSI Output Control Latch */
! 52: #define OOSIOP_SFBR 0x08 /* ro: SCSI First Byte Received */
! 53: #define OOSIOP_SIDL 0x09 /* ro: SCSI Input Data Latch */
! 54: #define OOSIOP_SBDL 0x0a /* ro: SCSI Bus Data Lines */
! 55: #define OOSIOP_SBCL 0x0b /* rw: SCSI Bus Control Lines */
! 56: #define OOSIOP_DSTAT 0x0c /* ro: DMA status */
! 57: #define OOSIOP_SSTAT0 0x0d /* ro: SCSI status reg 0 */
! 58: #define OOSIOP_SSTAT1 0x0e /* ro: SCSI status reg 1 */
! 59: #define OOSIOP_SSTAT2 0x0f /* ro: SCSI status reg 2 */
! 60: #define OOSIOP_SCRA0 0x10 /* rw: Scratch A */
! 61: #define OOSIOP_SCRA1 0x11
! 62: #define OOSIOP_SCRA2 0x12
! 63: #define OOSIOP_SCRA3 0x13
! 64: #define OOSIOP_CTEST0 0x14 /* ro: Chip test register 0 */
! 65: #define OOSIOP_CTEST1 0x15 /* ro: Chip test register 1 */
! 66: #define OOSIOP_CTEST2 0x16 /* ro: Chip test register 2 */
! 67: #define OOSIOP_CTEST3 0x17 /* ro: Chip test register 3 */
! 68: #define OOSIOP_CTEST4 0x18 /* rw: Chip test register 4 */
! 69: #define OOSIOP_CTEST5 0x19 /* rw: Chip test register 5 */
! 70: #define OOSIOP_CTEST6 0x1a /* rw: Chip test register 6 */
! 71: #define OOSIOP_CTEST7 0x1b /* rw: Chip test register 7 */
! 72: #define OOSIOP_TEMP 0x1c /* rw: Temporary Stack reg */
! 73: #define OOSIOP_DFIFO 0x20 /* rw: DMA FIFO */
! 74: #define OOSIOP_ISTAT 0x21 /* rw: Interrupt Status reg */
! 75: #define OOSIOP_CTEST8 0x22 /* rw: Chip test register 8 */
! 76: #define OOSIOP_CTEST9 0x23 /* ro: Chip test register 9 */
! 77: #define OOSIOP_DBC 0x24 /* rw: DMA Byte Counter reg */
! 78: #define OOSIOP_DCMD 0x27 /* rw: DMA Command Register */
! 79: #define OOSIOP_DNAD 0x28 /* rw: DMA Next Address */
! 80: #define OOSIOP_DSP 0x2c /* rw: DMA SCRIPTS Pointer reg */
! 81: #define OOSIOP_DSPS 0x30 /* rw: DMA SCRIPTS Pointer Save reg */
! 82: #define OOSIOP_DMODE 0x34 /* rw: DMA Mode reg */
! 83: #define OOSIOP_RES35 0x35
! 84: #define OOSIOP_RES36 0x36
! 85: #define OOSIOP_RES37 0x37
! 86: #define OOSIOP_RES38 0x38
! 87: #define OOSIOP_DIEN 0x39 /* rw: DMA Interrupt Enable */
! 88: #define OOSIOP_DWT 0x3a /* rw: DMA Watchdog Timer */
! 89: #define OOSIOP_DCNTL 0x3b /* rw: DMA Control reg */
! 90: #define OOSIOP_SCRB0 0x3c /* rw: Scratch B */
! 91: #define OOSIOP_SCRB1 0x3d
! 92: #define OOSIOP_SCRB2 0x3e
! 93: #define OOSIOP_SCRB3 0x3f
! 94:
! 95: #define OOSIOP_NREGS 0x40
! 96:
! 97:
! 98: /*
! 99: * Register defines
! 100: */
! 101:
! 102: /* Scsi control register 0 (scntl0) */
! 103:
! 104: #define OOSIOP_SCNTL0_ARB 0xc0 /* Arbitration mode */
! 105: #define OOSIOP_ARB_SIMPLE 0x00
! 106: #define OOSIOP_ARB_FULL 0xc0
! 107: #define OOSIOP_SCNTL0_START 0x20 /* Start Sequence */
! 108: #define OOSIOP_SCNTL0_WATN 0x10 /* (Select) With ATN */
! 109: #define OOSIOP_SCNTL0_EPC 0x08 /* Enable Parity Checking */
! 110: #define OOSIOP_SCNTL0_EPG 0x04 /* Enable Parity Generation */
! 111: #define OOSIOP_SCNTL0_AAP 0x02 /* Assert ATN on Parity Error */
! 112: #define OOSIOP_SCNTL0_TRG 0x01 /* Target Mode */
! 113:
! 114: /* Scsi control register 1 (scntl1) */
! 115:
! 116: #define OOSIOP_SCNTL1_EXC 0x80 /* Extra Clock Cycle of data setup */
! 117: #define OOSIOP_SCNTL1_ADB 0x40 /* Assert Data Bus */
! 118: #define OOSIOP_SCNTL1_ESR 0x20 /* Enable Selection/Reselection */
! 119: #define OOSIOP_SCNTL1_CON 0x10 /* Connected */
! 120: #define OOSIOP_SCNTL1_RST 0x08 /* Assert RST */
! 121: #define OOSIOP_SCNTL1_AESP 0x04 /* Assert even SCSI parity */
! 122: #define OOSIOP_SCNTL1_SND 0x02 /* Start Send operation */
! 123: #define OOSIOP_SCNTL1_RCV 0x01 /* Start Receive operation */
! 124:
! 125: /* Scsi interrupt enable register (sien) */
! 126:
! 127: #define OOSIOP_SIEN_M_A 0x80 /* Phase Mismatch or ATN active */
! 128: #define OOSIOP_SIEN_FC 0x40 /* Function Complete */
! 129: #define OOSIOP_SIEN_STO 0x20 /* (Re)Selection timeout */
! 130: #define OOSIOP_SIEN_SEL 0x10 /* (Re)Selected */
! 131: #define OOSIOP_SIEN_SGE 0x08 /* SCSI Gross Error */
! 132: #define OOSIOP_SIEN_UDC 0x04 /* Unexpected Disconnect */
! 133: #define OOSIOP_SIEN_RST 0x02 /* RST asserted */
! 134: #define OOSIOP_SIEN_PAR 0x01 /* Parity Error */
! 135:
! 136: /* Scsi chip ID (scid) */
! 137:
! 138: #define OOSIOP_SCID_VALUE(i) (1 << i)
! 139:
! 140: /* Scsi transfer register (sxfer) */
! 141:
! 142: #define OOSIOP_SXFER_DHP 0x80 /* Disable Halt on Parity error/
! 143: ATN asserted */
! 144: #define OOSIOP_SXFER_TP 0x70 /* Synch Transfer Period */
! 145: /* see specs for formulas:
! 146: Period = TCP * (4 + XFERP )
! 147: TCP = 1 + CLK + 1..2;
! 148: */
! 149: #define OOSIOP_SXFER_MO 0x0f /* Synch Max Offset */
! 150: #define OOSIOP_MAX_OFFSET 8
! 151:
! 152: /* Scsi output data latch register (sodl) */
! 153:
! 154: /* Scsi output control latch register (socl) */
! 155:
! 156: #define OOSIOP_REQ 0x80 /* SCSI signal <x> asserted */
! 157: #define OOSIOP_ACK 0x40
! 158: #define OOSIOP_BSY 0x20
! 159: #define OOSIOP_SEL 0x10
! 160: #define OOSIOP_ATN 0x08
! 161: #define OOSIOP_MSG 0x04
! 162: #define OOSIOP_CD 0x02
! 163: #define OOSIOP_IO 0x01
! 164:
! 165: #define OOSIOP_PHASE(socl) SCSI_PHASE(socl)
! 166:
! 167: /* Scsi first byte received register (sfbr) */
! 168:
! 169: /* Scsi input data latch register (sidl) */
! 170:
! 171: /* Scsi bus data lines register (sbdl) */
! 172:
! 173: /* Scsi bus control lines register (sbcl). Same as socl */
! 174:
! 175: #define OOSIOP_SBCL_SSCF1 0x02 /* wo */
! 176: #define OOSIOP_SBCL_SSCF0 0x01 /* wo */
! 177:
! 178: /* DMA status register (dstat) */
! 179:
! 180: #define OOSIOP_DSTAT_DFE 0x80 /* DMA FIFO empty */
! 181: #define OOSIOP_DSTAT_ABRT 0x10 /* Aborted */
! 182: #define OOSIOP_DSTAT_SSI 0x08 /* SCRIPT Single Step */
! 183: #define OOSIOP_DSTAT_SIR 0x04 /* SCRIPT Interrupt Instruction */
! 184: #define OOSIOP_DSTAT_WTD 0x02 /* Watchdog Timeout Detected */
! 185: #define OOSIOP_DSTAT_IID 0x01 /* Invalid Instruction Detected */
! 186:
! 187: /* Scsi status register 0 (sstat0) */
! 188:
! 189: #define OOSIOP_SSTAT0_M_A 0x80 /* Phase Mismatch or ATN active */
! 190: #define OOSIOP_SSTAT0_FC 0x40 /* Function Complete */
! 191: #define OOSIOP_SSTAT0_STO 0x20 /* (Re)Selection timeout */
! 192: #define OOSIOP_SSTAT0_SEL 0x10 /* (Re)Selected */
! 193: #define OOSIOP_SSTAT0_SGE 0x08 /* SCSI Gross Error */
! 194: #define OOSIOP_SSTAT0_UDC 0x04 /* Unexpected Disconnect */
! 195: #define OOSIOP_SSTAT0_RST 0x02 /* RST asserted */
! 196: #define OOSIOP_SSTAT0_PAR 0x01 /* Parity Error */
! 197:
! 198: /* Scsi status register 1 (sstat1) */
! 199:
! 200: #define OOSIOP_SSTAT1_ILF 0x80 /* Input latch (sidl) full */
! 201: #define OOSIOP_SSTAT1_ORF 0x40 /* output reg (sodr) full */
! 202: #define OOSIOP_SSTAT1_OLF 0x20 /* output latch (sodl) full */
! 203: #define OOSIOP_SSTAT1_AIP 0x10 /* Arbitration in progress */
! 204: #define OOSIOP_SSTAT1_LOA 0x08 /* Lost arbitration */
! 205: #define OOSIOP_SSTAT1_WOA 0x04 /* Won arbitration */
! 206: #define OOSIOP_SSTAT1_RST 0x02 /* SCSI RST current value */
! 207: #define OOSIOP_SSTAT1_SDP 0x01 /* SCSI SDP current value */
! 208:
! 209: /* Scsi status register 2 (sstat2) */
! 210:
! 211: #define OOSIOP_SSTAT2_FF 0xf0 /* SCSI FIFO flags (bytecount) */
! 212: #define OOSIOP_SCSI_FIFO_DEEP 8
! 213: #define OOSIOP_SSTAT2_SDP 0x08 /* Latched (on REQ) SCSI SDP */
! 214: #define OOSIOP_SSTAT2_MSG 0x04 /* Latched SCSI phase */
! 215: #define OOSIOP_SSTAT2_CD 0x02
! 216: #define OOSIOP_SSTAT2_IO 0x01
! 217:
! 218: /* Chip test register 0 (ctest0) */
! 219:
! 220: #define OOSIOP_CTEST0_RTRG 0x02 /* Real Target Mode */
! 221: #define OOSIOP_CTEST0_DDIR 0x01 /* Xfer direction (1-> from SCSI bus) */
! 222:
! 223: /* Chip test register 1 (ctest1) */
! 224:
! 225: #define OOSIOP_CTEST1_FMT 0xf0 /* Byte empty in DMA FIFO bottom
! 226: (high->byte3) */
! 227: #define OOSIOP_CTEST1_FFL 0x0f /* Byte full in DMA FIFO top, same */
! 228:
! 229: /* Chip test register 2 (ctest2) */
! 230:
! 231: #define OOSIOP_CTEST2_SOFF 0x20 /* Synch Offset compare
! 232: (1-> zero Init, max Tgt) */
! 233: #define OOSIOP_CTEST2_SFP 0x10 /* SCSI FIFO Parity */
! 234: #define OOSIOP_CTEST2_DFP 0x08 /* DMA FIFO Parity */
! 235: #define OOSIOP_CTEST2_TEOP 0x04 /* True EOP (a-la 5380) */
! 236: #define OOSIOP_CTEST2_DREQ 0x02 /* DREQ status */
! 237: #define OOSIOP_CTEST2_DACK 0x01 /* DACK status */
! 238:
! 239: /* Chip test register 3 (ctest3) read-only, top of SCSI FIFO */
! 240:
! 241: /* Chip test register 4 (ctest4) */
! 242:
! 243: #define OOSIOP_CTEST4_ZMOD 0x40 /* High-impedance outputs */
! 244: #define OOSIOP_CTEST4_SZM 0x20 /* ditto, SCSI "outputs" */
! 245: #define OOSIOP_CTEST4_SLBE 0x10 /* SCSI loopback enable */
! 246: #define OOSIOP_CTEST4_SFWR 0x08 /* SCSI FIFO write enable (from sodl) */
! 247: #define OOSIOP_CTEST4_FBL 0x07 /* DMA FIFO Byte Lane select
! 248: (from ctest6) 4->0, .. 7->3 */
! 249:
! 250: /* Chip test register 5 (ctest5) */
! 251:
! 252: #define OOSIOP_CTEST5_ADCK 0x80 /* Clock Address Incrementor */
! 253: #define OOSIOP_CTEST5_BBCK 0x40 /* Clock Byte counter */
! 254: #define OOSIOP_CTEST5_ROFF 0x20 /* Reset SCSI offset */
! 255: #define OOSIOP_CTEST5_MASR 0x10 /* Master set/reset pulses
! 256: (of bits 3-0) */
! 257: #define OOSIOP_CTEST5_DDIR 0x08 /* (re)set internal DMA direction */
! 258: #define OOSIOP_CTEST5_EOP 0x04 /* (re)set internal EOP */
! 259: #define OOSIOP_CTEST5_DREQ 0x02 /* (re)set internal REQ */
! 260: #define OOSIOP_CTEST5_DACK 0x01 /* (re)set internal ACK */
! 261:
! 262: /* Chip test register 6 (ctest6) DMA FIFO access */
! 263:
! 264: /* Chip test register 7 (ctest7) */
! 265:
! 266: #define OOSIOP_CTEST7_STD 0x10 /* Selection timeout disable */
! 267: #define OOSIOP_CTEST7_DFP 0x08 /* DMA FIFO parity bit */
! 268: #define OOSIOP_CTEST7_EVP 0x04 /* Even parity (to host bus) */
! 269: #define OOSIOP_CTEST7_DIFF 0x01 /* Differential mode */
! 270:
! 271: /* DMA FIFO register (dfifo) */
! 272:
! 273: #define OOSIOP_DFIFO_FLF 0x80 /* Flush (spill) DMA FIFO */
! 274: #define OOSIOP_DFIFO_CLF 0x40 /* Clear DMA and SCSI FIFOs */
! 275: #define OOSIOP_DFIFO_BO 0x3f /* FIFO byte offset counter */
! 276:
! 277: /* Interrupt status register (istat) */
! 278:
! 279: #define OOSIOP_ISTAT_ABRT 0x80 /* Abort operation */
! 280: #define OOSIOP_ISTAT_CON 0x08 /* Connected */
! 281: #define OOSIOP_ISTAT_PRE 0x04 /* Pointer register empty */
! 282: #define OOSIOP_ISTAT_SIP 0x02 /* SCSI Interrupt pending */
! 283: #define OOSIOP_ISTAT_DIP 0x01 /* DMA Interrupt pending */
! 284:
! 285: /* Chip test register 8 (ctest8) */
! 286:
! 287: /* DMA Byte Counter register (dbc) */
! 288: #define OOSIOP_DBC_MAX 0x00ffffff
! 289:
! 290: /* DMA Mode register (dmode) */
! 291:
! 292: #define OOSIOP_DMODE_BL_MASK 0xc0 /* 0->1 1->2 2->4 3->8 */
! 293: #define OOSIOP_DMODE_BL_1 0x00
! 294: #define OOSIOP_DMODE_BL_2 0x40
! 295: #define OOSIOP_DMODE_BL_4 0x80
! 296: #define OOSIOP_DMODE_BL_8 0xc0
! 297: #define OOSIOP_DMODE_BW16 0x20 /* Bus Width is 16 bits */
! 298: #define OOSIOP_DMODE_286 0x10 /* 286 mode */
! 299: #define OOSIOP_DMODE_IO_M 0x08 /* xfer data to memory or I/O space */
! 300: #define OOSIOP_DMODE_FAM 0x04 /* fixed address mode */
! 301: #define OOSIOP_DMODE_PIPE 0x02 /* SCRIPTS in Pipeline mode */
! 302: #define OOSIOP_DMODE_MAN 0x01 /* SCRIPTS in Manual start mode */
! 303:
! 304: /* DMA interrupt enable register (dien) */
! 305:
! 306: #define OOSIOP_DIEN_BF 0x20 /* On Bus Fault */
! 307: #define OOSIOP_DIEN_ABRT 0x10 /* On Abort */
! 308: #define OOSIOP_DIEN_SSI 0x08 /* On SCRIPTS sstep */
! 309: #define OOSIOP_DIEN_SIR 0x04 /* On SCRIPTS intr instruction */
! 310: #define OOSIOP_DIEN_WTD 0x02 /* On watchdog timeout */
! 311: #define OOSIOP_DIEN_IID 0x01 /* On illegal instruction detected */
! 312:
! 313: /* DMA control register (dcntl) */
! 314:
! 315: #define OOSIOP_DCNTL_CF_MASK 0xc0 /* Clock frequency dividers: */
! 316: #define OOSIOP_DCNTL_CF_2 0x00 /* 0 --> 37.51..50.00 MHz, div=2 */
! 317: #define OOSIOP_DCNTL_CF_1_5 0x40 /* 1 --> 25.01..37.50 MHz, div=1.5 */
! 318: #define OOSIOP_DCNTL_CF_1 0x80 /* 2 --> 16.67..25.00 MHz, div=1 */
! 319: #define OOSIOP_DCNTL_CF_3 0xc0 /* 3 --> 50.01..66.67 MHz, div=3 */
! 320: #define OOSIOP_DCNTL_S16 0x20 /* SCRIPTS fetches 16bits at a time */
! 321: #define OOSIOP_DCNTL_SSM 0x10 /* Single step mode */
! 322: #define OOSIOP_DCNTL_LLM 0x08 /* Enable SCSI Low-level mode */
! 323: #define OOSIOP_DCNTL_STD 0x04 /* Start DMA operation */
! 324: #define OOSIOP_DCNTL_RST 0x01 /* Software reset */
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