Annotation of sys/dev/ic/ncr53c9xvar.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: ncr53c9xvar.h,v 1.17 2006/06/26 22:16:23 miod Exp $ */
2: /* $NetBSD: ncr53c9xvar.h,v 1.13 1998/05/26 23:17:34 thorpej Exp $ */
3:
4: /*-
5: * Copyright (c) 1997 The NetBSD Foundation, Inc.
6: * All rights reserved.
7: *
8: * This code is derived from software contributed to The NetBSD Foundation
9: * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
10: * NASA Ames Research Center.
11: *
12: * Redistribution and use in source and binary forms, with or without
13: * modification, are permitted provided that the following conditions
14: * are met:
15: * 1. Redistributions of source code must retain the above copyright
16: * notice, this list of conditions and the following disclaimer.
17: * 2. Redistributions in binary form must reproduce the above copyright
18: * notice, this list of conditions and the following disclaimer in the
19: * documentation and/or other materials provided with the distribution.
20: * 3. All advertising materials mentioning features or use of this software
21: * must display the following acknowledgement:
22: * This product includes software developed by the NetBSD
23: * Foundation, Inc. and its contributors.
24: * 4. Neither the name of The NetBSD Foundation nor the names of its
25: * contributors may be used to endorse or promote products derived
26: * from this software without specific prior written permission.
27: *
28: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
29: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
30: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
31: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
32: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38: * POSSIBILITY OF SUCH DAMAGE.
39: */
40:
41: /*
42: * Copyright (c) 1994 Peter Galbavy. All rights reserved.
43: *
44: * Redistribution and use in source and binary forms, with or without
45: * modification, are permitted provided that the following conditions
46: * are met:
47: * 1. Redistributions of source code must retain the above copyright
48: * notice, this list of conditions and the following disclaimer.
49: * 2. Redistributions in binary form must reproduce the above copyright
50: * notice, this list of conditions and the following disclaimer in the
51: * documentation and/or other materials provided with the distribution.
52: *
53: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
54: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
55: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
56: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
57: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
58: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
59: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
60: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
61: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
62: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63: */
64:
65: #include <sys/timeout.h>
66:
67: /* Set this to 1 for normal debug, or 2 for per-target tracing. */
68: #if !defined(SMALL_KERNEL)
69: #define NCR53C9X_DEBUG 1
70: #endif
71:
72: /* Wide or differential can have 16 targets */
73: #define NCR_NTARG 16
74: #define NCR_NLUN 8
75:
76: #define NCR_ABORT_TIMEOUT 2000 /* time to wait for abort */
77: #define NCR_SENSE_TIMEOUT 1000 /* time to wait for sense */
78:
79: #define FREQTOCCF(freq) (((freq + 4) / 5))
80:
81: /*
82: * NCR 53c9x variants. Note, these values are used as indexes into
83: * a table; don't modify them unless you know what you're doing.
84: */
85: #define NCR_VARIANT_ESP100 0
86: #define NCR_VARIANT_ESP100A 1
87: #define NCR_VARIANT_ESP200 2
88: #define NCR_VARIANT_NCR53C94 3
89: #define NCR_VARIANT_NCR53C96 4
90: #define NCR_VARIANT_ESP406 5
91: #define NCR_VARIANT_FAS408 6
92: #define NCR_VARIANT_FAS216 7
93: #define NCR_VARIANT_AM53C974 8
94: #define NCR_VARIANT_FAS366 9
95: #define NCR_VARIANT_MAX 10
96:
97: /*
98: * ECB. Holds additional information for each SCSI command Comments: We
99: * need a separate scsi command block because we may need to overwrite it
100: * with a request sense command. Basicly, we refrain from fiddling with
101: * the scsi_xfer struct (except do the expected updating of return values).
102: * We'll generally update: xs->{flags,resid,error,sense,status} and
103: * occasionally xs->retries.
104: */
105: struct ncr53c9x_ecb {
106: TAILQ_ENTRY(ncr53c9x_ecb) chain;
107: struct scsi_xfer *xs; /* SCSI xfer ctrl block from above */
108: int flags;
109: #define ECB_ALLOC 0x01
110: #define ECB_READY 0x02
111: #define ECB_SENSE 0x04
112: #define ECB_ABORT 0x40
113: #define ECB_RESET 0x80
114: #define ECB_TENTATIVE_DONE 0x100
115: int timeout;
116: struct timeout to;
117:
118: struct {
119: u_char msg[3]; /* Selection Id msg */
120: struct scsi_generic cmd; /* SCSI command block */
121: } cmd;
122: char *daddr; /* Saved data pointer */
123: int clen; /* Size of command in cmd.cmd */
124: int dleft; /* Residue */
125: u_char stat; /* SCSI status byte */
126: u_char tag[2]; /* TAG bytes */
127: u_char pad[1];
128:
129: #if NCR53C9X_DEBUG > 1
130: char trace[1000];
131: #endif
132: };
133: #if NCR53C9X_DEBUG > 1
134: #define ECB_TRACE(ecb, msg, a, b) do { \
135: const char *f = "[" msg "]"; \
136: int n = strlen((ecb)->trace); \
137: if (n < (sizeof((ecb)->trace)-100)) \
138: snprintf((ecb)->trace + n, sizeof((ecb)->trace) - n, f, a, b); \
139: } while(0)
140: #else
141: #define ECB_TRACE(ecb, msg, a, b)
142: #endif
143:
144: /*
145: * Some info about ech (possible) target and LUN on the SCSI bus.
146: *
147: * SCSI I and II devices can have up to 8 LUNs, each with up to 256
148: * outstanding tags. SCSI III devices have 64-bit LUN identifiers
149: * that can be sparsely allocated.
150: *
151: * Since SCSI II devices can have up to 8 LUNs, we use an array
152: * of 8 pointers to ncr53c9x_linfo structures for fast lookup.
153: * Longer LUNs need to traverse the linked list.
154: */
155:
156: struct ncr53c9x_linfo {
157: int64_t lun;
158: LIST_ENTRY(ncr53c9x_linfo) link;
159: time_t last_used;
160: unsigned char used; /* # slots in use */
161: unsigned char avail; /* where to start scanning */
162: unsigned char busy;
163: struct ncr53c9x_ecb *untagged;
164: struct ncr53c9x_ecb *queued[256];
165: };
166:
167: struct ncr53c9x_tinfo {
168: int cmds; /* # of commands processed */
169: int dconns; /* # of disconnects */
170: int touts; /* # of timeouts */
171: int perrs; /* # of parity errors */
172: int senses; /* # of request sense commands sent */
173: u_char flags;
174: #define T_NEED_TO_RESET 0x01 /* Should send a BUS_DEV_RESET */
175: #define T_NEGOTIATE 0x02 /* (Re)Negotiate synchronous options */
176: #define T_BUSY 0x04 /* Target is busy, i.e. cmd in progress */
177: #define T_SYNCMODE 0x08 /* sync mode has been negotiated */
178: #define T_SYNCHOFF 0x10 /* .. */
179: #define T_RSELECTOFF 0x20 /* .. */
180: #define T_TAG 0x40 /* TAG QUEUEs are on */
181: #define T_WIDE 0x80 /* Negotiate wide options */
182: u_char period; /* Period suggestion */
183: u_char offset; /* Offset suggestion */
184: u_char cfg3; /* per target config 3 */
185: u_char nextag; /* Next available tag */
186: u_char width; /* width suggestion */
187: LIST_HEAD(lun_list, ncr53c9x_linfo) luns;
188: struct ncr53c9x_linfo *lun[NCR_NLUN]; /* For speedy lookups */
189: };
190:
191: /* Look up a lun in a tinfo */
192: #define TINFO_LUN(t, l) ((((l) < NCR_NLUN) && (((t)->lun[(l)]) != NULL)) ? \
193: ((t)->lun[(l)]) : ncr53c9x_lunsearch((t), (int64_t)(l)))
194:
195: /* Register a linenumber (for debugging) */
196: #define LOGLINE(p)
197:
198: #define NCR_SHOWECBS 0x01
199: #define NCR_SHOWINTS 0x02
200: #define NCR_SHOWCMDS 0x04
201: #define NCR_SHOWMISC 0x08
202: #define NCR_SHOWTRAC 0x10
203: #define NCR_SHOWSTART 0x20
204: #define NCR_SHOWPHASE 0x40
205: #define NCR_SHOWDMA 0x80
206: #define NCR_SHOWCCMDS 0x100
207: #define NCR_SHOWMSGS 0x200
208:
209: #ifdef NCR53C9X_DEBUG
210: extern int ncr53c9x_debug;
211: #define NCR_ECBS(str) \
212: do {if (ncr53c9x_debug & NCR_SHOWECBS) printf str;} while (0)
213: #define NCR_MISC(str) \
214: do {if (ncr53c9x_debug & NCR_SHOWMISC) printf str;} while (0)
215: #define NCR_INTS(str) \
216: do {if (ncr53c9x_debug & NCR_SHOWINTS) printf str;} while (0)
217: #define NCR_TRACE(str) \
218: do {if (ncr53c9x_debug & NCR_SHOWTRAC) printf str;} while (0)
219: #define NCR_CMDS(str) \
220: do {if (ncr53c9x_debug & NCR_SHOWCMDS) printf str;} while (0)
221: #define NCR_START(str) \
222: do {if (ncr53c9x_debug & NCR_SHOWSTART) printf str;}while (0)
223: #define NCR_PHASE(str) \
224: do {if (ncr53c9x_debug & NCR_SHOWPHASE) printf str;}while (0)
225: #define NCR_DMA(str) \
226: do {if (ncr53c9x_debug & NCR_SHOWDMA) printf str;}while (0)
227: #define NCR_MSGS(str) \
228: do {if (ncr53c9x_debug & NCR_SHOWMSGS) printf str;}while (0)
229: #else
230: #define NCR_ECBS(str)
231: #define NCR_MISC(str)
232: #define NCR_INTS(str)
233: #define NCR_TRACE(str)
234: #define NCR_CMDS(str)
235: #define NCR_START(str)
236: #define NCR_PHASE(str)
237: #define NCR_DMA(str)
238: #define NCR_MSGS(str)
239: #endif
240:
241: #define NCR_MAX_MSG_LEN 8
242:
243: struct ncr53c9x_softc;
244:
245: /*
246: * Function switch used as glue to MD code.
247: */
248: struct ncr53c9x_glue {
249: /* Mandatory entry points. */
250: u_char (*gl_read_reg)(struct ncr53c9x_softc *, int);
251: void (*gl_write_reg)(struct ncr53c9x_softc *, int, u_char);
252: int (*gl_dma_isintr)(struct ncr53c9x_softc *);
253: void (*gl_dma_reset)(struct ncr53c9x_softc *);
254: int (*gl_dma_intr)(struct ncr53c9x_softc *);
255: int (*gl_dma_setup)(struct ncr53c9x_softc *,
256: caddr_t *, size_t *, int, size_t *);
257: void (*gl_dma_go)(struct ncr53c9x_softc *);
258: void (*gl_dma_stop)(struct ncr53c9x_softc *);
259: int (*gl_dma_isactive)(struct ncr53c9x_softc *);
260:
261: /* Optional entry points. */
262: void (*gl_clear_latched_intr)(struct ncr53c9x_softc *);
263: };
264:
265: struct ncr53c9x_softc {
266: struct device sc_dev; /* us as a device */
267:
268: struct timeout sc_watchdog; /* periodic timer */
269: struct scsi_link sc_link; /* scsi link struct */
270:
271: struct ncr53c9x_glue *sc_glue; /* glue to MD code */
272:
273: int sc_ntarg; /* number of targets */
274: int sc_cfflags; /* Copy of config flags */
275:
276: /* register defaults */
277: u_char sc_cfg1; /* Config 1 */
278: u_char sc_cfg2; /* Config 2, not ESP100 */
279: u_char sc_cfg3; /* Config 3, only ESP200 */
280: u_char sc_cfg3_fscsi; /* Chip specific FSCSI bit */
281: u_char sc_cfg4; /* Config 4 */
282: u_char sc_cfg5; /* Config 5 */
283: u_char sc_ccf; /* Clock Conversion */
284: u_char sc_timeout;
285:
286: /* register copies, see espreadregs() */
287: u_char sc_espintr;
288: u_char sc_espstat;
289: u_char sc_espstep;
290: u_char sc_espstat2;
291: u_char sc_espfflags;
292:
293: /* Lists of command blocks */
294: TAILQ_HEAD(ecb_list, ncr53c9x_ecb) ready_list;
295:
296: struct ncr53c9x_ecb *sc_nexus; /* Current command */
297: struct ncr53c9x_tinfo sc_tinfo[NCR_NTARG];
298:
299: /* Data about the current nexus (updated for every cmd switch) */
300: caddr_t sc_dp; /* Current data pointer */
301: ssize_t sc_dleft; /* Data left to transfer */
302:
303: /* Adapter state */
304: int sc_phase; /* Copy of what bus phase we are in */
305: int sc_prevphase; /* Copy of what bus phase we were in */
306: u_char sc_state; /* State applicable to the adapter */
307: u_char sc_flags; /* See below */
308: u_char sc_selid;
309: u_char sc_lastcmd;
310:
311: /* Message stuff */
312: u_short sc_msgify; /* IDENTIFY message associated with this nexus */
313: u_short sc_msgout; /* What message is on its way out? */
314: u_short sc_msgpriq; /* One or more messages to send (encoded) */
315: u_short sc_msgoutq; /* What messages have been sent so far? */
316:
317: u_char *sc_omess; /* MSGOUT buffer */
318: caddr_t sc_omp; /* Message pointer (for multibyte messages) */
319: size_t sc_omlen;
320: u_char *sc_imess; /* MSGIN buffer */
321: caddr_t sc_imp; /* Message pointer (for multibyte messages) */
322: size_t sc_imlen;
323:
324: caddr_t sc_cmdp; /* Command pointer (for DMAed commands) */
325: size_t sc_cmdlen; /* Size of command in transit */
326:
327: /* Hardware attributes */
328: int sc_freq; /* SCSI bus frequency in MHz */
329: int sc_id; /* Our SCSI id */
330: int sc_rev; /* Chip revision */
331: int sc_features; /* Chip features */
332: int sc_minsync; /* Minimum sync period / 4 */
333: int sc_maxxfer; /* Maximum transfer size */
334: };
335:
336: /* values for sc_state */
337: #define NCR_IDLE 1 /* waiting for something to do */
338: #define NCR_SELECTING 2 /* SCSI command is arbiting */
339: #define NCR_RESELECTED 3 /* Has been reselected */
340: #define NCR_IDENTIFIED 4 /* Has gotten IFY but not TAG */
341: #define NCR_CONNECTED 5 /* Actively using the SCSI bus */
342: #define NCR_DISCONNECT 6 /* MSG_DISCONNECT received */
343: #define NCR_CMDCOMPLETE 7 /* MSG_CMDCOMPLETE received */
344: #define NCR_CLEANING 8
345: #define NCR_SBR 9 /* Expect a SCSI RST because we commanded it */
346:
347: /* values for sc_flags */
348: #define NCR_DROP_MSGI 0x01 /* Discard all msgs (parity err detected) */
349: #define NCR_ABORTING 0x02 /* Bailing out */
350: #define NCR_DOINGDMA 0x04 /* The FIFO data path is active! */
351: #define NCR_SYNCHNEGO 0x08 /* Synch negotiation in progress. */
352: #define NCR_ICCS 0x10 /* Expect status phase results */
353: #define NCR_WAITI 0x20 /* Waiting for non-DMA data to arrive */
354: #define NCR_ATN 0x40 /* ATN asserted */
355: #define NCR_EXPECT_ILLCMD 0x80 /* Expect Illegal Command Interrupt */
356:
357: /* values for sc_features */
358: #define NCR_F_HASCFG3 0x01 /* chip has CFG3 register */
359: #define NCR_F_FASTSCSI 0x02 /* chip supports Fast mode */
360: #define NCR_F_DMASELECT 0x04 /* can do dma select */
361: #define NCR_F_SELATN3 0x08 /* can do selatn3 */
362:
363: /* values for sc_msgout */
364: #define SEND_DEV_RESET 0x0001
365: #define SEND_PARITY_ERROR 0x0002
366: #define SEND_INIT_DET_ERR 0x0004
367: #define SEND_REJECT 0x0008
368: #define SEND_IDENTIFY 0x0010
369: #define SEND_ABORT 0x0020
370: #define SEND_WDTR 0x0040
371: #define SEND_SDTR 0x0080
372: #define SEND_TAG 0x0100
373:
374: /* SCSI Status codes */
375: #define ST_MASK 0x3e /* bit 0,6,7 is reserved */
376:
377: /* phase bits */
378: #define IOI 0x01
379: #define CDI 0x02
380: #define MSGI 0x04
381:
382: /* Information transfer phases */
383: #define DATA_OUT_PHASE (0)
384: #define DATA_IN_PHASE (IOI)
385: #define COMMAND_PHASE (CDI)
386: #define STATUS_PHASE (CDI|IOI)
387: #define MESSAGE_OUT_PHASE (MSGI|CDI)
388: #define MESSAGE_IN_PHASE (MSGI|CDI|IOI)
389:
390: #define PHASE_MASK (MSGI|CDI|IOI)
391:
392: /* Some pseudo phases for getphase()*/
393: #define BUSFREE_PHASE 0x100 /* Re/Selection no longer valid */
394: #define INVALID_PHASE 0x101 /* Re/Selection valid, but no REQ yet */
395: #define PSEUDO_PHASE 0x100 /* "pseudo" bit */
396:
397: /*
398: * Macros to read and write the chip's registers.
399: */
400: #define NCR_READ_REG(sc, reg) \
401: (*(sc)->sc_glue->gl_read_reg)((sc), (reg))
402: #define NCR_WRITE_REG(sc, reg, val) \
403: (*(sc)->sc_glue->gl_write_reg)((sc), (reg), (val))
404:
405: #ifdef NCR53C9X_DEBUG
406: #define NCRCMD(sc, cmd) do { \
407: if (ncr53c9x_debug & NCR_SHOWCCMDS) \
408: printf("<cmd:0x%x %d>", (unsigned)cmd, __LINE__); \
409: sc->sc_lastcmd = cmd; \
410: NCR_WRITE_REG(sc, NCR_CMD, cmd); \
411: } while (0)
412: #else
413: #define NCRCMD(sc, cmd) NCR_WRITE_REG(sc, NCR_CMD, cmd)
414: #endif
415:
416: /*
417: * DMA macros for NCR53c9x
418: */
419: #define NCRDMA_ISINTR(sc) (*(sc)->sc_glue->gl_dma_isintr)((sc))
420: #define NCRDMA_RESET(sc) (*(sc)->sc_glue->gl_dma_reset)((sc))
421: #define NCRDMA_INTR(sc) (*(sc)->sc_glue->gl_dma_intr)((sc))
422: #define NCRDMA_SETUP(sc, addr, len, datain, dmasize) \
423: (*(sc)->sc_glue->gl_dma_setup)((sc), (addr), (len), (datain), (dmasize))
424: #define NCRDMA_GO(sc) (*(sc)->sc_glue->gl_dma_go)((sc))
425: #define NCRDMA_ISACTIVE(sc) (*(sc)->sc_glue->gl_dma_isactive)((sc))
426:
427: /*
428: * Macro to convert the chip register Clock Per Byte value to
429: * Synchronous Transfer Period.
430: */
431: #define ncr53c9x_cpb2stp(sc, cpb) \
432: ((250 * (cpb)) / (sc)->sc_freq)
433:
434: void ncr53c9x_attach(struct ncr53c9x_softc *,
435: struct scsi_adapter *, struct scsi_device *);
436: int ncr53c9x_scsi_cmd(struct scsi_xfer *);
437: void ncr53c9x_reset(struct ncr53c9x_softc *);
438: int ncr53c9x_intr(void *);
439: void ncr53c9x_init(struct ncr53c9x_softc *, int);
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