Annotation of sys/dev/ic/ncr53c9xreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: ncr53c9xreg.h,v 1.9 2003/10/21 18:58:49 jmc Exp $ */
2: /* $NetBSD: ncr53c9xreg.h,v 1.4 1997/05/17 20:56:55 pk Exp $ */
3:
4: /*
5: * Copyright (c) 1994 Peter Galbavy. All rights reserved.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: *
16: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26: */
27:
28: /*
29: * Register addresses, relative to some base address
30: */
31:
32: #define NCR_TCL 0x00 /* RW - Transfer Count Low */
33: #define NCR_TCM 0x01 /* RW - Transfer Count Mid */
34: #define NCR_TCH 0x0e /* RW - Transfer Count High */
35: /* NOT on 53C90 */
36:
37: #define NCR_FIFO 0x02 /* RW - FIFO data */
38:
39: #define NCR_CMD 0x03 /* RW - Command (2 deep) */
40: #define NCRCMD_DMA 0x80 /* DMA Bit */
41: #define NCRCMD_NOP 0x00 /* No Operation */
42: #define NCRCMD_FLUSH 0x01 /* Flush FIFO */
43: #define NCRCMD_RSTCHIP 0x02 /* Reset Chip */
44: #define NCRCMD_RSTSCSI 0x03 /* Reset SCSI Bus */
45: #define NCRCMD_RESEL 0x40 /* Reselect Sequence */
46: #define NCRCMD_SELNATN 0x41 /* Select without ATN */
47: #define NCRCMD_SELATN 0x42 /* Select with ATN */
48: #define NCRCMD_SELATNS 0x43 /* Select with ATN & Stop */
49: #define NCRCMD_ENSEL 0x44 /* Enable (Re)Selection */
50: #define NCRCMD_DISSEL 0x45 /* Disable (Re)Selection */
51: #define NCRCMD_SELATN3 0x46 /* Select with ATN3 */
52: #define NCRCMD_RESEL3 0x47 /* Reselect3 Sequence */
53: #define NCRCMD_SNDMSG 0x20 /* Send Message */
54: #define NCRCMD_SNDSTAT 0x21 /* Send Status */
55: #define NCRCMD_SNDDATA 0x22 /* Send Data */
56: #define NCRCMD_DISCSEQ 0x23 /* Disconnect Sequence */
57: #define NCRCMD_TERMSEQ 0x24 /* Terminate Sequence */
58: #define NCRCMD_TCCS 0x25 /* Target Command Comp Seq */
59: #define NCRCMD_DISC 0x27 /* Disconnect */
60: #define NCRCMD_RECMSG 0x28 /* Receive Message */
61: #define NCRCMD_RECCMD 0x29 /* Receive Command */
62: #define NCRCMD_RECDATA 0x2a /* Receive Data */
63: #define NCRCMD_RECCSEQ 0x2b /* Receive Command Sequence*/
64: #define NCRCMD_ABORT 0x04 /* Target Abort DMA */
65: #define NCRCMD_TRANS 0x10 /* Transfer Information */
66: #define NCRCMD_ICCS 0x11 /* Initiator Cmd Comp Seq */
67: #define NCRCMD_MSGOK 0x12 /* Message Accepted */
68: #define NCRCMD_TRPAD 0x18 /* Transfer Pad */
69: #define NCRCMD_SETATN 0x1a /* Set ATN */
70: #define NCRCMD_RSTATN 0x1b /* Reset ATN */
71:
72: #define NCR_STAT 0x04 /* RO - Status */
73: #define NCRSTAT_INT 0x80 /* Interrupt */
74: #define NCRSTAT_GE 0x40 /* Gross Error */
75: #define NCRSTAT_PE 0x20 /* Parity Error */
76: #define NCRSTAT_TC 0x10 /* Terminal Count */
77: #define NCRSTAT_VGC 0x08 /* Valid Group Code */
78: #define NCRSTAT_PHASE 0x07 /* Phase bits */
79:
80: #define NCR_SELID 0x04 /* WO - Select/Reselect Bus ID */
81: #define NCR_BUSID_HME 0x10 /* XXX HME reselect ID */
82: #define NCR_BUSID_HME32 0x40 /* XXX HME to select more than 16 */
83:
84: #define NCR_INTR 0x05 /* RO - Interrupt */
85: #define NCRINTR_SBR 0x80 /* SCSI Bus Reset */
86: #define NCRINTR_ILL 0x40 /* Illegal Command */
87: #define NCRINTR_DIS 0x20 /* Disconnect */
88: #define NCRINTR_BS 0x10 /* Bus Service */
89: #define NCRINTR_FC 0x08 /* Function Complete */
90: #define NCRINTR_RESEL 0x04 /* Reselected */
91: #define NCRINTR_SELATN 0x02 /* Select with ATN */
92: #define NCRINTR_SEL 0x01 /* Selected */
93:
94: #define NCR_TIMEOUT 0x05 /* WO - Select/Reselect Timeout */
95:
96: #define NCR_STEP 0x06 /* RO - Sequence Step */
97: #define NCRSTEP_MASK 0x07 /* the last 3 bits */
98: #define NCRSTEP_DONE 0x04 /* command went out */
99:
100: #define NCR_SYNCTP 0x06 /* WO - Synch Transfer Period */
101: /* Default 5 (53C9X) */
102:
103: #define NCR_FFLAG 0x07 /* RO - FIFO Flags */
104: #define NCRFIFO_SS 0xe0 /* Sequence Step (Dup) */
105: #define NCRFIFO_FF 0x1f /* Bytes in FIFO */
106:
107: #define NCR_SYNCOFF 0x07 /* WO - Synch Offset */
108: /* 0 = ASYNC */
109: /* 1 - 15 = SYNC bytes */
110:
111: #define NCR_CFG1 0x08 /* RW - Configuration #1 */
112: #define NCRCFG1_SLOW 0x80 /* Slow Cable Mode */
113: #define NCRCFG1_SRR 0x40 /* SCSI Reset Rep Int Dis */
114: #define NCRCFG1_PTEST 0x20 /* Parity Test Mod */
115: #define NCRCFG1_PARENB 0x10 /* Enable Parity Check */
116: #define NCRCFG1_CTEST 0x08 /* Enable Chip Test */
117: #define NCRCFG1_BUSID 0x07 /* Bus ID */
118:
119: #define NCR_CCF 0x09 /* WO - Clock Conversion Factor */
120: /* 0 = 35.01 - 40MHz */
121: /* NEVER SET TO 1 */
122: /* 2 = 10MHz */
123: /* 3 = 10.01 - 15MHz */
124: /* 4 = 15.01 - 20MHz */
125: /* 5 = 20.01 - 25MHz */
126: /* 6 = 25.01 - 30MHz */
127: /* 7 = 30.01 - 35MHz */
128:
129: #define NCR_TEST 0x0a /* WO - Test (Chip Test Only) */
130:
131: #define NCR_CFG2 0x0b /* RW - Configuration #2 */
132: #define NCRCFG2_RSVD 0xa0 /* reserved */
133: #define NCRCFG2_FE 0x40 /* Features Enable */
134: #define NCRCFG2_DREQ 0x10 /* DREQ High Impedance */
135: #define NCRCFG2_SCSI2 0x08 /* SCSI-2 Enable */
136: #define NCRCFG2_BPA 0x04 /* Target Bad Parity Abort */
137: #define NCRCFG2_RPE 0x02 /* Register Parity Error */
138: #define NCRCFG2_DPE 0x01 /* DMA Parity Error */
139: #define NCRCFG2_HMEFE 0x10 /* HME feature enable */
140: #define NCRCFG2_HME32 0x80 /* HME 32 extended */
141:
142: /* Config #3 only on 53C9X */
143: #define NCR_CFG3 0x0c /* RW - Configuration #3 */
144: #define NCRCFG3_RSVD 0xe0 /* reserved */
145: #define NCRCFG3_IDM 0x10 /* ID Message Res Check */
146: #define NCRCFG3_QTE 0x08 /* Queue Tag Enable */
147: #define NCRCFG3_CDB 0x04 /* CDB 10-bytes OK */
148: #define NCRCFG3_FSCSI 0x02 /* Fast SCSI */
149: #define NCRCFG3_FCLK 0x01 /* Fast Clock (>25MHz) */
150:
151: /*
152: * For some unknown reason, the ESP406/FAS408 looks like every
153: * other ncr53c9x, except for configuration #3 register. At any
154: * rate, if you're dealing with these chips, you need to use these
155: * defines instead.
156: */
157:
158: /* Config #3 different on ESP406/FAS408 */
159: #define NCR_ESPCFG3 0x0c /* RW - Configuration #3 */
160: #define NCRESPCFG3_IDM 0x80 /* ID Message Res Check */
161: #define NCRESPCFG3_QTE 0x40 /* Queue Tag Enable */
162: #define NCRESPCFG3_CDB 0x20 /* CDB 10-bytes OK */
163: #define NCRESPCFG3_FSCSI 0x10 /* Fast SCSI */
164: #define NCRESPCFG3_SRESB 0x08 /* Save Residual Byte */
165: #define NCRESPCFG3_FCLK 0x04 /* Fast Clock (>25MHz) */
166: #define NCRESPCFG3_ADMA 0x02 /* Alternate DMA Mode */
167: #define NCRESPCFG3_T8M 0x01 /* Threshold 8 Mode */
168:
169: /* Config #3 also different on NCR53CF9x/FAS216 */
170: #define NCR_F9XCFG3 0x0c /* RW - Configuration #3 */
171: #define NCRF9XCFG3_IDM 0x80 /* ID Message Res Check */
172: #define NCRF9XCFG3_QTE 0x40 /* Queue Tag Enable */
173: #define NCRF9XCFG3_CDB 0x20 /* CDB 10-bytes OK */
174: #define NCRF9XCFG3_FSCSI 0x10 /* Fast SCSI */
175: #define NCRF9XCFG3_FCLK 0x08 /* Fast Clock (>25MHz) */
176: #define NCRF9XCFG3_SRESB 0x04 /* Save Residual Byte */
177: #define NCRF9XCFG3_ADMA 0x02 /* Alternate DMA Mode */
178: #define NCRF9XCFG3_T8M 0x01 /* Threshold 8 Mode */
179:
180: /* Config #3 on FAS366 */
181: #define NCRFASCFG3_OBAUTO 0x80 /* auto push odd-byte to dma */
182: #define NCRFASCFG3_EWIDE 0x40 /* Enable Wide-SCSI */
183: #define NCRFASCFG3_IDBIT3 0x20 /* Bit 3 of HME SCSI-ID */
184: #define NCRFASCFG3_IDRESCHK 0x10 /* ID message checking */
185: #define NCRFASCFG3_QUENB 0x08 /* 3-byte msg support */
186: #define NCRFASCFG3_CDB10 0x04 /* group 2 scsi-2 support */
187: #define NCRFASCFG3_FASTSCSI 0x02 /* 10 MB/S fast scsi mode */
188: #define NCRFASCFG3_FASTCLK 0x01 /* fast clock mode */
189:
190: /* Config #4 only on ESP406/FAS408 */
191: #define NCR_CFG4 0x0d /* RW - Configuration #4 */
192: #define NCRCFG4_CRS1 0x80 /* Select register set #1 */
193: #define NCRCFG4_RSVD 0x7b /* reserved */
194: #define NCRCFG4_ACTNEG 0x04 /* Active negation */
195:
196: /*
197: The following registers are only on the ESP406/FAS408. The
198: documentation refers to them as "Control Register Set #1".
199: These are the registers that are visible when bit 7 of
200: register 0x0d is set. This bit is common to both register sets.
201: */
202:
203: #define NCR_JMP 0x00 /* RO - Jumper Sense Register */
204: #define NCRJMP_RSVD 0xc0 /* reserved */
205: #define NCRJMP_ROMSZ 0x20 /* ROM Size 1=16K, 0=32K */
206: #define NCRJMP_J4 0x10 /* Jumper #4 */
207: #define NCRJMP_J3 0x08 /* Jumper #3 */
208: #define NCRJMP_J2 0x04 /* Jumper #2 */
209: #define NCRJMP_J1 0x02 /* Jumper #1 */
210: #define NCRJMP_J0 0x01 /* Jumper #0 */
211:
212: #define NCR_PIOFIFO 0x04 /* WO - PIO FIFO, 4 bytes deep */
213:
214: #define NCR_PSTAT 0x08 /* RW - PIO Status Register */
215: #define NCRPSTAT_PERR 0x80 /* PIO Error */
216: #define NCRPSTAT_SIRQ 0x40 /* Active High of SCSI IRQ */
217: #define NCRPSTAT_ATAI 0x20 /* ATA IRQ */
218: #define NCRPSTAT_FEMPT 0x10 /* PIO FIFO Empty */
219: #define NCRPSTAT_F13 0x08 /* PIO FIFO 1/3 */
220: #define NCRPSTAT_F23 0x04 /* PIO FIFO 2/3 */
221: #define NCRPSTAT_FFULL 0x02 /* PIO FIFO Full */
222: #define NCRPSTAT_PIOM 0x01 /* PIO/DMA Mode */
223:
224: #define NCR_PIOI 0x0b /* RW - PIO Interrupt Enable */
225: #define NCRPIOI_RSVD 0xe0 /* reserved */
226: #define NCRPIOI_EMPTY 0x10 /* IRQ When Empty */
227: #define NCRPIOI_13 0x08 /* IRQ When 1/3 */
228: #define NCRPIOI_23 0x04 /* IRQ When 2/3 */
229: #define NCRPIOI_FULL 0x02 /* IRQ When Full */
230: #define NCRPIOI_FINV 0x01 /* Flag Invert */
231:
232: #define NCR_CFG5 0x0d /* RW - Configuration #5 */
233: #define NCRCFG5_CRS1 0x80 /* Select Register Set #1 */
234: #define NCRCFG5_SRAM 0x40 /* SRAM Memory Map */
235: #define NCRCFG5_AADDR 0x20 /* Auto Address */
236: #define NCRCFG5_PTRINC 0x10 /* Pointer Increment */
237: #define NCRCFG5_LOWPWR 0x08 /* Low Power Mode */
238: #define NCRCFG5_SINT 0x04 /* SCSI Interrupt Enable */
239: #define NCRCFG5_INTP 0x02 /* INT Polarity */
240: #define NCRCFG5_AINT 0x01 /* ATA Interrupt Enable */
241:
242: #define NCR_SIGNTR 0x0e /* RO - Signature */
243:
244: /* Am53c974 Config #3 */
245: #define NCR_AMDCFG3 0x0c /* RW - Configuration #3 */
246: #define NCRAMDCFG3_IDM 0x80 /* ID Message Res Check */
247: #define NCRAMDCFG3_QTE 0x40 /* Queue Tag Enable */
248: #define NCRAMDCFG3_CDB 0x20 /* CDB 10-bytes OK */
249: #define NCRAMDCFG3_FSCSI 0x10 /* Fast SCSI */
250: #define NCRAMDCFG3_FCLK 0x08 /* Fast Clock (40MHz) */
251: #define NCRAMDCFG3_RSVD 0x07 /* Reserved */
252:
253: /* Am53c974 Config #4 */
254: #define NCR_AMDCFG4 0x0d /* RW - Configuration #4 */
255: #define NCRAMDCFG4_GE 0xc0 /* Glitch Eater */
256: #define NCRAMDCFG4_GE12NS 0x00 /* Signal window 12ns */
257: #define NCRAMDCFG4_GE25NS 0x80 /* Signal window 25ns */
258: #define NCRAMDCFG4_GE35NS 0x40 /* Signal window 35ns */
259: #define NCRAMDCFG4_GE0NS 0xc0 /* Signal window 0ns */
260: #define NCRAMDCFG4_PWD 0x20 /* Reduced power feature */
261: #define NCRAMDCFG4_RSVD 0x13 /* Reserved */
262: #define NCRAMDCFG4_RAE 0x08 /* Active neg. REQ/ACK */
263: #define NCRAMDCFG4_RADE 0x04 /* Active neg. REQ/ACK/DAT */
264:
265: /*
266: * FAS366
267: */
268: #define NCR_RCL NCR_TCH /* Recommand counter low */
269: #define NCR_RCH 0xf /* Recommand counter high */
270: #define NCR_UID NCR_RCL /* fas366 part-uniq id */
271:
272: /* status register #2 definitions (read only) */
273: #define NCR_STAT2 NCR_CCF
274: #define FAS_STAT2_SEQCNT 0x01 /* Sequence counter bit 7-3 enabled */
275: #define FAS_STAT2_FLATCHED 0x02 /* FIFO flags register latched */
276: #define FAS_STAT2_CLATCHED 0x04 /* Xfer cntr & recommand ctr latched */
277: #define FAS_STAT2_CACTIVE 0x08 /* Command register is active */
278: #define FAS_STAT2_SCSI16 0x10 /* SCSI interface is wide */
279: #define FAS_STAT2_ISHUTTLE 0x20 /* FIFO Top register contains 1 byte */
280: #define FAS_STAT2_OSHUTTLE 0x40 /* next byte from FIFO is MSB */
281: #define FAS_STAT2_EMPTY 0x80 /* FIFO is empty */
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