Annotation of sys/dev/ic/ncr5380reg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: ncr5380reg.h,v 1.3 1996/10/31 01:01:35 niklas Exp $ */
! 2: /* $NetBSD: ncr5380reg.h,v 1.2 1996/01/01 22:24:35 thorpej Exp $ */
! 3:
! 4: /*
! 5: * Mach Operating System
! 6: * Copyright (c) 1991,1990,1989 Carnegie Mellon University
! 7: * All Rights Reserved.
! 8: *
! 9: * Permission to use, copy, modify and distribute this software and its
! 10: * documentation is hereby granted, provided that both the copyright
! 11: * notice and this permission notice appear in all copies of the
! 12: * software, derivative works or modified versions, and any portions
! 13: * thereof, and that both notices appear in supporting documentation.
! 14: *
! 15: * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS
! 16: * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
! 17: * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
! 18: *
! 19: * Carnegie Mellon requests users of this software to return to
! 20: *
! 21: * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
! 22: * School of Computer Science
! 23: * Carnegie Mellon University
! 24: * Pittsburgh PA 15213-3890
! 25: *
! 26: * any improvements or extensions that they make and grant Carnegie the
! 27: * rights to redistribute these changes.
! 28: */
! 29: /*
! 30: * HISTORY (mach3)
! 31: * Revision 2.3 91/08/24 12:25:10 af
! 32: * Moved padding of regmap in impl file.
! 33: * [91/08/02 04:22:39 af]
! 34: *
! 35: * Revision 2.2 91/06/19 16:28:35 rvb
! 36: * From the NCR data sheets
! 37: * "NCR 5380 Family, SCSI Protocol Controller Data Manual"
! 38: * NCR Microelectronics Division, Colorado Spring, 6/98 T01891L
! 39: * [91/04/21 af]
! 40: *
! 41: */
! 42:
! 43: /*
! 44: * File: scsi_5380.h
! 45: * Author: Alessandro Forin, Carnegie Mellon University
! 46: * Date: 5/91
! 47: *
! 48: * Defines for the NCR 5380 (SCSI chip), aka Am5380
! 49: */
! 50:
! 51: /*
! 52: * Register map: Note not declared here anymore!
! 53: * All the 5380 registers are accessed through individual
! 54: * pointers initialized by MD code. This allows the 5380
! 55: * MI functions to be shared between MD drivers that have
! 56: * different padding between the registers (i.e. amiga).
! 57: */
! 58: #if 0 /* example only */
! 59: struct ncr5380regs {
! 60: volatile u_char sci_r0;
! 61: volatile u_char sci_r1;
! 62: volatile u_char sci_r2;
! 63: volatile u_char sci_r3;
! 64: volatile u_char sci_r4;
! 65: volatile u_char sci_r5;
! 66: volatile u_char sci_r6;
! 67: volatile u_char sci_r7;
! 68: };
! 69: #endif
! 70:
! 71: /*
! 72: * Machine-independent code uses these names:
! 73: */
! 74: #define sci_data sci_r0 /* r: Current data */
! 75: #define sci_odata sci_r0 /* w: Out data */
! 76:
! 77: #define sci_icmd sci_r1 /* rw: Initiator command */
! 78: #define sci_mode sci_r2 /* rw: Mode */
! 79: #define sci_tcmd sci_r3 /* rw: Target command */
! 80:
! 81: #define sci_bus_csr sci_r4 /* r: Bus Status */
! 82: #define sci_sel_enb sci_r4 /* w: Select enable */
! 83:
! 84: #define sci_csr sci_r5 /* r: Status */
! 85: #define sci_dma_send sci_r5 /* w: Start dma send data */
! 86:
! 87: #define sci_idata sci_r6 /* r: Input data */
! 88: #define sci_trecv sci_r6 /* w: Start dma receive, target */
! 89:
! 90: #define sci_iack sci_r7 /* r: Interrupt Acknowledge */
! 91: #define sci_irecv sci_r7 /* w: Start dma receive, initiator */
! 92:
! 93:
! 94: /*
! 95: * R1: Initiator command register
! 96: */
! 97: #define SCI_ICMD_DATA 0x01 /* rw: Assert data bus */
! 98: #define SCI_ICMD_ATN 0x02 /* rw: Assert ATN signal */
! 99: #define SCI_ICMD_SEL 0x04 /* rw: Assert SEL signal */
! 100: #define SCI_ICMD_BSY 0x08 /* rw: Assert BSY signal */
! 101: #define SCI_ICMD_ACK 0x10 /* rw: Assert ACK signal */
! 102: #define SCI_ICMD_LST 0x20 /* r: Lost arbitration */
! 103: #define SCI_ICMD_DIFF SCI_ICMD_LST /* w: Differential cable */
! 104: #define SCI_ICMD_AIP 0x40 /* r: Arbitration in progress */
! 105: #define SCI_ICMD_TEST SCI_ICMD_AIP /* w: Test mode */
! 106: #define SCI_ICMD_RST 0x80 /* rw: Assert RST signal */
! 107: /* Bits to keep when doing read/modify/write (leave out RST) */
! 108: #define SCI_ICMD_RMASK 0x1F
! 109:
! 110:
! 111: /*
! 112: * R2: Mode register
! 113: */
! 114: #define SCI_MODE_ARB 0x01 /* rw: Start arbitration */
! 115: #define SCI_MODE_DMA 0x02 /* rw: Enable DMA xfers */
! 116: #define SCI_MODE_MONBSY 0x04 /* rw: Monitor BSY signal */
! 117: #define SCI_MODE_DMA_IE 0x08 /* rw: Enable DMA complete interrupt */
! 118: #define SCI_MODE_PERR_IE 0x10 /* rw: Interrupt on parity errors */
! 119: #define SCI_MODE_PAR_CHK 0x20 /* rw: Check parity */
! 120: #define SCI_MODE_TARGET 0x40 /* rw: Target mode (Initiator if 0) */
! 121: #define SCI_MODE_BLOCKDMA 0x80 /* rw: Block-mode DMA handshake */
! 122:
! 123:
! 124: /*
! 125: * R3: Target command register
! 126: */
! 127: #define SCI_TCMD_IO 0x01 /* rw: Assert I/O signal */
! 128: #define SCI_TCMD_CD 0x02 /* rw: Assert C/D signal */
! 129: #define SCI_TCMD_MSG 0x04 /* rw: Assert MSG signal */
! 130: #define SCI_TCMD_PHASE_MASK 0x07 /* r: Mask for current bus phase */
! 131: #define SCI_TCMD_REQ 0x08 /* rw: Assert REQ signal */
! 132: #define SCI_TCMD_LAST_SENT 0x80 /* ro: Last byte was xferred
! 133: * (not on 5380/1) */
! 134:
! 135: #define SCI_TCMD_PHASE(x) ((x) & 0x7)
! 136:
! 137: /*
! 138: * R4: Current (SCSI) Bus status (.sci_bus_csr)
! 139: */
! 140: #define SCI_BUS_DBP 0x01 /* r: Data Bus parity */
! 141: #define SCI_BUS_SEL 0x02 /* r: SEL signal */
! 142: #define SCI_BUS_IO 0x04 /* r: I/O signal */
! 143: #define SCI_BUS_CD 0x08 /* r: C/D signal */
! 144: #define SCI_BUS_MSG 0x10 /* r: MSG signal */
! 145: #define SCI_BUS_REQ 0x20 /* r: REQ signal */
! 146: #define SCI_BUS_BSY 0x40 /* r: BSY signal */
! 147: #define SCI_BUS_RST 0x80 /* r: RST signal */
! 148:
! 149: #define SCI_BUS_PHASE(x) (((x) >> 2) & 7)
! 150:
! 151: /*
! 152: * R5: Bus and Status register (.sci_csr)
! 153: */
! 154: #define SCI_CSR_ACK 0x01 /* r: ACK signal */
! 155: #define SCI_CSR_ATN 0x02 /* r: ATN signal */
! 156: #define SCI_CSR_DISC 0x04 /* r: Disconnected (BSY==0) */
! 157: #define SCI_CSR_PHASE_MATCH 0x08 /* r: Bus and SCI_TCMD match */
! 158: #define SCI_CSR_INT 0x10 /* r: Interrupt request */
! 159: #define SCI_CSR_PERR 0x20 /* r: Parity error */
! 160: #define SCI_CSR_DREQ 0x40 /* r: DMA request */
! 161: #define SCI_CSR_DONE 0x80 /* r: DMA count is zero */
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