Annotation of sys/dev/ic/mpireg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: mpireg.h,v 1.31 2006/09/21 08:35:39 dlg Exp $ */
2:
3: /*
4: * Copyright (c) 2005 David Gwynne <dlg@openbsd.org>
5: * Copyright (c) 2005 Marco Peereboom <marco@openbsd.org>
6: *
7: * Permission to use, copy, modify, and distribute this software for any
8: * purpose with or without fee is hereby granted, provided that the above
9: * copyright notice and this permission notice appear in all copies.
10: *
11: * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12: * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13: * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14: * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15: * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16: * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17: * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18: */
19:
20: /*
21: * System Interface Register Set
22: */
23:
24: #define MPI_DOORBELL 0x00
25: /* doorbell read bits */
26: #define MPI_DOORBELL_STATE (0xf<<28) /* ioc state */
27: #define MPI_DOORBELL_STATE_RESET (0x0<<28)
28: #define MPI_DOORBELL_STATE_READY (0x1<<28)
29: #define MPI_DOORBELL_STATE_OPER (0x2<<28)
30: #define MPI_DOORBELL_STATE_FAULT (0x4<<28)
31: #define MPI_DOORBELL_INUSE (0x1<<27) /* doorbell used */
32: #define MPI_DOORBELL_WHOINIT (0x7<<24) /* last to reset ioc */
33: #define MPI_DOORBELL_WHOINIT_NOONE (0x0<<24) /* not initialized */
34: #define MPI_DOORBELL_WHOINIT_SYSBIOS (0x1<<24) /* system bios */
35: #define MPI_DOORBELL_WHOINIT_ROMBIOS (0x2<<24) /* rom bios */
36: #define MPI_DOORBELL_WHOINIT_PCIPEER (0x3<<24) /* pci peer */
37: #define MPI_DOORBELL_WHOINIT_DRIVER (0x4<<24) /* host driver */
38: #define MPI_DOORBELL_WHOINIT_MANUFACT (0x5<<24) /* manufacturing */
39: #define MPI_DOORBELL_FAULT (0xffff<<0) /* fault code */
40: #define MPI_DOORBELL_FAULT_REQ_PCIPAR 0x8111 /* req msg pci parity err */
41: #define MPI_DOORBELL_FAULT_REQ_PCIBUS 0x8112 /* req msg pci bus err */
42: #define MPI_DOORBELL_FAULT_REP_PCIPAR 0x8113 /* reply msg pci parity err */
43: #define MPI_DOORBELL_FAULT_REP_PCIBUS 0x8114 /* reply msg pci bus err */
44: #define MPI_DOORBELL_FAULT_SND_PCIPAR 0x8115 /* data send pci parity err */
45: #define MPI_DOORBELL_FAULT_SND_PCIBUS 0x8116 /* data send pci bus err */
46: #define MPI_DOORBELL_FAULT_RCV_PCIPAR 0x8117 /* data recv pci parity err */
47: #define MPI_DOORBELL_FAULT_RCV_PCIBUS 0x8118 /* data recv pci bus err */
48: /* doorbell write bits */
49: #define MPI_DOORBELL_FUNCTION_SHIFT 24
50: #define MPI_DOORBELL_FUNCTION_MASK (0xff << MPI_DOORBELL_FUNCTION_SHIFT)
51: #define MPI_DOORBELL_FUNCTION(x) \
52: (((x) << MPI_DOORBELL_FUNCTION_SHIFT) & MPI_DOORBELL_FUNCTION_MASK)
53: #define MPI_DOORBELL_DWORDS_SHIFT 16
54: #define MPI_DOORBELL_DWORDS_MASK (0xff << MPI_DOORBELL_DWORDS_SHIFT)
55: #define MPI_DOORBELL_DWORDS(x) \
56: (((x) << MPI_DOORBELL_DWORDS_SHIFT) & MPI_DOORBELL_DWORDS_MASK)
57: #define MPI_DOORBELL_DATA_MASK 0xffff
58:
59: #define MPI_WRITESEQ 0x04
60: #define MPI_WRITESEQ_VALUE 0x0000000f /* key value */
61: #define MPI_WRITESEQ_1 0x04
62: #define MPI_WRITESEQ_2 0x0b
63: #define MPI_WRITESEQ_3 0x02
64: #define MPI_WRITESEQ_4 0x07
65: #define MPI_WRITESEQ_5 0x0d
66:
67: #define MPI_HOSTDIAG 0x08
68: #define MPI_HOSTDIAG_CLEARFBS (1<<10) /* clear flash bad sig */
69: #define MPI_HOSTDIAG_POICB (1<<9) /* prevent ioc boot */
70: #define MPI_HOSTDIAG_DWRE (1<<7) /* diag reg write enabled */
71: #define MPI_HOSTDIAG_FBS (1<<6) /* flash bad sig */
72: #define MPI_HOSTDIAG_RESET_HIST (1<<5) /* reset history */
73: #define MPI_HOSTDIAG_DIAGWR_EN (1<<4) /* diagnostic write enabled */
74: #define MPI_HOSTDIAG_RESET_ADAPTER (1<<2) /* reset adapter */
75: #define MPI_HOSTDIAG_DISABLE_ARM (1<<1) /* disable arm */
76: #define MPI_HOSTDIAG_DIAGMEM_EN (1<<0) /* diag mem enable */
77:
78: #define MPI_TESTBASE 0x0c
79:
80: #define MPI_DIAGRWDATA 0x10
81:
82: #define MPI_DIAGRWADDR 0x18
83:
84: #define MPI_INTR_STATUS 0x30
85: #define MPI_INTR_STATUS_IOCDOORBELL (1<<31) /* ioc doorbell status */
86: #define MPI_INTR_STATUS_REPLY (1<<3) /* reply message interrupt */
87: #define MPI_INTR_STATUS_DOORBELL (1<<0) /* doorbell interrupt */
88:
89: #define MPI_INTR_MASK 0x34
90: #define MPI_INTR_MASK_REPLY (1<<3) /* reply message intr mask */
91: #define MPI_INTR_MASK_DOORBELL (1<<0) /* doorbell interrupt mask */
92:
93: #define MPI_REQ_QUEUE 0x40
94:
95: #define MPI_REPLY_QUEUE 0x44
96: #define MPI_REPLY_QUEUE_ADDRESS (1<<31) /* address reply */
97: #define MPI_REPLY_QUEUE_ADDRESS_MASK 0x7fffffff
98: #define MPI_REPLY_QUEUE_TYPE_MASK (3<<29)
99: #define MPI_REPLY_QUEUE_TYPE_INIT (0<<29) /* scsi initiator reply */
100: #define MPI_REPLY_QUEUE_TYPE_TARGET (1<<29) /* scsi target reply */
101: #define MPI_REPLY_QUEUE_TYPE_LAN (2<<29) /* lan reply */
102: #define MPI_REPLY_QUEUE_CONTEXT 0x1fffffff /* not address and type */
103:
104: #define MPI_PRIREQ_QUEUE 0x48
105:
106: /*
107: * Scatter Gather Lists
108: */
109:
110: #define MPI_SGE_FL_LAST (0x1<<31) /* last element in segment */
111: #define MPI_SGE_FL_EOB (0x1<<30) /* last element of buffer */
112: #define MPI_SGE_FL_TYPE (0x3<<28) /* element type */
113: #define MPI_SGE_FL_TYPE_SIMPLE (0x1<<28) /* simple element */
114: #define MPI_SGE_FL_TYPE_CHAIN (0x3<<28) /* chain element */
115: #define MPI_SGE_FL_TYPE_XACTCTX (0x0<<28) /* transaction context */
116: #define MPI_SGE_FL_LOCAL (0x1<<27) /* local address */
117: #define MPI_SGE_FL_DIR (0x1<<26) /* direction */
118: #define MPI_SGE_FL_DIR_OUT (0x1<<26)
119: #define MPI_SGE_FL_DIR_IN (0x0<<26)
120: #define MPI_SGE_FL_SIZE (0x1<<25) /* address size */
121: #define MPI_SGE_FL_SIZE_32 (0x0<<25)
122: #define MPI_SGE_FL_SIZE_64 (0x1<<25)
123: #define MPI_SGE_FL_EOL (0x1<<24) /* end of list */
124: #define MPI_SGE_FLAGS_IOC_TO_HOST (0x00)
125: #define MPI_SGE_FLAGS_HOST_TO_IOC (0x04)
126:
127: struct mpi_sge {
128: u_int32_t sg_hdr;
129: u_int32_t sg_lo_addr;
130: u_int32_t sg_hi_addr;
131: } __packed;
132:
133: struct mpi_fw_tce {
134: u_int8_t reserved1;
135: u_int8_t context_size;
136: u_int8_t details_length;
137: u_int8_t flags;
138:
139: u_int32_t reserved2;
140:
141: u_int32_t image_offset;
142:
143: u_int32_t image_size;
144: } __packed;
145:
146: /*
147: * Messages
148: */
149:
150: /* functions */
151: #define MPI_FUNCTION_SCSI_IO_REQUEST (0x00)
152: #define MPI_FUNCTION_SCSI_TASK_MGMT (0x01)
153: #define MPI_FUNCTION_IOC_INIT (0x02)
154: #define MPI_FUNCTION_IOC_FACTS (0x03)
155: #define MPI_FUNCTION_CONFIG (0x04)
156: #define MPI_FUNCTION_PORT_FACTS (0x05)
157: #define MPI_FUNCTION_PORT_ENABLE (0x06)
158: #define MPI_FUNCTION_EVENT_NOTIFICATION (0x07)
159: #define MPI_FUNCTION_EVENT_ACK (0x08)
160: #define MPI_FUNCTION_FW_DOWNLOAD (0x09)
161: #define MPI_FUNCTION_TARGET_CMD_BUFFER_POST (0x0A)
162: #define MPI_FUNCTION_TARGET_ASSIST (0x0B)
163: #define MPI_FUNCTION_TARGET_STATUS_SEND (0x0C)
164: #define MPI_FUNCTION_TARGET_MODE_ABORT (0x0D)
165: #define MPI_FUNCTION_TARGET_FC_BUF_POST_LINK_SRVC (0x0E) /* obsolete */
166: #define MPI_FUNCTION_TARGET_FC_RSP_LINK_SRVC (0x0F) /* obsolete */
167: #define MPI_FUNCTION_TARGET_FC_EX_SEND_LINK_SRVC (0x10) /* obsolete */
168: #define MPI_FUNCTION_TARGET_FC_ABORT (0x11) /* obsolete */
169: #define MPI_FUNCTION_FC_LINK_SRVC_BUF_POST (0x0E)
170: #define MPI_FUNCTION_FC_LINK_SRVC_RSP (0x0F)
171: #define MPI_FUNCTION_FC_EX_LINK_SRVC_SEND (0x10)
172: #define MPI_FUNCTION_FC_ABORT (0x11)
173: #define MPI_FUNCTION_FW_UPLOAD (0x12)
174: #define MPI_FUNCTION_FC_COMMON_TRANSPORT_SEND (0x13)
175: #define MPI_FUNCTION_FC_PRIMITIVE_SEND (0x14)
176:
177: #define MPI_FUNCTION_RAID_ACTION (0x15)
178: #define MPI_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16)
179:
180: #define MPI_FUNCTION_TOOLBOX (0x17)
181:
182: #define MPI_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18)
183:
184: #define MPI_FUNCTION_MAILBOX (0x19)
185:
186: #define MPI_FUNCTION_LAN_SEND (0x20)
187: #define MPI_FUNCTION_LAN_RECEIVE (0x21)
188: #define MPI_FUNCTION_LAN_RESET (0x22)
189:
190: #define MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
191: #define MPI_FUNCTION_IO_UNIT_RESET (0x41)
192: #define MPI_FUNCTION_HANDSHAKE (0x42)
193: #define MPI_FUNCTION_REPLY_FRAME_REMOVAL (0x43)
194:
195: /* reply flags */
196: #define MPI_REP_FLAGS_CONT (1<<7) /* continuation reply */
197:
198: #define MPI_REP_IOCSTATUS_AVAIL (1<<15) /* logging info available */
199: #define MPI_REP_IOCSTATUS (0x7fff) /* status */
200:
201: /* Common IOCStatus values for all replies */
202: #define MPI_IOCSTATUS_SUCCESS (0x0000)
203: #define MPI_IOCSTATUS_INVALID_FUNCTION (0x0001)
204: #define MPI_IOCSTATUS_BUSY (0x0002)
205: #define MPI_IOCSTATUS_INVALID_SGL (0x0003)
206: #define MPI_IOCSTATUS_INTERNAL_ERROR (0x0004)
207: #define MPI_IOCSTATUS_RESERVED (0x0005)
208: #define MPI_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
209: #define MPI_IOCSTATUS_INVALID_FIELD (0x0007)
210: #define MPI_IOCSTATUS_INVALID_STATE (0x0008)
211: #define MPI_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
212: /* Config IOCStatus values */
213: #define MPI_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
214: #define MPI_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
215: #define MPI_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
216: #define MPI_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
217: #define MPI_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
218: #define MPI_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
219: /* SCSIIO Reply (SPI & FCP) initiator values */
220: #define MPI_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
221: #define MPI_IOCSTATUS_SCSI_INVALID_BUS (0x0041)
222: #define MPI_IOCSTATUS_SCSI_INVALID_TARGETID (0x0042)
223: #define MPI_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
224: #define MPI_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
225: #define MPI_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045)
226: #define MPI_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046)
227: #define MPI_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047)
228: #define MPI_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048)
229: #define MPI_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049)
230: #define MPI_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A)
231: #define MPI_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B)
232: #define MPI_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C)
233: /* For use by SCSI Initiator and SCSI Target end-to-end data protection */
234: #define MPI_IOCSTATUS_EEDP_GUARD_ERROR (0x004D)
235: #define MPI_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E)
236: #define MPI_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F)
237: /* SCSI (SPI & FCP) target values */
238: #define MPI_IOCSTATUS_TARGET_PRIORITY_IO (0x0060)
239: #define MPI_IOCSTATUS_TARGET_INVALID_PORT (0x0061)
240: #define MPI_IOCSTATUS_TARGET_INVALID_IOCINDEX (0x0062) /* obsolete */
241: #define MPI_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062)
242: #define MPI_IOCSTATUS_TARGET_ABORTED (0x0063)
243: #define MPI_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064)
244: #define MPI_IOCSTATUS_TARGET_NO_CONNECTION (0x0065)
245: #define MPI_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A)
246: #define MPI_IOCSTATUS_TARGET_STS_DATA_NOT_SENT (0x006B)
247: #define MPI_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D)
248: #define MPI_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E)
249: #define MPI_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F)
250: /* Additional FCP target values */
251: #define MPI_IOCSTATUS_TARGET_FC_ABORTED (0x0066) /* obsolete */
252: #define MPI_IOCSTATUS_TARGET_FC_RX_ID_INVALID (0x0067) /* obsolete */
253: #define MPI_IOCSTATUS_TARGET_FC_DID_INVALID (0x0068) /* obsolete */
254: #define MPI_IOCSTATUS_TARGET_FC_NODE_LOGGED_OUT (0x0069) /* obsolete */
255: /* Fibre Channel Direct Access values */
256: #define MPI_IOCSTATUS_FC_ABORTED (0x0066)
257: #define MPI_IOCSTATUS_FC_RX_ID_INVALID (0x0067)
258: #define MPI_IOCSTATUS_FC_DID_INVALID (0x0068)
259: #define MPI_IOCSTATUS_FC_NODE_LOGGED_OUT (0x0069)
260: #define MPI_IOCSTATUS_FC_EXCHANGE_CANCELED (0x006C)
261: /* LAN values */
262: #define MPI_IOCSTATUS_LAN_DEVICE_NOT_FOUND (0x0080)
263: #define MPI_IOCSTATUS_LAN_DEVICE_FAILURE (0x0081)
264: #define MPI_IOCSTATUS_LAN_TRANSMIT_ERROR (0x0082)
265: #define MPI_IOCSTATUS_LAN_TRANSMIT_ABORTED (0x0083)
266: #define MPI_IOCSTATUS_LAN_RECEIVE_ERROR (0x0084)
267: #define MPI_IOCSTATUS_LAN_RECEIVE_ABORTED (0x0085)
268: #define MPI_IOCSTATUS_LAN_PARTIAL_PACKET (0x0086)
269: #define MPI_IOCSTATUS_LAN_CANCELED (0x0087)
270: /* Serial Attached SCSI values */
271: #define MPI_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090)
272: #define MPI_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091)
273: /* Inband values */
274: #define MPI_IOCSTATUS_INBAND_ABORTED (0x0098)
275: #define MPI_IOCSTATUS_INBAND_NO_CONNECTION (0x0099)
276: /* Diagnostic Tools values */
277: #define MPI_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0)
278:
279: #define MPI_REP_IOCLOGINFO_TYPE (0xf<<28) /* logging info type */
280: #define MPI_REP_IOCLOGINFO_TYPE_NONE (0x0<<28)
281: #define MPI_REP_IOCLOGINFO_TYPE_SCSI (0x1<<28)
282: #define MPI_REP_IOCLOGINFO_TYPE_FC (0x2<<28)
283: #define MPI_REP_IOCLOGINFO_TYPE_SAS (0x3<<28)
284: #define MPI_REP_IOCLOGINFO_TYPE_ISCSI (0x4<<28)
285: #define MPI_REP_IOCLOGINFO_DATA (0x0fffffff) /* logging info data */
286:
287: /* event notification types */
288: #define MPI_EVENT_NONE 0x00
289: #define MPI_EVENT_LOG_DATA 0x01
290: #define MPI_EVENT_STATE_CHANGE 0x02
291: #define MPI_EVENT_UNIT_ATTENTION 0x03
292: #define MPI_EVENT_IOC_BUS_RESET 0x04
293: #define MPI_EVENT_EXT_BUS_RESET 0x05
294: #define MPI_EVENT_RESCAN 0x06
295: #define MPI_EVENT_LINK_STATUS_CHANGE 0x07
296: #define MPI_EVENT_LOOP_STATE_CHANGE 0x08
297: #define MPI_EVENT_LOGOUT 0x09
298: #define MPI_EVENT_EVENT_CHANGE 0x0a
299: #define MPI_EVENT_INTEGRATED_RAID 0x0b
300: #define MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE 0x0c
301: #define MPI_EVENT_ON_BUS_TIMER_EXPIRED 0x0d
302: #define MPI_EVENT_QUEUE_FULL 0x0e
303: #define MPI_EVENT_SAS_DEVICE_STATUS_CHANGE 0x0f
304: #define MPI_EVENT_SAS_SES 0x10
305: #define MPI_EVENT_PERSISTENT_TABLE_FULL 0x11
306: #define MPI_EVENT_SAS_PHY_LINK_STATUS 0x12
307: #define MPI_EVENT_SAS_DISCOVERY_ERROR 0x13
308: #define MPI_EVENT_IR_RESYNC_UPDATE 0x14
309: #define MPI_EVENT_IR2 0x15
310: #define MPI_EVENT_SAS_DISCOVERY 0x16
311: #define MPI_EVENT_LOG_ENTRY_ADDED 0x21
312:
313: /* messages */
314:
315: #define MPI_WHOINIT_NOONE 0x00
316: #define MPI_WHOINIT_SYSTEM_BIOS 0x01
317: #define MPI_WHOINIT_ROM_BIOS 0x02
318: #define MPI_WHOINIT_PCI_PEER 0x03
319: #define MPI_WHOINIT_HOST_DRIVER 0x04
320: #define MPI_WHOINIT_MANUFACTURER 0x05
321:
322: /* page address fields */
323: #define MPI_PAGE_ADDRESS_FC_BTID (1<<24) /* Bus Target ID */
324:
325: /* default messages */
326:
327: struct mpi_msg_request {
328: u_int8_t reserved1;
329: u_int8_t reserved2;
330: u_int8_t chain_offset;
331: u_int8_t function;
332:
333: u_int8_t reserved3;
334: u_int8_t reserved4;
335: u_int8_t reserved5;
336: u_int8_t msg_flags;
337:
338: u_int32_t msg_context;
339: } __packed;
340:
341: struct mpi_msg_reply {
342: u_int8_t reserved1;
343: u_int8_t reserved2;
344: u_int8_t msg_length;
345: u_int8_t function;
346:
347: u_int8_t reserved3;
348: u_int8_t reserved4;
349: u_int8_t reserved5;
350: u_int8_t msg_flags;
351:
352: u_int32_t msg_context;
353:
354: u_int8_t reserved6;
355: u_int8_t reserved7;
356: u_int16_t ioc_status;
357:
358: u_int32_t ioc_loginfo;
359: } __packed;
360:
361: /* ioc init */
362:
363: struct mpi_msg_iocinit_request {
364: u_int8_t whoinit;
365: u_int8_t reserved1;
366: u_int8_t chain_offset;
367: u_int8_t function;
368:
369: u_int8_t flags;
370: #define MPI_IOCINIT_F_DISCARD_FW (1<<0)
371: #define MPI_IOCINIT_F_ENABLE_HOST_FIFO (1<<1)
372: #define MPI_IOCINIT_F_HOST_PG_BUF_PERSIST (1<<2)
373: u_int8_t max_devices;
374: u_int8_t max_buses;
375: u_int8_t msg_flags;
376:
377: u_int32_t msg_context;
378:
379: u_int16_t reply_frame_size;
380: u_int16_t reserved2;
381:
382: u_int32_t host_mfa_hi_addr;
383:
384: u_int32_t sense_buffer_hi_addr;
385:
386: u_int32_t reply_fifo_host_signalling_addr;
387:
388: struct mpi_sge host_page_buffer_sge;
389:
390: u_int8_t msg_version_min;
391: u_int8_t msg_version_maj;
392:
393: u_int8_t hdr_version_unit;
394: u_int8_t hdr_version_dev;
395: } __packed;
396:
397: struct mpi_msg_iocinit_reply {
398: u_int8_t whoinit;
399: u_int8_t reserved1;
400: u_int8_t msg_length;
401: u_int8_t function;
402:
403: u_int8_t flags;
404: u_int8_t max_devices;
405: u_int8_t max_buses;
406: u_int8_t msg_flags;
407:
408: u_int32_t msg_context;
409:
410: u_int16_t reserved2;
411: u_int16_t ioc_status;
412:
413: u_int32_t ioc_loginfo;
414: } __packed;
415:
416:
417: /* ioc facts */
418: struct mpi_msg_iocfacts_request {
419: u_int8_t reserved1;
420: u_int8_t reserved2;
421: u_int8_t chain_offset;
422: u_int8_t function;
423:
424: u_int8_t reserved3;
425: u_int8_t reserved4;
426: u_int8_t reserved5;
427: u_int8_t msg_flags;
428:
429: u_int32_t msg_context;
430: } __packed;
431:
432: struct mpi_msg_iocfacts_reply {
433: u_int8_t msg_version_min;
434: u_int8_t msg_version_maj;
435: u_int8_t msg_length;
436: u_int8_t function;
437:
438: u_int8_t header_version_min;
439: u_int8_t header_version_maj;
440: u_int8_t ioc_number;
441: u_int8_t msg_flags;
442:
443: u_int32_t msg_context;
444:
445: u_int16_t ioc_exceptions;
446: #define MPI_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (1<<0)
447: #define MPI_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (1<<1)
448: #define MPI_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (1<<2)
449: #define MPI_IOCFACTS_EXCEPT_PERSISTENT_TABLE_FULL (1<<3)
450: u_int16_t ioc_status;
451:
452: u_int32_t ioc_loginfo;
453:
454: u_int8_t max_chain_depth;
455: u_int8_t whoinit;
456: u_int8_t block_size;
457: u_int8_t flags;
458: #define MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT (1<<0)
459: #define MPI_IOCFACTS_FLAGS_REPLY_FIFO_HOST_SIGNAL (1<<1)
460: #define MPI_IOCFACTS_FLAGS_HOST_PAGE_BUFFER_PERSISTENT (1<<2)
461:
462: u_int16_t reply_queue_depth;
463: u_int16_t request_frame_size;
464:
465: u_int16_t reserved1;
466: u_int16_t product_id; /* product id */
467:
468: u_int32_t current_host_mfa_hi_addr;
469:
470: u_int16_t global_credits;
471: u_int8_t number_of_ports;
472: u_int8_t event_state;
473:
474: u_int32_t current_sense_buffer_hi_addr;
475:
476: u_int16_t current_reply_frame_size;
477: u_int8_t max_devices;
478: u_int8_t max_buses;
479:
480: u_int32_t fw_image_size;
481:
482: u_int32_t ioc_capabilities;
483: #define MPI_IOCFACTS_CAPABILITY_HIGH_PRI_Q (1<<0)
484: #define MPI_IOCFACTS_CAPABILITY_REPLY_HOST_SIGNAL (1<<1)
485: #define MPI_IOCFACTS_CAPABILITY_QUEUE_FULL_HANDLING (1<<2)
486: #define MPI_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (1<<3)
487: #define MPI_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (1<<4)
488: #define MPI_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (1<<5)
489: #define MPI_IOCFACTS_CAPABILITY_EEDP (1<<6)
490: #define MPI_IOCFACTS_CAPABILITY_BIDIRECTIONAL (1<<7)
491: #define MPI_IOCFACTS_CAPABILITY_MULTICAST (1<<8)
492: #define MPI_IOCFACTS_CAPABILITY_SCSIIO32 (1<<9)
493: #define MPI_IOCFACTS_CAPABILITY_NO_SCSIIO16 (1<<10)
494:
495: u_int8_t fw_version_dev;
496: u_int8_t fw_version_unit;
497: u_int8_t fw_version_min;
498: u_int8_t fw_version_maj;
499:
500: u_int16_t hi_priority_queue_depth;
501: u_int16_t reserved2;
502:
503: struct mpi_sge host_page_buffer_sge;
504:
505: u_int32_t reply_fifo_host_signalling_addr;
506: } __packed;
507:
508: struct mpi_msg_portfacts_request {
509: u_int8_t reserved1;
510: u_int8_t reserved2;
511: u_int8_t chain_offset;
512: u_int8_t function;
513:
514: u_int8_t reserved3;
515: u_int8_t reserved4;
516: u_int8_t port_number;
517: u_int8_t msg_flags;
518:
519: u_int32_t msg_context;
520:
521: } __packed;
522:
523: struct mpi_msg_portfacts_reply {
524: u_int16_t reserved1;
525: u_int8_t msg_length;
526: u_int8_t function;
527:
528: u_int16_t reserved2;
529: u_int8_t port_number;
530: u_int8_t msg_flags;
531:
532: u_int32_t msg_context;
533:
534: u_int16_t reserved3;
535: u_int16_t ioc_status;
536:
537: u_int32_t ioc_loginfo;
538:
539: u_int8_t reserved4;
540: u_int8_t port_type;
541: #define MPI_PORTFACTS_PORTTYPE_INACTIVE 0x00
542: #define MPI_PORTFACTS_PORTTYPE_SCSI 0x01
543: #define MPI_PORTFACTS_PORTTYPE_FC 0x10
544: #define MPI_PORTFACTS_PORTTYPE_ISCSI 0x20
545: #define MPI_PORTFACTS_PORTTYPE_SAS 0x30
546:
547: u_int16_t max_devices;
548:
549: u_int16_t port_scsi_id;
550: u_int16_t protocol_flags;
551: #define MPI_PORTFACTS_PROTOCOL_LOGBUSADDR (1<<0)
552: #define MPI_PORTFACTS_PROTOCOL_LAN (1<<1)
553: #define MPI_PORTFACTS_PROTOCOL_TARGET (1<<2)
554: #define MPI_PORTFACTS_PROTOCOL_INITIATOR (1<<3)
555:
556: u_int16_t max_posted_cmd_buffers;
557: u_int16_t max_persistent_ids;
558:
559: u_int16_t max_lan_buckets;
560: u_int16_t reserved5;
561:
562: u_int32_t reserved6;
563: } __packed;
564:
565: struct mpi_msg_portenable_request {
566: u_int16_t reserved1;
567: u_int8_t chain_offset;
568: u_int8_t function;
569:
570: u_int16_t reserved2;
571: u_int8_t port_number;
572: u_int8_t msg_flags;
573:
574: u_int32_t msg_context;
575: } __packed;
576:
577: struct mpi_msg_portenable_reply {
578: u_int16_t reserved1;
579: u_int8_t msg_length;
580: u_int8_t function;
581:
582: u_int16_t reserved2;
583: u_int8_t port_number;
584: u_int8_t msg_flags;
585:
586: u_int32_t msg_context;
587:
588: u_int16_t reserved3;
589: u_int16_t ioc_status;
590:
591: u_int32_t ioc_loginfo;
592: } __packed;
593:
594: struct mpi_msg_event_request {
595: u_int8_t event_switch;
596: #define MPI_EVENT_SWITCH_ON (0x01)
597: #define MPI_EVENT_SWITCH_OFF (0x00)
598: u_int8_t reserved1;
599: u_int8_t chain_offset;
600: u_int8_t function;
601:
602: u_int8_t reserved2[3];
603: u_int8_t msg_flags;
604:
605: u_int32_t msg_context;
606: } __packed;
607:
608: struct mpi_msg_event_reply {
609: u_int16_t data_length;
610: u_int8_t msg_length;
611: u_int8_t function;
612:
613: u_int16_t reserved1;
614: u_int8_t ack_required;
615: #define MPI_EVENT_ACK_REQUIRED (0x01)
616: u_int8_t msg_flags;
617: #define MPI_EVENT_FLAGS_REPLY_KEPT (1<<7)
618:
619: u_int32_t msg_context;
620:
621: u_int16_t reserved2;
622: u_int16_t ioc_status;
623:
624: u_int32_t ioc_loginfo;
625:
626: u_int32_t event;
627:
628: u_int32_t event_context;
629:
630: /* event data follows */
631: } __packed;
632:
633: struct mpi_evt_change {
634: u_int8_t event_state;
635: u_int8_t reserved[3];
636: } __packed;
637:
638: struct mpi_evt_sas_phy {
639: u_int8_t phy_num;
640: u_int8_t link_rates;
641: #define MPI_EVT_SASPHY_LINK_CUR(x) (((x) & 0xf0) >> 4)
642: #define MPI_EVT_SASPHY_LINK_PREV(x) ((x) & 0x0f)
643: #define MPI_EVT_SASPHY_LINK_ENABLED 0x0
644: #define MPI_EVT_SASPHY_LINK_DISABLED 0x1
645: #define MPI_EVT_SASPHY_LINK_NEGFAIL 0x2
646: #define MPI_EVT_SASPHY_LINK_SATAOOB 0x3
647: #define MPI_EVT_SASPHY_LINK_1_5GBPS 0x8
648: #define MPI_EVT_SASPHY_LINK_3_0GBPS 0x9
649: u_int16_t dev_handle;
650:
651: u_int64_t sas_addr;
652: } __packed;
653:
654: struct mpi_evt_sas_change {
655: u_int8_t target;
656: u_int8_t bus;
657: u_int8_t reason;
658: #define MPI_EVT_SASCH_REASON_ADDED 0x03
659: #define MPI_EVT_SASCH_REASON_NOT_RESPONDING 0x04
660: #define MPI_EVT_SASCH_REASON_SMART_DATA 0x05
661: #define MPI_EVT_SASCH_REASON_NO_PERSIST_ADDED 0x06
662: #define MPI_EVT_SASCH_REASON_UNSUPPORTED 0x07
663: #define MPI_EVT_SASCH_REASON_INTERNAL_RESET 0x08
664: u_int8_t reserved1;
665:
666: u_int8_t asc;
667: u_int8_t ascq;
668: u_int16_t dev_handle;
669:
670: u_int32_t device_info;
671: #define MPI_EVT_SASCH_INFO_ATAPI (1<<13)
672: #define MPI_EVT_SASCH_INFO_LSI (1<<12)
673: #define MPI_EVT_SASCH_INFO_DIRECT_ATTACHED (1<<11)
674: #define MPI_EVT_SASCH_INFO_SSP (1<<10)
675: #define MPI_EVT_SASCH_INFO_STP (1<<9)
676: #define MPI_EVT_SASCH_INFO_SMP (1<<8)
677: #define MPI_EVT_SASCH_INFO_SATA (1<<7)
678: #define MPI_EVT_SASCH_INFO_SSP_INITIATOR (1<<6)
679: #define MPI_EVT_SASCH_INFO_STP_INITIATOR (1<<5)
680: #define MPI_EVT_SASCH_INFO_SMP_INITIATOR (1<<4)
681: #define MPI_EVT_SASCH_INFO_SATA_HOST (1<<3)
682: #define MPI_EVT_SASCH_INFO_TYPE_MASK 0x7
683: #define MPI_EVT_SASCH_INFO_TYPE_NONE 0x0
684: #define MPI_EVT_SASCH_INFO_TYPE_END 0x1
685: #define MPI_EVT_SASCH_INFO_TYPE_EDGE 0x2
686: #define MPI_EVT_SASCH_INFO_TYPE_FANOUT 0x3
687:
688: u_int16_t parent_dev_handle;
689: u_int8_t phy_num;
690: u_int8_t reserved2;
691:
692: u_int64_t sas_addr;
693: } __packed;
694:
695: struct mpi_msg_eventack_request {
696: u_int16_t reserved1;
697: u_int8_t chain_offset;
698: u_int8_t function;
699:
700: u_int8_t reserved2[3];
701: u_int8_t msg_flags;
702:
703: u_int32_t msg_context;
704:
705: u_int32_t event;
706:
707: u_int32_t event_context;
708: } __packed;
709:
710: struct mpi_msg_eventack_reply {
711: u_int16_t reserved1;
712: u_int8_t msg_length;
713: u_int8_t function;
714:
715: u_int8_t reserved2[3];
716: u_int8_t msg_flags;
717:
718: u_int32_t msg_context;
719:
720: u_int16_t reserved3;
721: u_int32_t ioc_status;
722:
723: u_int32_t ioc_loginfo;
724: } __packed;
725:
726: struct mpi_msg_fwupload_request {
727: u_int8_t image_type;
728: #define MPI_FWUPLOAD_IMAGETYPE_IOC_FW (0x00)
729: #define MPI_FWUPLOAD_IMAGETYPE_NV_FW (0x01)
730: #define MPI_FWUPLOAD_IMAGETYPE_MPI_NV_FW (0x02)
731: #define MPI_FWUPLOAD_IMAGETYPE_NV_DATA (0x03)
732: #define MPI_FWUPLOAD_IMAGETYPE_BOOT (0x04)
733: #define MPI_FWUPLOAD_IMAGETYPE_NV_BACKUP (0x05)
734: u_int8_t reserved1;
735: u_int8_t chain_offset;
736: u_int8_t function;
737:
738: u_int8_t reserved2[3];
739: u_int8_t msg_flags;
740:
741: u_int32_t msg_context;
742:
743: struct mpi_fw_tce tce;
744:
745: /* followed by an sgl */
746: } __packed;
747:
748: struct mpi_msg_fwupload_reply {
749: u_int8_t image_type;
750: u_int8_t reserved1;
751: u_int8_t msg_length;
752: u_int8_t function;
753:
754: u_int8_t reserved2[3];
755: u_int8_t msg_flags;
756:
757: u_int32_t msg_context;
758:
759: u_int16_t reserved3;
760: u_int16_t ioc_status;
761:
762: u_int32_t ioc_loginfo;
763:
764: u_int32_t actual_image_size;
765: } __packed;
766:
767: struct mpi_msg_scsi_io {
768: u_int8_t target_id;
769: u_int8_t bus;
770: u_int8_t chain_offset;
771: u_int8_t function;
772:
773: u_int8_t cdb_length;
774: u_int8_t sense_buf_len;
775: u_int8_t reserved1;
776: u_int8_t msg_flags;
777: #define MPI_SCSIIO_EEDP 0xf0
778: #define MPI_SCSIIO_CMD_DATA_DIR (1<<2)
779: #define MPI_SCSIIO_SENSE_BUF_LOC (1<<1)
780: #define MPI_SCSIIO_SENSE_BUF_ADDR_WIDTH (1<<0)
781: #define MPI_SCSIIO_SENSE_BUF_ADDR_WIDTH_32 (0<<0)
782: #define MPI_SCSIIO_SENSE_BUF_ADDR_WIDTH_64 (1<<0)
783:
784: u_int32_t msg_context;
785:
786: u_int16_t lun[4];
787:
788: u_int8_t reserved2;
789: u_int8_t tagging;
790: #define MPI_SCSIIO_ATTR_SIMPLE_Q (0x0)
791: #define MPI_SCSIIO_ATTR_HEAD_OF_Q (0x1)
792: #define MPI_SCSIIO_ATTR_ORDERED_Q (0x2)
793: #define MPI_SCSIIO_ATTR_ACA_Q (0x4)
794: #define MPI_SCSIIO_ATTR_UNTAGGED (0x5)
795: #define MPI_SCSIIO_ATTR_NO_DISCONNECT (0x7)
796: u_int8_t reserved3;
797: u_int8_t direction;
798: #define MPI_SCSIIO_DIR_NONE (0x0)
799: #define MPI_SCSIIO_DIR_WRITE (0x1)
800: #define MPI_SCSIIO_DIR_READ (0x2)
801:
802: #define MPI_CDB_LEN 16
803: u_int8_t cdb[MPI_CDB_LEN];
804:
805: u_int32_t data_length;
806:
807: u_int32_t sense_buf_low_addr;
808:
809: /* followed by an sgl */
810: } __packed;
811:
812: struct mpi_msg_scsi_io_error {
813: u_int8_t target_id;
814: u_int8_t bus;
815: u_int8_t msg_length;
816: u_int8_t function;
817:
818: u_int8_t cdb_length;
819: u_int8_t sense_buf_len;
820: u_int8_t reserved1;
821: u_int8_t msg_flags;
822:
823: u_int32_t msg_context;
824:
825: u_int8_t scsi_status;
826: #if notyet
827: #define MPI_SCSIIO_ERR_STATUS_SUCCESS
828: #define MPI_SCSIIO_ERR_STATUS_CHECK_COND
829: #define MPI_SCSIIO_ERR_STATUS_BUSY
830: #define MPI_SCSIIO_ERR_STATUS_INTERMEDIATE
831: #define MPI_SCSIIO_ERR_STATUS_INTERMEDIATE_CONDMET
832: #define MPI_SCSIIO_ERR_STATUS_RESERVATION_CONFLICT
833: #define MPI_SCSIIO_ERR_STATUS_CMD_TERM
834: #define MPI_SCSIIO_ERR_STATUS_TASK_SET_FULL
835: #define MPI_SCSIIO_ERR_STATUS_ACA_ACTIVE
836: #endif
837: u_int8_t scsi_state;
838: #define MPI_SCSIIO_ERR_STATE_AUTOSENSE_VALID (1<<0)
839: #define MPI_SCSIIO_ERR_STATE_AUTOSENSE_FAILED (1<<2)
840: #define MPI_SCSIIO_ERR_STATE_NO_SCSI_STATUS (1<<3)
841: #define MPI_SCSIIO_ERR_STATE_TERMINATED (1<<4)
842: #define MPI_SCSIIO_ERR_STATE_RESPONSE_INFO_VALID (1<<5)
843: #define MPI_SCSIIO_ERR_STATE_QUEUE_TAG_REJECTED (1<<6)
844: u_int16_t ioc_status;
845:
846: u_int32_t ioc_loginfo;
847:
848: u_int32_t transfer_count;
849:
850: u_int32_t sense_count;
851:
852: u_int32_t response_info;
853:
854: u_int16_t tag;
855: u_int16_t reserved2;
856: } __packed;
857:
858: struct mpi_msg_scsi_task_request {
859: u_int8_t target_id;
860: u_int8_t bus;
861: u_int8_t chain_offset;
862: u_int8_t function;
863:
864: u_int8_t reserved1;
865: u_int8_t task_type;
866: #define MPI_MSG_SCSI_TASK_TYPE_ABORT_TASK (0x01)
867: #define MPI_MSG_SCSI_TASK_TYPE_ABRT_TASK_SET (0x02)
868: #define MPI_MSG_SCSI_TASK_TYPE_TARGET_RESET (0x03)
869: #define MPI_MSG_SCSI_TASK_TYPE_RESET_BUS (0x04)
870: #define MPI_MSG_SCSI_TASK_TYPE_LOGICAL_UNIT_RESET (0x05)
871: u_int8_t reserved2;
872: u_int8_t msg_flags;
873:
874: u_int32_t msg_context;
875:
876: u_int16_t lun[4];
877:
878: u_int32_t reserved3[7]; /* wtf? */
879:
880: u_int32_t target_msg_context;
881: } __packed;
882:
883: struct mpi_msg_scsi_task_reply {
884: u_int8_t target_id;
885: u_int8_t bus;
886: u_int8_t msg_length;
887: u_int8_t function;
888:
889: u_int8_t response_code;
890: u_int8_t task_type;
891: u_int8_t reserved1;
892: u_int8_t msg_flags;
893:
894: u_int32_t msg_context;
895:
896: u_int16_t reserved2;
897: u_int16_t ioc_status;
898:
899: u_int32_t ioc_loginfo;
900:
901: u_int32_t termination_count;
902: } __packed;
903:
904: struct mpi_cfg_hdr {
905: u_int8_t page_version;
906: u_int8_t page_length;
907: u_int8_t page_number;
908: u_int8_t page_type;
909: #define MPI_CONFIG_REQ_PAGE_TYPE_ATTRIBUTE (0xf0)
910: #define MPI_CONFIG_REQ_PAGE_TYPE_MASK (0x0f)
911: #define MPI_CONFIG_REQ_PAGE_TYPE_IO_UNIT (0x00)
912: #define MPI_CONFIG_REQ_PAGE_TYPE_IOC (0x01)
913: #define MPI_CONFIG_REQ_PAGE_TYPE_BIOS (0x02)
914: #define MPI_CONFIG_REQ_PAGE_TYPE_SCSI_SPI_PORT (0x03)
915: #define MPI_CONFIG_REQ_PAGE_TYPE_SCSI_SPI_DEV (0x04)
916: #define MPI_CONFIG_REQ_PAGE_TYPE_FC_PORT (0x05)
917: #define MPI_CONFIG_REQ_PAGE_TYPE_FC_DEV (0x06)
918: #define MPI_CONFIG_REQ_PAGE_TYPE_LAN (0x07)
919: #define MPI_CONFIG_REQ_PAGE_TYPE_RAID_VOL (0x08)
920: #define MPI_CONFIG_REQ_PAGE_TYPE_MANUFACTURING (0x09)
921: #define MPI_CONFIG_REQ_PAGE_TYPE_RAID_PD (0x0A)
922: #define MPI_CONFIG_REQ_PAGE_TYPE_INBAND (0x0B)
923: #define MPI_CONFIG_REQ_PAGE_TYPE_EXTENDED (0x0F)
924: } __packed;
925:
926: struct mpi_msg_config_request {
927: u_int8_t action;
928: #define MPI_CONFIG_REQ_ACTION_PAGE_HEADER (0x00)
929: #define MPI_CONFIG_REQ_ACTION_PAGE_READ_CURRENT (0x01)
930: #define MPI_CONFIG_REQ_ACTION_PAGE_WRITE_CURRENT (0x02)
931: #define MPI_CONFIG_REQ_ACTION_PAGE_DEFAULT (0x03)
932: #define MPI_CONFIG_REQ_ACTION_PAGE_WRITE_NVRAM (0x04)
933: #define MPI_CONFIG_REQ_ACTION_PAGE_READ_DEFAULT (0x05)
934: #define MPI_CONFIG_REQ_ACTION_PAGE_READ_NVRAM (0x06)
935: u_int8_t reserved1;
936: u_int8_t chain_offset;
937: u_int8_t function;
938:
939: u_int16_t ext_page_len;
940: u_int8_t ext_page_type;
941: #define MPI_CONFIG_REQ_EXTPAGE_TYPE_SAS_IO_UNIT (0x10)
942: #define MPI_CONFIG_REQ_EXTPAGE_TYPE_SAS_EXPANDER (0x11)
943: #define MPI_CONFIG_REQ_EXTPAGE_TYPE_SAS_DEVICE (0x12)
944: #define MPI_CONFIG_REQ_EXTPAGE_TYPE_SAS_PHY (0x13)
945: #define MPI_CONFIG_REQ_EXTPAGE_TYPE_LOG (0x14)
946: u_int8_t msg_flags;
947:
948: u_int32_t msg_context;
949:
950: u_int32_t reserved2[2];
951:
952: struct mpi_cfg_hdr config_header;
953:
954: u_int32_t page_address;
955: /* XXX lots of defns here */
956:
957: struct mpi_sge page_buffer;
958: } __packed;
959:
960: struct mpi_msg_config_reply {
961: u_int8_t action;
962: u_int8_t reserved1;
963: u_int8_t msg_length;
964: u_int8_t function;
965:
966: u_int16_t ext_page_length;
967: u_int8_t ext_page_type;
968: u_int8_t msg_flags;
969:
970: u_int32_t msg_context;
971:
972: u_int16_t reserved2;
973: u_int16_t ioc_status;
974:
975: u_int32_t ioc_loginfo;
976:
977: struct mpi_cfg_hdr config_header;
978: } __packed;
979:
980: struct mpi_cfg_spi_port_pg0 {
981: struct mpi_cfg_hdr config_header;
982:
983: u_int8_t capabilities1;
984: #define MPI_CFG_SPI_PORT_0_CAPABILITIES_PACKETIZED (1<<0)
985: #define MPI_CFG_SPI_PORT_0_CAPABILITIES_DT (1<<1)
986: #define MPI_CFG_SPI_PORT_0_CAPABILITIES_QAS (1<<2)
987: u_int8_t min_period;
988: u_int8_t max_offset;
989: u_int8_t capabilities2;
990: #define MPI_CFG_SPI_PORT_0_CAPABILITIES_IDP (1<<3)
991: #define MPI_CFG_SPI_PORT_0_CAPABILITIES_WIDTH (1<<5)
992: #define MPI_CFG_SPI_PORT_0_CAPABILITIES_WIDTH_NARROW (0<<5)
993: #define MPI_CFG_SPI_PORT_0_CAPABILITIES_WIDTH_WIDE (1<<5)
994: #define MPI_CFG_SPI_PORT_0_CAPABILITIES_AIP (1<<7)
995:
996: u_int8_t signalling_type;
997: #define MPI_CFG_SPI_PORT_0_SIGNAL_HVD (0x1)
998: #define MPI_CFG_SPI_PORT_0_SIGNAL_SE (0x2)
999: #define MPI_CFG_SPI_PORT_0_SIGNAL_LVD (0x3)
1000: u_int16_t reserved;
1001: u_int8_t connected_id;
1002: #define MPI_CFG_SPI_PORT_0_CONNECTEDID_BUSFREE (0xfe)
1003: #define MPI_CFG_SPI_PORT_0_CONNECTEDID_UNKNOWN (0xff)
1004: } __packed;
1005:
1006: struct mpi_cfg_spi_port_pg1 {
1007: struct mpi_cfg_hdr config_header;
1008:
1009: /* configuration */
1010: u_int8_t port_scsi_id;
1011: u_int8_t reserved1;
1012: u_int16_t port_resp_ids;
1013:
1014: u_int32_t on_bus_timer_value;
1015:
1016: u_int8_t target_config;
1017: #define MPI_CFG_SPI_PORT_1_TARGCFG_TARGET_ONLY (0x01)
1018: #define MPI_CFG_SPI_PORT_1_TARGCFG_INIT_TARGET (0x02)
1019: u_int8_t reserved2;
1020: u_int16_t id_config;
1021: } __packed;
1022:
1023: struct mpi_cfg_spi_port_pg2 {
1024: struct mpi_cfg_hdr config_header;
1025:
1026: u_int32_t port_flags;
1027: #define MPI_CFG_SPI_PORT_2_PORT_FLAGS_SCAN_HI2LOW (1<<0)
1028: #define MPI_CFG_SPI_PORT_2_PORT_FLAGS_AVOID_RESET (1<<2)
1029: #define MPI_CFG_SPI_PORT_2_PORT_FLAGS_ALT_CHS (1<<3)
1030: #define MPI_CFG_SPI_PORT_2_PORT_FLAGS_TERM_DISABLED (1<<4)
1031: #define MPI_CFG_SPI_PORT_2_PORT_FLAGS_DV_CTL (0x3<<5)
1032: #define MPI_CFG_SPI_PORT_2_PORT_FLAGS_DV_HOST_BE (0x0<<5)
1033: #define MPI_CFG_SPI_PORT_2_PORT_FLAGS_DV_HOST_B (0x1<<5)
1034: #define MPI_CFG_SPI_PORT_2_PORT_FLAGS_DV_HOST_NONE (0x3<<5)
1035:
1036: u_int32_t port_settings;
1037: #define MPI_CFG_SPI_PORT_2_PORT_SET_HOST_ID (0x7<<0)
1038: #define MPI_CFG_SPI_PORT_2_PORT_SET_INIT_HBA (0x3<<4)
1039: #define MPI_CFG_SPI_PORT_2_PORT_SET_INIT_HBA_DISABLED (0x0<<4)
1040: #define MPI_CFG_SPI_PORT_2_PORT_SET_INIT_HBA_BIOS (0x1<<4)
1041: #define MPI_CFG_SPI_PORT_2_PORT_SET_INIT_HBA_OS (0x2<<4)
1042: #define MPI_CFG_SPI_PORT_2_PORT_SET_INIT_HBA_BIOS_OS (0x3<<4)
1043: #define MPI_CFG_SPI_PORT_2_PORT_SET_REMOVABLE (0x3<<6)
1044: #define MPI_CFG_SPI_PORT_2_PORT_SET_SPINUP_DELAY (0xf<<8)
1045: #define MPI_CFG_SPI_PORT_2_PORT_SET_SYNC (0x3<<12)
1046: #define MPI_CFG_SPI_PORT_2_PORT_SET_NEG_SUPPORTED (0x0<<12)
1047: #define MPI_CFG_SPI_PORT_2_PORT_SET_NEG_NONE (0x1<<12)
1048: #define MPI_CFG_SPI_PORT_2_PORT_SET_NEG_ALL (0x3<<12)
1049:
1050: struct {
1051: u_int8_t timeout;
1052: u_int8_t sync_factor;
1053: u_int16_t device_flags;
1054: #define MPI_CFG_SPI_PORT_2_DEV_FLAG_DISCONNECT_EN (1<<0)
1055: #define MPI_CFG_SPI_PORT_2_DEV_FLAG_SCAN_ID_EN (1<<1)
1056: #define MPI_CFG_SPI_PORT_2_DEV_FLAG_SCAN_LUN_EN (1<<2)
1057: #define MPI_CFG_SPI_PORT_2_DEV_FLAG_TAQ_Q_EN (1<<3)
1058: #define MPI_CFG_SPI_PORT_2_DEV_FLAG_WIDE_DIS (1<<4)
1059: #define MPI_CFG_SPI_PORT_2_DEV_FLAG_BOOT_CHOICE (1<<5)
1060: } __packed device_settings[16];
1061: };
1062:
1063: struct mpi_cfg_spi_dev_pg0 {
1064: struct mpi_cfg_hdr config_header;
1065:
1066: u_int8_t neg_params1;
1067: #define MPI_CFG_SPI_DEV_0_NEGPARAMS_PACKETIZED (1<<0)
1068: #define MPI_CFG_SPI_DEV_0_NEGPARAMS_DUALXFERS (1<<1)
1069: #define MPI_CFG_SPI_DEV_0_NEGPARAMS_QAS (1<<2)
1070: #define MPI_CFG_SPI_DEV_0_NEGPARAMS_HOLD_MCS (1<<3)
1071: #define MPI_CFG_SPI_DEV_0_NEGPARAMS_WR_FLOW (1<<4)
1072: #define MPI_CFG_SPI_DEV_0_NEGPARAMS_RD_STRM (1<<5)
1073: #define MPI_CFG_SPI_DEV_0_NEGPARAMS_RTI (1<<6)
1074: #define MPI_CFG_SPI_DEV_0_NEGPARAMS_PCOMP_EN (1<<7)
1075: u_int8_t neg_period;
1076: u_int8_t neg_offset;
1077: u_int8_t neg_params2;
1078: #define MPI_CFG_SPI_DEV_0_NEGPARAMS_IDP_EN (1<<3)
1079: #define MPI_CFG_SPI_DEV_0_NEGPARAMS_WIDTH (1<<5)
1080: #define MPI_CFG_SPI_DEV_0_NEGPARAMS_WIDTH_NARROW (0<<5)
1081: #define MPI_CFG_SPI_DEV_0_NEGPARAMS_WIDTH_WIDE (1<<5)
1082: #define MPI_CFG_SPI_DEV_0_NEGPARAMS_AIP (1<<7)
1083:
1084: u_int32_t information;
1085: #define MPI_CFG_SPI_DEV_0_INFO_NEG_OCCURRED (1<<0)
1086: #define MPI_CFG_SPI_DEV_0_INFO_SDTR_REJECTED (1<<1)
1087: #define MPI_CFG_SPI_DEV_0_INFO_WDTR_REJECTED (1<<2)
1088: #define MPI_CFG_SPI_DEV_0_INFO_PPR_REJECTED (1<<3)
1089: } __packed;
1090:
1091: struct mpi_cfg_spi_dev_pg1 {
1092: struct mpi_cfg_hdr config_header;
1093:
1094: u_int8_t req_params1;
1095: #define MPI_CFG_SPI_DEV_1_REQPARAMS_PACKETIZED (1<<0)
1096: #define MPI_CFG_SPI_DEV_1_REQPARAMS_DUALXFERS (1<<1)
1097: #define MPI_CFG_SPI_DEV_1_REQPARAMS_QAS (1<<2)
1098: #define MPI_CFG_SPI_DEV_1_REQPARAMS_HOLD_MCS (1<<3)
1099: #define MPI_CFG_SPI_DEV_1_REQPARAMS_WR_FLOW (1<<4)
1100: #define MPI_CFG_SPI_DEV_1_REQPARAMS_RD_STRM (1<<5)
1101: #define MPI_CFG_SPI_DEV_1_REQPARAMS_RTI (1<<6)
1102: #define MPI_CFG_SPI_DEV_1_REQPARAMS_PCOMP_EN (1<<7)
1103: u_int8_t req_period;
1104: u_int8_t req_offset;
1105: u_int8_t req_params2;
1106: #define MPI_CFG_SPI_DEV_1_REQPARAMS_IDP_EN (1<<3)
1107: #define MPI_CFG_SPI_DEV_1_REQPARAMS_WIDTH (1<<5)
1108: #define MPI_CFG_SPI_DEV_1_REQPARAMS_WIDTH_NARROW (0<<5)
1109: #define MPI_CFG_SPI_DEV_1_REQPARAMS_WIDTH_WIDE (1<<5)
1110: #define MPI_CFG_SPI_DEV_1_REQPARAMS_AIP (1<<7)
1111:
1112: u_int32_t reserved;
1113:
1114: u_int32_t configuration;
1115: #define MPI_CFG_SPI_DEV_1_CONF_WDTR_DISALLOWED (1<<1)
1116: #define MPI_CFG_SPI_DEV_1_CONF_SDTR_DISALLOWED (1<<2)
1117: #define MPI_CFG_SPI_DEV_1_CONF_EXTPARAMS (1<<3)
1118: #define MPI_CFG_SPI_DEV_1_CONF_FORCE_PPR (1<<4)
1119: } __packed;
1120:
1121: struct mpi_cfg_spi_dev_pg2 {
1122: struct mpi_cfg_hdr config_header;
1123:
1124: u_int32_t domain_validation;
1125: #define MPI_CFG_SPI_DEV_2_DV_ISI_ENABLED (1<<4)
1126: #define MPI_CFG_SPI_DEV_2_DV_SECONDARY_DRV_EN (1<<5)
1127: #define MPI_CFG_SPI_DEV_2_DV_SLEW_RATE_CTL (0x7<<7)
1128: #define MPI_CFG_SPI_DEV_2_DV_PRIMARY_DRV_STRENGTH (0x7<<10)
1129: #define MPI_CFG_SPI_DEV_2_DV_XCLKH_ST (1<<28)
1130: #define MPI_CFG_SPI_DEV_2_DV_XCLKS_ST (1<<29)
1131: #define MPI_CFG_SPI_DEV_2_DV_XCLKH_DT (1<<30)
1132: #define MPI_CFG_SPI_DEV_2_DV_XCLKS_DT (1<<31)
1133:
1134: u_int32_t parity_pipe_select;
1135: #define MPI_CFG_SPI_DEV_2_PARITY_PIPE_SELECT (0x3)
1136:
1137: u_int32_t data_pipe_select;
1138: #define MPI_CFG_SPI_DEV_2_DATA_PIPE_SELECT(x) (0x3<<((x)*2))
1139:
1140: } __packed;
1141:
1142: struct mpi_cfg_spi_dev_pg3 {
1143: struct mpi_cfg_hdr config_header;
1144:
1145: u_int16_t msg_reject_count;
1146: u_int16_t phase_error_count;
1147:
1148: u_int16_t parity_error_count;
1149: u_int16_t reserved;
1150: } __packed;
1151:
1152: struct mpi_cfg_manufacturing_pg0 {
1153: struct mpi_cfg_hdr config_header;
1154:
1155: char chip_name[16];
1156: char chip_revision[8];
1157: char board_name[16];
1158: char board_assembly[16];
1159: char board_tracer_number[16];
1160: } __packed;
1161:
1162: struct mpi_cfg_ioc_pg2 {
1163: struct mpi_cfg_hdr config_header;
1164:
1165: u_int32_t capabilities;
1166: #define MPI_CFG_IOC_2_CAPABILITIES_IS (1<<0)
1167: #define MPI_CFG_IOC_2_CAPABILITIES_IME (1<<1)
1168: #define MPI_CFG_IOC_2_CAPABILITIES_IM (1<<2)
1169: #define MPI_CFG_IOC_2_CAPABILITIES_RAID ( \
1170: MPI_CFG_IOC_2_CAPABILITIES_IS | MPI_CFG_IOC_2_CAPABILITIES_IME | \
1171: MPI_CFG_IOC_2_CAPABILITIES_IM)
1172: #define MPI_CFG_IOC_2_CAPABILITIES_SES (1<<29)
1173: #define MPI_CFG_IOC_2_CAPABILITIES_SAFTE (1<<30)
1174: #define MPI_CFG_IOC_2_CAPABILITIES_XCHANNEL (1<<31)
1175:
1176: u_int8_t active_vols;
1177: u_int8_t max_vols;
1178: u_int8_t active_physdisks;
1179: u_int8_t max_physdisks;
1180:
1181: /* followed by a list of mpi_cf_raid_vol structs */
1182: } __packed;
1183:
1184: struct mpi_cfg_raid_vol {
1185: u_int8_t vol_id;
1186: u_int8_t vol_bus;
1187: u_int8_t vol_ioc;
1188: u_int8_t vol_page;
1189:
1190: u_int8_t vol_type;
1191: #define MPI_CFG_RAID_TYPE_RAID_IS (0x00)
1192: #define MPI_CFG_RAID_TYPE_RAID_IME (0x01)
1193: #define MPI_CFG_RAID_TYPE_RAID_IM (0x02)
1194: u_int8_t flags;
1195: #define MPI_CFG_RAID_VOL_INACTIVE (1<<3)
1196: u_int16_t reserved;
1197: } __packed;
1198:
1199: struct mpi_cfg_ioc_pg3 {
1200: struct mpi_cfg_hdr config_header;
1201:
1202: u_int8_t no_phys_disks;
1203: u_int8_t reserved[3];
1204:
1205: /* followed by a list of mpi_cf_raid_physdisk structs */
1206: } __packed;
1207:
1208: struct mpi_cfg_raid_physdisk {
1209: u_int8_t phys_disk_id;
1210: u_int8_t phys_disk_bus;
1211: u_int8_t phys_disk_ioc;
1212: u_int8_t phys_disk_num;
1213: } __packed;
1214:
1215: struct mpi_cfg_fc_port_pg0 {
1216: struct mpi_cfg_hdr config_header;
1217:
1218: u_int32_t flags;
1219:
1220: u_int8_t mpi_port_nr;
1221: u_int8_t link_type;
1222: u_int8_t port_state;
1223: u_int8_t reserved1;
1224:
1225: u_int32_t port_id;
1226:
1227: u_int64_t wwnn;
1228:
1229: u_int64_t wwpn;
1230:
1231: u_int32_t supported_service_class;
1232:
1233: u_int32_t supported_speeds;
1234:
1235: u_int32_t current_speed;
1236:
1237: u_int32_t max_frame_size;
1238:
1239: u_int64_t fabric_wwnn;
1240:
1241: u_int64_t fabric_wwpn;
1242:
1243: u_int32_t discovered_port_count;
1244:
1245: u_int32_t max_initiators;
1246:
1247: u_int8_t max_aliases_supported;
1248: u_int8_t max_hard_aliases_supported;
1249: u_int8_t num_current_aliases;
1250: u_int8_t reserved2;
1251: } __packed;
1252:
1253: struct mpi_cfg_fc_device_pg0 {
1254: struct mpi_cfg_hdr config_header;
1255:
1256: u_int64_t wwnn;
1257:
1258: u_int64_t wwpn;
1259:
1260: u_int32_t port_id;
1261:
1262: u_int8_t protocol;
1263: u_int8_t flags;
1264: u_int16_t bb_credit;
1265:
1266: u_int16_t max_rx_frame_size;
1267: u_int8_t adisc_hard_alpa;
1268: u_int8_t port_nr;
1269:
1270: u_int8_t fc_ph_low_version;
1271: u_int8_t fc_ph_high_version;
1272: u_int8_t current_target_id;
1273: u_int8_t current_bus;
1274: } __packed;
1275:
1276: struct mpi_cfg_raid_vol_pg0 {
1277: struct mpi_cfg_hdr config_header;
1278:
1279: u_int8_t volume_id;
1280: u_int8_t volume_bus;
1281: u_int8_t volume_ioc;
1282: u_int8_t volume_type;
1283:
1284: u_int8_t volume_status;
1285: #define MPI_CFG_RAID_VOL_0_STATUS_ENABLED (1<<0)
1286: #define MPI_CFG_RAID_VOL_0_STATUS_QUIESCED (1<<1)
1287: #define MPI_CFG_RAID_VOL_0_STATUS_RESYNCING (1<<2)
1288: #define MPI_CFG_RAID_VOL_0_STATUS_ACTIVE (1<<3)
1289: u_int8_t volume_state;
1290: #define MPI_CFG_RAID_VOL_0_STATE_OPTIMAL (0x00)
1291: #define MPI_CFG_RAID_VOL_0_STATE_DEGRADED (0x01)
1292: #define MPI_CFG_RAID_VOL_0_STATE_FAILED (0x02)
1293: u_int16_t reserved1;
1294:
1295: u_int16_t volume_settings;
1296: #define MPI_CFG_RAID_VOL_0_SETTINGS_WRITE_CACHE_EN (1<<0)
1297: #define MPI_CFG_RAID_VOL_0_SETTINGS_OFFLINE_SMART_ERR (1<<1)
1298: #define MPI_CFG_RAID_VOL_0_SETTINGS_OFFLINE_SMART (1<<2)
1299: #define MPI_CFG_RAID_VOL_0_SETTINGS_AUTO_SWAP (1<<3)
1300: #define MPI_CFG_RAID_VOL_0_SETTINGS_HI_PRI_RESYNC (1<<4)
1301: #define MPI_CFG_RAID_VOL_0_SETTINGS_PROD_SUFFIX (1<<5)
1302: #define MPI_CFG_RAID_VOL_0_SETTINGS_FAST_SCRUB (1<<6) /* obsolete */
1303: #define MPI_CFG_RAID_VOL_0_SETTINGS_DEFAULTS (1<<15)
1304: u_int8_t hot_spare_pool;
1305: u_int8_t reserved2;
1306:
1307: u_int32_t max_lba;
1308:
1309: u_int32_t reserved3;
1310:
1311: u_int32_t stripe_size;
1312:
1313: u_int32_t reserved4;
1314:
1315: u_int32_t reserved5;
1316:
1317: u_int8_t num_phys_disks;
1318: u_int8_t data_scrub_rate;
1319: u_int8_t resync_rate;
1320: u_int8_t inactive_status;
1321: #define MPI_CFG_RAID_VOL_0_INACTIVE_UNKNOWN (0x00)
1322: #define MPI_CFG_RAID_VOL_0_INACTIVE_STALE_META (0x01)
1323: #define MPI_CFG_RAID_VOL_0_INACTIVE_FOREIGN_VOL (0x02)
1324: #define MPI_CFG_RAID_VOL_0_INACTIVE_NO_RESOURCES (0x03)
1325: #define MPI_CFG_RAID_VOL_0_INACTIVE_CLONED_VOL (0x04)
1326: #define MPI_CFG_RAID_VOL_0_INACTIVE_INSUF_META (0x05)
1327:
1328: /* followed by a list of mpi_cfg_raid_vol_pg0_physdisk structs */
1329: } __packed;
1330:
1331: struct mpi_cfg_raid_vol_pg0_physdisk {
1332: u_int16_t reserved;
1333: u_int8_t phys_disk_map;
1334: u_int8_t phys_disk_num;
1335: } __packed;
1336:
1337: struct mpi_cfg_raid_vol_pg1 {
1338: struct mpi_cfg_hdr config_header;
1339:
1340: u_int8_t volume_id;
1341: u_int8_t volume_bus;
1342: u_int8_t volume_ioc;
1343: u_int8_t reserved1;
1344:
1345: u_int8_t guid[24];
1346:
1347: u_int8_t name[32];
1348:
1349: u_int64_t wwid;
1350:
1351: u_int32_t reserved2;
1352:
1353: u_int32_t reserved3;
1354: } __packed;
1355:
1356: struct mpi_cfg_raid_physdisk_pg0 {
1357: struct mpi_cfg_hdr config_header;
1358:
1359: u_int8_t phys_disk_id;
1360: u_int8_t phys_disk_bus;
1361: u_int8_t phys_disk_ioc;
1362: u_int8_t phys_disk_num;
1363:
1364: u_int8_t enc_id;
1365: u_int8_t enc_bus;
1366: u_int8_t hot_spare_pool;
1367: u_int8_t enc_type;
1368: #define MPI_CFG_RAID_PHYDISK_0_ENCTYPE_NONE (0x0)
1369: #define MPI_CFG_RAID_PHYDISK_0_ENCTYPE_SAFTE (0x1)
1370: #define MPI_CFG_RAID_PHYDISK_0_ENCTYPE_SES (0x2)
1371:
1372: u_int32_t reserved1;
1373:
1374: u_int8_t ext_disk_id[8];
1375:
1376: u_int8_t disk_id[16];
1377:
1378: u_int8_t vendor_id[8];
1379:
1380: u_int8_t product_id[16];
1381:
1382: u_int8_t product_rev[4];
1383:
1384: u_int8_t info[32];
1385:
1386: u_int8_t phys_disk_status;
1387: #define MPI_CFG_RAID_PHYDISK_0_STATUS_OUTOFSYNC (1<<0)
1388: #define MPI_CFG_RAID_PHYDISK_0_STATUS_QUIESCED (1<<1)
1389: u_int8_t phys_disk_state;
1390: #define MPI_CFG_RAID_PHYDISK_0_STATE_ONLINE (0x00)
1391: #define MPI_CFG_RAID_PHYDISK_0_STATE_MISSING (0x01)
1392: #define MPI_CFG_RAID_PHYDISK_0_STATE_INCOMPAT (0x02)
1393: #define MPI_CFG_RAID_PHYDISK_0_STATE_FAILED (0x03)
1394: #define MPI_CFG_RAID_PHYDISK_0_STATE_INIT (0x04)
1395: #define MPI_CFG_RAID_PHYDISK_0_STATE_OFFLINE (0x05)
1396: #define MPI_CFG_RAID_PHYDISK_0_STATE_HOSTFAIL (0x06)
1397: #define MPI_CFG_RAID_PHYDISK_0_STATE_OTHER (0xff)
1398: u_int16_t reserved2;
1399:
1400: u_int32_t max_lba;
1401:
1402: u_int8_t error_cdb_byte;
1403: u_int8_t error_sense_key;
1404: u_int16_t reserved3;
1405:
1406: u_int16_t error_count;
1407: u_int8_t error_asc;
1408: u_int8_t error_ascq;
1409:
1410: u_int16_t smart_count;
1411: u_int8_t smart_asc;
1412: u_int8_t smart_ascq;
1413: } __packed;
1414:
1415: struct mpi_cfg_raid_physdisk_pg1 {
1416: struct mpi_cfg_hdr config_header;
1417:
1418: u_int8_t num_phys_disk_paths;
1419: u_int8_t phys_disk_num;
1420: u_int16_t reserved1;
1421:
1422: u_int32_t reserved2;
1423:
1424: /* followed by mpi_cfg_raid_physdisk_path structs */
1425: } __packed;
1426:
1427: struct mpi_cfg_raid_physdisk_path {
1428: u_int8_t phys_disk_id;
1429: u_int8_t phys_disk_bus;
1430: u_int16_t reserved1;
1431:
1432: u_int64_t wwwid;
1433:
1434: u_int64_t owner_wwid;
1435:
1436: u_int8_t ownder_id;
1437: u_int8_t reserved2;
1438: u_int16_t flags;
1439: #define MPI_CFG_RAID_PHYDISK_PATH_INVALID (1<<0)
1440: #define MPI_CFG_RAID_PHYDISK_PATH_BROKEN (1<<1)
1441: } __packed;
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