Annotation of sys/dev/ic/midwayvar.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: midwayvar.h,v 1.12 2003/10/21 18:58:49 jmc Exp $ */
2:
3: /*
4: *
5: * Copyright (c) 1996 Charles D. Cranor and Washington University.
6: * All rights reserved.
7: *
8: * Redistribution and use in source and binary forms, with or without
9: * modification, are permitted provided that the following conditions
10: * are met:
11: * 1. Redistributions of source code must retain the above copyright
12: * notice, this list of conditions and the following disclaimer.
13: * 2. Redistributions in binary form must reproduce the above copyright
14: * notice, this list of conditions and the following disclaimer in the
15: * documentation and/or other materials provided with the distribution.
16: * 3. All advertising materials mentioning features or use of this software
17: * must display the following acknowledgement:
18: * This product includes software developed by Charles D. Cranor and
19: * Washington University.
20: * 4. The name of the author may not be used to endorse or promote products
21: * derived from this software without specific prior written permission.
22: *
23: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33: */
34:
35: /*
36: * m i d w a y v a r . h
37: *
38: * we define the en_softc here so that bus specific modules can allocate
39: * it as the first item in their softc. note that BSD-required
40: * "struct device" is in the mid_softc!
41: *
42: * author: Chuck Cranor <chuck@ccrc.wustl.edu>
43: */
44:
45: /*
46: * params needed to determine softc size
47: */
48:
49: #ifndef EN_NTX
50: #define EN_NTX 8 /* number of tx bufs to use */
51: #endif
52: #ifndef EN_TXSZ
53: #define EN_TXSZ 32 /* transmit buf size in KB */
54: #endif
55: #ifndef EN_RXSZ
56: #define EN_RXSZ 32 /* recv buf size in KB */
57: #endif
58: #define EN_MAXNRX ((2048-(EN_NTX*EN_TXSZ))/EN_RXSZ)
59: /* largest possible NRX (depends on RAM size) */
60:
61:
62: #if defined(__NetBSD__) || defined(__OpenBSD__) || defined(__bsdi__)
63: #define EN_INTR_TYPE int
64: #define EN_INTR_RET(X) return(X)
65: #if defined(__NetBSD__) || defined(__OpenBSD__)
66: #define EN_IOCTL_CMDT u_long
67: #elif defined(__bsdi__)
68: #define EN_IOCTL_CMDT int
69: #endif
70:
71: #elif defined(__FreeBSD__)
72:
73: #define EN_INTR_TYPE void
74: #define EN_INTR_RET(X) return
75: #define EN_IOCTL_CMDT int
76:
77: struct device {
78: char dv_xname[IFNAMSIZ];
79: };
80:
81: #define DV_IFNET 1
82:
83: struct cfdriver {
84: int zero;
85: char *name;
86: int one;
87: int cd_ndevs;
88: void *cd_devs[NEN];
89: };
90:
91: #endif
92:
93:
94: /*
95: * softc
96: */
97:
98: struct en_softc {
99: /* bsd glue */
100: struct device sc_dev; /* system device */
101: struct ifnet enif; /* network ifnet handle */
102:
103: /* bus glue */
104: bus_space_tag_t en_memt; /* for EN_READ/EN_WRITE */
105: bus_space_handle_t en_base; /* base of en card */
106: bus_size_t en_obmemsz; /* size of en card (bytes) */
107: void (*en_busreset)(void *); /* bus specific reset function */
108:
109: /* serv list */
110: u_int32_t hwslistp; /* hw pointer to service list (byte offset) */
111: u_int16_t swslist[MID_SL_N]; /* software service list (see en_service()) */
112: u_int16_t swsl_head, /* ends of swslist (index into swslist) */
113: swsl_tail;
114: u_int32_t swsl_size; /* # of items in swsl */
115:
116:
117: /* xmit dma */
118: u_int32_t dtq[MID_DTQ_N]; /* sw copy of dma q (see ENIDQ macros) */
119: u_int32_t dtq_free; /* # of dtq's free */
120: u_int32_t dtq_us; /* software copy of our pointer (byte offset) */
121: u_int32_t dtq_chip; /* chip's pointer (byte offset) */
122: u_int32_t need_dtqs; /* true if we ran out of DTQs */
123:
124: /* recv dma */
125: u_int32_t drq[MID_DRQ_N]; /* sw copy of dma q (see ENIDQ macros) */
126: u_int32_t drq_free; /* # of drq's free */
127: u_int32_t drq_us; /* software copy of our pointer (byte offset) */
128: u_int32_t drq_chip; /* chip's pointer (byte offset) */
129: u_int32_t need_drqs; /* true if we ran out of DRQs */
130:
131: /* xmit buf ctrl. (per channel) */
132: struct {
133: u_int32_t mbsize; /* # mbuf bytes we are using (max=TXHIWAT) */
134: u_int32_t bfree; /* # free bytes in buffer (not dma or xmit) */
135: u_int32_t start, stop; /* ends of buffer area (byte offset) */
136: u_int32_t cur; /* next free area (byte offset) */
137: u_int32_t nref; /* # of VCs using this channel */
138: struct ifqueue indma; /* mbufs being dma'd now */
139: struct ifqueue q; /* mbufs waiting for dma now */
140: } txslot[MID_NTX_CH];
141:
142: /* xmit vc ctrl. (per vc) */
143: u_int8_t txspeed[MID_N_VC]; /* speed of tx on a VC */
144: u_int8_t txvc2slot[MID_N_VC]; /* map VC to slot */
145:
146: /* recv vc ctrl. (per vc). maps VC number to recv slot */
147: u_int16_t rxvc2slot[MID_N_VC];
148: int en_nrx; /* # of active rx slots */
149:
150: /* recv buf ctrl. (per recv slot) */
151: struct {
152: void *rxhand; /* recv. handle if doing direct delivery */
153: u_int32_t mode; /* saved copy of mode info */
154: u_int32_t start, stop; /* ends of my buffer area */
155: u_int32_t cur; /* where I am at */
156: u_int16_t atm_vci; /* backpointer to VCI */
157: u_int8_t atm_flags; /* copy of atm_flags from atm_ph */
158: u_int8_t oth_flags; /* other flags */
159: u_int32_t raw_threshold; /* for raw mode */
160: struct ifqueue indma; /* mbufs being dma'd now */
161: struct ifqueue q; /* mbufs waiting for dma now */
162: } rxslot[EN_MAXNRX]; /* recv info */
163:
164: /* stats */
165: u_int32_t vtrash; /* sw copy of counter */
166: u_int32_t otrash; /* sw copy of counter */
167: u_int32_t ttrash; /* # of RBD's with T bit set */
168: u_int32_t mfix; /* # of times we had to call mfix */
169: u_int32_t mfixfail; /* # of times mfix failed */
170: u_int32_t headbyte; /* # of times we used BYTE DMA at front */
171: u_int32_t tailbyte; /* # of times we used BYTE DMA at end */
172: u_int32_t tailflush; /* # of times we had to FLUSH out DMA bytes */
173: u_int32_t txmbovr; /* # of times we dropped due to mbsize */
174: u_int32_t dmaovr; /* tx dma overflow count */
175: u_int32_t txoutspace; /* out of space in xmit buffer */
176: u_int32_t txdtqout; /* out of DTQs */
177: u_int32_t launch; /* total # of launches */
178: u_int32_t lheader; /* # of launches without OB header */
179: u_int32_t ltail; /* # of launches without OB tail */
180: u_int32_t hwpull; /* # of pulls off hardware service list */
181: u_int32_t swadd; /* # of pushes on sw service list */
182: u_int32_t rxqnotus; /* # of times we pull from rx q, but fail */
183: u_int32_t rxqus; /* # of good pulls from rx q */
184: u_int32_t rxoutboth; /* # of times out of mbufs and DRQs */
185: u_int32_t rxdrqout; /* # of times out of DRQs */
186: u_int32_t rxmbufout; /* # of time out of mbufs */
187:
188: /* random stuff */
189: u_int32_t ipl; /* sbus interrupt lvl (1 on pci?) */
190: u_int8_t bestburstcode; /* code of best burst we can use */
191: u_int8_t bestburstlen; /* length of best burst (bytes) */
192: u_int8_t bestburstshift; /* (x >> shift) == (x / bestburstlen) */
193: u_int8_t bestburstmask; /* bits to check if not multiple of burst */
194: u_int8_t alburst; /* align dma bursts? */
195: u_int8_t is_adaptec; /* adaptec version of midway? */
196: };
197:
198: /*
199: * exported functions
200: */
201:
202: void en_attach(struct en_softc *);
203: EN_INTR_TYPE en_intr(void *);
204: void en_reset(struct en_softc *);
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