Annotation of sys/dev/ic/midwayreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: midwayreg.h,v 1.9 2003/10/21 18:58:49 jmc Exp $ */
2:
3: /*
4: * m i d w a y r e g . h
5: *
6: * this file contains the description of the ENI ATM midway chip
7: * data structures. see midway.c for more details.
8: *
9: */
10:
11: #if defined(__sparc__) || defined(__FreeBSD__)
12: /* XXX: gross. netbsd/sparc doesn't have machine/bus.h yet. */
13: typedef void * bus_space_tag_t;
14: typedef u_int32_t pci_chipset_tag_t;
15: typedef caddr_t bus_space_handle_t;
16: typedef u_int32_t bus_size_t;
17: typedef caddr_t bus_addr_t;
18:
19: #define bus_space_read_4(t, h, o) ((void) t, \
20: (*(volatile u_int32_t *)((h) + (o))))
21: #define bus_space_write_4(t, h, o, v) \
22: ((void) t, ((void)(*(volatile u_int32_t *)((h) + (o)) = (v))))
23:
24: #if defined(__sparc__)
25: #define vtophys(x) ((u_int32_t)(x)) /* sun4c dvma */
26: #endif
27:
28: #endif
29:
30:
31: #define MID_SZTOB(X) ((X) * 256 * 4) /* size to bytes */
32: #define MID_BTOSZ(X) ((X) / 256 / 4) /* bytes to "size" */
33:
34: #define MID_N_VC 1024 /* # of VCs we can use */
35: #define MID_NTX_CH 8 /* 8 transmit channels (shared) */
36: #define MID_ATMDATASZ 48 /* need data in 48 byte blocks */
37:
38: /*
39: * card data structures, top down
40: *
41: * in order to have a portable driver, the netbsd guys will not let us
42: * use structs. we have a bus_space_handle_t which is the en_base address.
43: * everything else is an offset from that base. all card data must be
44: * accessed with bus_space_read_4()/bus_space_write_4():
45: *
46: * rv = bus_space_read_4(sc->en_memt, sc->en_base, BYTE_OFFSET);
47: * bus_space_write_4(sc->en_memt, sc->en_base, BYTE_OFFSET, VALUE);
48: *
49: * en_card: the whole card (prom + phy + midway + obmem)
50: * obmem contains: vci tab + dma queues (rx & tx) + service list + bufs
51: */
52:
53: /* byte offsets from en_base of various items */
54: #define MID_PHYOFF 0x030000 /* PHY offset */
55: #define MID_MIDOFF 0x040000 /* midway regs offset */
56: #define MID_RAMOFF 0x200000 /* RAM offset */
57: #define MID_DRQOFF 0x204000 /* DRQ offset */
58: #define MID_DRQEND MID_DTQOFF /* DRQ end */
59: #define MID_DTQOFF 0x205000 /* DTQ offset */
60: #define MID_DTQEND MID_SLOFF /* DTQ end */
61: #define MID_SLOFF 0x206000 /* service list */
62: #define MID_SLEND MID_BUFOFF /* service list end */
63: #define MID_BUFOFF 0x207000 /* buffer area */
64: #define MID_PROBEOFF 0x21fffc /* start probe here */
65: #define MID_PROBSIZE 0x020000 /* 128 KB */
66: #define MID_MAXOFF 0x3ffffc /* max offset */
67:
68: /*
69: * prom & phy: not defined here
70: */
71:
72: /*
73: * midway regs (byte offsets from en_base)
74: */
75:
76: #define MID_RESID 0x40000 /* write=reset reg, read=ID reg */
77:
78: #define MID_VER(X) (((X) & 0xf0000000) >> 28) /* midway version # */
79: #define MID_MID(X) (((X) & 0x700) >> 8) /* motherboard ID */
80: #define MID_IS_SABRE(X) ((X) & 0x80) /* sabre controller? */
81: #define MID_IS_SUNI(X) ((X) & 0x40) /* SUNI? vs utopia */
82: #define MID_IS_UPIPE(X) ((X) & 0x20) /* utopia pipeline? */
83: #define MID_DID(X) ((X) & 0x1f) /* daughterboard ID */
84:
85: #define MID_INTACK 0x40004 /* interrupt ACK */
86: #define MID_INTSTAT 0x40008 /* interrupt status */
87: #define MID_INTENA 0x4000c /* interrupt enable */
88:
89: #define MID_TXCHAN(N) (1 << ((N) + 9)) /* ack/status/enable xmit channel bit*/
90: #define MID_INT_TX 0x1fe00 /* mask for any xmit interrupt */
91: #define MID_INT_DMA_OVR 0x00100 /* DMA overflow interrupt */
92: #define MID_INT_IDENT 0x00080 /* ident match error interrupt */
93: #define MID_INT_LERR 0x00040 /* LERR interrupt (sbus?) */
94: #define MID_INT_DMA_ERR 0x00020 /* DMA error interrupt */
95: #define MID_INT_DMA_RX 0x00010 /* DMA recv interrupt */
96: #define MID_INT_DMA_TX 0x00008 /* DMA xmit interrupt */
97: #define MID_INT_SERVICE 0x00004 /* service list interrupt */
98: #define MID_INT_SUNI 0x00002 /* SUNI interrupt */
99: #define MID_INT_STATS 0x00001 /* stats overflow interrupt */
100:
101: #define MID_INT_ANY 0x1ffff /* any interrupt? */
102:
103: #define MID_INTBITS "\20\21T7\20T6\17T5\16T4\15T3\14T2\13T1\12T0\11DMAOVR\10ID\7LERR\6DMAERR\5RXDMA\4TXDMA\3SERV\2SUNI\1STAT"
104:
105: #define MID_MAST_CSR 0x40010 /* master CSR */
106:
107: #define MID_IPL(X) (((X) & 0x1c0) >> 6) /* IPL */
108: #define MID_SETIPL(I) ((I) << 6)
109: #define MID_MCSR_TXLOCK 0x20 /* lock on xmit overflow mode */
110: /* NOTE: next 5 bits: write 1 means enable, write 0 means no change */
111: #define MID_MCSR_ENDMA 0x10 /* DMA enable */
112: #define MID_MCSR_ENTX 0x08 /* TX enable */
113: #define MID_MCSR_ENRX 0x04 /* RX enable */
114: #define MID_MCSR_W1MS 0x02 /* wait 1 msec */
115: #define MID_MCSR_W500US 0x01 /* wait 500 usec */
116:
117: #define MID_MCSRBITS "\20\6LCK\5DMAON\4TXON\3RXON\2W1MS\1W500US"
118:
119: #define MID_STAT 0x40014 /* stat register, clear on read */
120:
121: #define MID_VTRASH(X) (((X) >> 16) & 0xffff)
122: /* # cells trashed due to VCI's mode */
123: #define MID_OTRASH(X) ((X) & 0xffff) /* # cells trashed due to overflow */
124:
125: #define MID_SERV_WRITE 0x40018 /* 10 bit service write pointer (r/o) */
126: #define MID_DMA_ADDR 0x4001c /* VA of DMA (r/o) */
127:
128: /* DMA queue pointers (bits 0 to 8) */
129: #define MID_DMA_WRRX 0x40020 /* write ptr. for DMA recv queue */
130: /* (for adaptor -> host xfers) */
131: #define MID_DMA_RDRX 0x40024 /* read ptr for DMA recv queue (r/o) */
132: /* (i.e. current adaptor->host xfer) */
133: #define MID_DMA_WRTX 0x40028 /* write ptr for DMA xmit queue */
134: /* (for host -> adaptor xfers) */
135: #define MID_DMA_RDTX 0x4002c /* read ptr for DMA xmit queue (r/o) */
136: /* (i.e. current host->adaptor xfer) */
137:
138: /* xmit channel regs (1 per channel, MID_NTX_CH max channels) */
139:
140: #define MIDX_PLACE(N) (0x40040+((N)*0x10)) /* xmit place */
141:
142: #define MIDX_MKPLACE(SZ,LOC) ( ((SZ) << 11) | (LOC) )
143: #define MIDX_LOC(X) ((X) & 0x7ff) /* location in obmem */
144: #define MIDX_SZ(X) ((X) >> 11) /* (size of block / 256) in int32_t's*/
145: #define MIDX_BASE(X) \
146: (((MIDX_LOC(X) << MIDV_LOCTOPSHFT) * sizeof(u_int32_t)) + MID_RAMOFF)
147:
148: /* the following two regs are word offsets in the block */
149: #define MIDX_READPTR(N) (0x40044+((N)*0x10)) /* xmit read pointer (r/o) */
150: #define MIDX_DESCSTART(N) (0x40048+((N)*0x10)) /* seg currently in DMA (r/o) */
151:
152:
153: /*
154: * obmem items
155: */
156:
157: /*
158: * vci table in obmem (offset from MID_VCTOFF)
159: */
160:
161: #define MID_VC(N) (MID_RAMOFF+((N)*0x10))
162:
163: #define MIDV_TRASH 0x00000000 /* ignore VC */
164: #define MIDV_AAL5 0x80000000 /* do AAL5 on it */
165: #define MIDV_NOAAL 0x40000000 /* do per-cell stuff on it */
166: #define MIDV_MASK 0xc0000000 /* mode mask */
167: #define MIDV_SETMODE(VC,M) (((VC) & ~(MIDV_MASK)) | (M)) /* new mode */
168: #define MIDV_PTI 0x20000000 /* save PTI cells? */
169: #define MIDV_LOCTOPSHFT 8 /* shift to get top 11 bits of 19 */
170: #define MIDV_LOCSHIFT 18
171: #define MIDV_LOCMASK 0x7ff
172: #define MIDV_LOC(X) (((X) >> MIDV_LOCSHIFT) & MIDV_LOCMASK)
173: /* 11 most sig bits of addr */
174: #define MIDV_SZSHIFT 15
175: #define MIDV_SZ(X) (((X) >> MIDV_SZSHIFT) & 7)
176: /* size encoded the usual way */
177: #define MIDV_INSERVICE 0x1 /* in service list */
178:
179: #define MID_DST_RP(N) (MID_VC(N)|0x4)
180:
181: #define MIDV_DSTART_SHIFT 16 /* shift */
182: #define MIDV_DSTART(X) (((X) >> MIDV_DSTART_SHIFT) & 0x7fff)
183: #define MIDV_READP_MASK 0x7fff /* valid bits, (shift = 0) */
184:
185: #define MID_WP_ST_CNT(N) (MID_VC(N)|0x8) /* write pointer/state/count */
186:
187: #define MIDV_WRITEP_MASK 0x7fff0000 /* mask for write ptr. */
188: #define MIDV_WRITEP_SHIFT 16
189: #define MIDV_ST_IDLE 0x0000
190: #define MIDV_ST_TRASH 0xc000
191: #define MIDV_ST_REASS 0x4000
192: #define MIDV_CCOUNT 0x7ff /* cell count */
193:
194: #define MID_CRC(N) (MID_VC(N)|0xc) /* CRC */
195:
196: /*
197: * dma recv q.
198: */
199:
200: #define MID_DMA_END (1 << 5) /* for both tx and rx */
201: #define MID_DMA_CNT(X) (((X) >> 16) & 0xffff)
202: #define MID_DMA_TXCHAN(X) (((X) >> 6) & 0x7)
203: #define MID_DMA_RXVCI(X) (((X) >> 6) & 0x3ff)
204: #define MID_DMA_TYPE(X) ((X) & 0xf)
205:
206: #define MID_DRQ_N 512 /* # of descriptors */
207: #define MID_DRQ_A2REG(N) (((N) - MID_DRQOFF) >> 3)
208: /* convert byte offset to reg value */
209: #define MID_DRQ_REG2A(N) (((N) << 3) + MID_DRQOFF) /* and back */
210:
211: /* note: format of word 1 of RXQ is different between ENI and ADP cards */
212: #define MID_MK_RXQ_ENI(CNT,VC,END,TYPE) \
213: ( ((CNT) << 16)|((VC) << 6)|(END)|(TYPE) )
214:
215: #define MID_MK_RXQ_ADP(CNT,VC,END,JK) \
216: ( ((CNT) << 12)|((VC) << 2)|((END) >> 4)|(((JK) != 0) ? 1 : 0))
217: /*
218: * dma xmit q.
219: */
220:
221: #define MID_DTQ_N 512 /* # of descriptors */
222: #define MID_DTQ_A2REG(N) (((N) - MID_DTQOFF) >> 3)
223: /* convert byte offset to reg value */
224: #define MID_DTQ_REG2A(N) (((N) << 3) + MID_DTQOFF) /* and back */
225:
226:
227: /* note: format of word 1 of TXQ is different between ENI and ADP cards */
228: #define MID_MK_TXQ_ENI(CNT,CHN,END,TYPE) \
229: ( ((CNT) << 16)|((CHN) << 6)|(END)|(TYPE) )
230:
231: #define MID_MK_TXQ_ADP(CNT,CHN,END,JK) \
232: ( ((CNT) << 12)|((CHN) << 2)|((END) >> 4)|(((JK) != 0) ? 1 : 0) )
233:
234: /*
235: * dma types
236: */
237:
238: #define MIDDMA_JK 0x3 /* just kidding */
239: #define MIDDMA_BYTE 0x1 /* byte */
240: #define MIDDMA_2BYTE 0x2 /* 2 bytes */
241: #define MIDDMA_WORD 0x0 /* word */
242: #define MIDDMA_2WORD 0x7 /* 2 words */
243: #define MIDDMA_4WORD 0x4 /* 4 words */
244: #define MIDDMA_8WORD 0x5 /* 8 words */
245: #define MIDDMA_16WORD 0x6 /* 16 words!!! */
246: #define MIDDMA_2WMAYBE 0xf /* 2 words, maybe */
247: #define MIDDMA_4WMAYBE 0xc /* 4 words, maybe */
248: #define MIDDMA_8WMAYBE 0xd /* 8 words, maybe */
249: #define MIDDMA_16WMAYBE 0xe /* 16 words, maybe */
250:
251: #define MIDDMA_MAYBE 0xc /* mask to detect WMAYBE dma code */
252: #define MIDDMA_MAXBURST (16 * sizeof(u_int32_t)) /* largest burst */
253:
254: /*
255: * service list
256: */
257:
258: #define MID_SL_N 1024 /* max # entries on slist */
259: #define MID_SL_A2REG(N) (((N) - MID_SLOFF) >> 2)
260: /* convert byte offset to reg value */
261: #define MID_SL_REG2A(N) (((N) << 2) + MID_SLOFF) /* and back */
262:
263: /*
264: * data in the buffer area of obmem
265: */
266:
267: /*
268: * recv buffer desc. (1 u_int32_t at start of buffer)
269: */
270:
271: #define MID_RBD_SIZE 4 /* RBD size */
272: #define MID_CHDR_SIZE 4 /* on aal0, cell header size */
273: #define MID_RBD_ID(X) ((X) & 0xfe000000) /* get ID */
274: #define MID_RBD_STDID 0x36000000 /* standard ID */
275: #define MID_RBD_CLP 0x01000000 /* CLP: cell loss priority */
276: #define MID_RBD_CE 0x00010000 /* CE: congestion experienced */
277: #define MID_RBD_T 0x00001000 /* T: trashed due to overflow */
278: #define MID_RBD_CRCERR 0x00000800 /* CRC error */
279: #define MID_RBD_CNT(X) ((X) & 0x7ff) /* cell count */
280:
281: /*
282: * xmit buffer desc. (2 u_int32_t's at start of buffer)
283: * (note we treat the PR & RATE as a single u_int8_t)
284: */
285:
286: #define MID_TBD_SIZE 8
287: #define MID_TBD_MK1(AAL,PR_RATE,CNT) \
288: (MID_TBD_STDID|(AAL)|((PR_RATE) << 19)|(CNT))
289: #define MID_TBD_STDID 0xb0000000 /* standard ID */
290: #define MID_TBD_AAL5 0x08000000 /* AAL 5 */
291: #define MID_TBD_NOAAL5 0x00000000 /* not AAL 5 */
292:
293: #define MID_TBD_MK2(VCI,PTI,CLP) \
294: (((VCI) << 4)|((PTI) << 1)|(CLP))
295:
296: /*
297: * aal5 pdu tail, last 2 words of last cell of AAL5 frame
298: * (word 2 is CRC .. handled by hw)
299: */
300:
301: #define MID_PDU_SIZE 8
302: #define MID_PDU_MK1(UU,CPI,LEN) \
303: (((UU) << 24)|((CPI) << 16)|(LEN))
304: #define MID_PDU_LEN(X) ((X) & 0xffff)
CVSweb
![[BACK]](/icons/back.gif){kind=icon}
Return to midwayreg.h CVS log ![[TXT]](/icons/text.gif){kind=icon}
![[DIR]](/icons/dir.gif){kind=icon}
Up to [local] / sys / dev / ic