Annotation of sys/dev/ic/lsi64854reg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: lsi64854reg.h,v 1.3 2006/05/29 20:40:03 miod Exp $ */
2: /* $NetBSD: lsi64854reg.h,v 1.5 2001/03/29 02:58:39 petrov Exp $ */
3:
4: /*-
5: * Copyright (c) 1998 The NetBSD Foundation, Inc.
6: * All rights reserved.
7: *
8: * This code is derived from software contributed to The NetBSD Foundation
9: * by Paul Kranenburg.
10: *
11: * Redistribution and use in source and binary forms, with or without
12: * modification, are permitted provided that the following conditions
13: * are met:
14: * 1. Redistributions of source code must retain the above copyright
15: * notice, this list of conditions and the following disclaimer.
16: * 2. Redistributions in binary form must reproduce the above copyright
17: * notice, this list of conditions and the following disclaimer in the
18: * documentation and/or other materials provided with the distribution.
19: * 3. All advertising materials mentioning features or use of this software
20: * must display the following acknowledgement:
21: * This product includes software developed by the NetBSD
22: * Foundation, Inc. and its contributors.
23: * 4. Neither the name of The NetBSD Foundation nor the names of its
24: * contributors may be used to endorse or promote products derived
25: * from this software without specific prior written permission.
26: *
27: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37: * POSSIBILITY OF SUCH DAMAGE.
38: */
39:
40: /*
41: * LSI 64854 DMA engine. Contains three independent channels
42: * designed to interface with (a) a NCR539X SCSI controller,
43: * (b) a AM7990 Ethernet controller, (c) Parallel port hardware..
44: */
45:
46: /*
47: * Register offsets to bus handle.
48: */
49: #define L64854_REG_CSR 0 /* Control bits */
50: #define L64854_REG_ADDR 4 /* DMA Address */
51: #define L64854_REG_CNT 8 /* DMA count */
52: #define L64854_REG_CNT_MASK 0x00ffffff /* only 24 bits */
53: #define L64854_REG_ENBAR 12 /* ENET Base register */
54: #define L64854_REG_TEST 12 /* SCSI Test register */
55: #define L64854_REG_HCR 16 /* PP Hardware Configuration */
56: #define L64854_REG_OCR 18 /* PP Operation Configuration */
57: #define L64854_REG_DR 20 /* PP Data register */
58: #define L64854_REG_TCR 21 /* PP Transfer Control */
59: #define L64854_REG_OR 22 /* PP Output register */
60: #define L64854_REG_IR 23 /* PP Input register */
61: #define L64854_REG_ICR 24 /* PP Interrupt Control */
62:
63:
64: /*
65: * Control bits common to all three channels.
66: */
67: #define L64854_INT_PEND 0x00000001 /* Interrupt pending */
68: #define L64854_ERR_PEND 0x00000002 /* Error pending */
69: #define L64854_DRAINING 0x0000000c /* FIFO draining */
70: #define L64854_INT_EN 0x00000010 /* Interrupt enable */
71: #define L64854_INVALIDATE 0x00000020 /* Invalidate FIFO */
72: #define L64854_SLAVE_ERR 0x00000040 /* Slave access size error */
73: #define L64854_RESET 0x00000080 /* Reset device */
74: #define L64854_WRITE 0x00000100 /* 1: xfer to memory */
75: #define L64854_EN_DMA 0x00000200 /* enable DMA transfers */
76:
77: #define L64854_BURST_SIZE 0x000c0000 /* Read/write burst size */
78: #define L64854_BURST_0 0x00080000 /* no bursts (SCSI-only) */
79: #define L64854_BURST_16 0x00000000 /* 16-byte bursts */
80: #define L64854_BURST_32 0x00040000 /* 32-byte bursts */
81: #define L64854_BURST_64 0x000c0000 /* 64-byte bursts (fas) */
82:
83: #define L64854_RST_FAS366 0x08000000 /* FAS366 hardware reset */
84:
85: #define L64854_DEVID 0xf0000000 /* device ID bits */
86:
87: /*
88: * SCSI DMA control bits.
89: */
90: #define D_INT_PEND L64854_INT_PEND /* interrupt pending */
91: #define D_ERR_PEND L64854_ERR_PEND /* error pending */
92: #define D_DRAINING L64854_DRAINING /* fifo draining */
93: #define D_INT_EN L64854_INT_EN /* interrupt enable */
94: #define D_INVALIDATE L64854_INVALIDATE/* invalidate fifo */
95: #define D_SLAVE_ERR L64854_SLAVE_ERR/* slave access size error */
96: #define D_RESET L64854_RESET /* reset scsi */
97: #define D_WRITE L64854_WRITE /* 1 = dev -> mem */
98: #define D_EN_DMA L64854_EN_DMA /* enable DMA requests */
99: #define D_EN_CNT 0x00002000 /* enable byte counter */
100: #define D_TC 0x00004000 /* terminal count */
101: #define D_WIDE_EN 0x00008000 /* enable wide mode SBUS DMA (fas) */
102: #define D_DSBL_CSR_DRN 0x00010000 /* disable fifo drain on csr */
103: #define D_DSBL_SCSI_DRN 0x00020000 /* disable fifo drain on reg */
104:
105: #define D_DIAG 0x00100000 /* disable fifo drain on addr */
106: #define D_TWO_CYCLE 0x00200000 /* 2 clocks per transfer */
107: #define D_FASTER 0x00400000 /* 3 clocks per transfer */
108: #define D_TCI_DIS 0x00800000 /* disable intr on D_TC */
109: #define D_EN_NEXT 0x01000000 /* enable auto next address */
110: #define D_DMA_ON 0x02000000 /* enable dma from scsi XXX */
111: #define D_DSBL_PARITY_CHK \
112: 0x02000000 /* disable checking for parity on bus (default 1:fas) */
113: #define D_A_LOADED 0x04000000 /* address loaded */
114: #define D_NA_LOADED 0x08000000 /* next address loaded */
115: #define D_HW_RESET_FAS366 \
116: 0x08000000 /* hardware reset FAS366 (fas) */
117: #define D_DEV_ID L64854_DEVID /* device ID */
118: #define DMAREV_0 0x00000000 /* Sunray DMA */
119: #define DMAREV_ESC 0x40000000 /* DMA ESC array */
120: #define DMAREV_1 0x80000000 /* 'DMA' */
121: #define DMAREV_PLUS 0x90000000 /* 'DMA+' */
122: #define DMAREV_2 0xa0000000 /* 'DMA2' */
123: #define DMAREV_HME 0xb0000000 /* 'HME' */
124:
125: /*
126: * revisions 0,1 and ESC have different bits.
127: */
128: #define D_ESC_DRAIN 0x00000040 /* rev0,1,esc: drain fifo */
129: #define D_ESC_R_PEND 0x00000400 /* rev0,1: request pending */
130: #define D_ESC_BURST 0x00000800 /* DMA ESC: 16 byte bursts */
131: #define D_ESC_AUTODRAIN 0x00040000 /* DMA ESC: Auto-drain */
132:
133: #define DDMACSR_BITS "\020" \
134: "\01INT\02ERR\03DR1\04DR2\05IEN" \
135: "\07SLVERR\010RST\011WRITE\012ENDMA" \
136: "\016ENCNT\017TC\021DSBL_CSR_DRN" \
137: "\022DSBL_SCSI_DRN\026TWOCYCLE" \
138: "\027FASTER\030TCIDIS\031ENNXT\032DMAON" \
139: "\033ALOADED\034NALOADED"
140:
141:
142: /*
143: * ENET DMA control bits.
144: */
145: #define E_INT_PEND L64854_INT_PEND /* interrupt pending */
146: #define E_ERR_PEND L64854_ERR_PEND /* error pending */
147: #define E_DRAINING L64854_DRAINING /* fifo draining */
148: #define E_INT_EN L64854_INT_EN /* interrupt enable */
149: #define E_INVALIDATE L64854_INVALIDATE/* invalidate fifo */
150: #define E_SLAVE_ERR L64854_SLAVE_ERR/* slave access size error */
151: #define E_RESET L64854_RESET /* reset ENET */
152: #define E_reserved1 0x00000300 /* */
153: #define E_DRAIN 0x00000400 /* force Ecache drain */
154: #define E_DSBL_WR_DRN 0x00000800 /* disable Ecache drain on .. */
155: #define E_DSBL_RD_DRN 0x00001000 /* disable Ecache drain on .. */
156: #define E_reserved2 0x00006000 /* */
157: #define E_ILACC 0x00008000 /* ... */
158: #define E_DSBL_BUF_WR 0x00010000 /* no buffering of slave writes */
159: #define E_DSBL_WR_INVAL 0x00020000 /* no Ecache invalidate on slave writes */
160:
161: #define E_reserved3 0x00100000 /* */
162: #define E_LOOP_TEST 0x00200000 /* loopback mode */
163: #define E_TP_AUI 0x00400000 /* 1 for TP, 0 for AUI */
164: #define E_reserved4 0x0c800000 /* */
165: #define E_DEV_ID L64854_DEVID /* ID bits */
166:
167: #define EDMACSR_BITS "\020" \
168: "\01INT\02ERR\05IEN" \
169: "\07SLVERR\010RST\011WRITE\013DRAIN" \
170: "\014DSBL_WR_DRN\015DSBL_RD_DRN\020ILACC" \
171: "\021DSBL_BUF_WR\022DSBL_WR_INVAL" \
172: "\026LOOPTEST\027TP"
173:
174: /*
175: * PP DMA control bits.
176: */
177: #define P_INT_PEND L64854_INT_PEND /* interrupt pending */
178: #define P_ERR_PEND L64854_ERR_PEND /* error pending */
179: #define P_DRAINING L64854_DRAINING /* fifo draining */
180: #define P_INT_EN L64854_INT_EN /* interrupt enable */
181: #define P_INVALIDATE L64854_INVALIDATE/* invalidate fifo */
182: #define P_SLAVE_ERR L64854_SLAVE_ERR/* slave access size error */
183: #define P_RESET L64854_RESET /* reset PP */
184: #define P_WRITE L64854_WRITE /* 1: xfer to memory */
185: #define P_EN_DMA L64854_EN_DMA /* enable DMA transfers */
186: #define P_reserved1 0x00001c00 /* */
187: #define P_EN_CNT 0x00002000 /* enable counter */
188: #define P_TC 0x00004000 /* terminal count */
189: #define P_reserved2 0x00038000 /* */
190:
191: #define P_DIAG 0x00100000 /* ... */
192: #define P_reserved3 0x00600000 /* */
193: #define P_TCI_DIS 0x00800000 /* no interrupt on terminal count */
194: #define P_EN_NEXT 0x01000000 /* enable DMA chaining */
195: #define P_DMA_ON 0x02000000 /* DMA xfers enabled */
196: #define P_A_LOADED 0x04000000 /* addr and byte count valid */
197: #define P_NA_LOADED 0x08000000 /* next addr & count valid but not used */
198: #define P_DEV_ID L64854_DEVID /* ID bits */
199:
200: #define PDMACSR_BITS "\020" \
201: "\01INT\02ERR\05IEN" \
202: "\07SLVERR\010RST\011WRITE\012ENDMA" \
203: "\016ENCNT\017TC\025DIAG\030TCIDIS" \
204: "\031ENNXT\032DMAON\033ALOADED\034NALOADED"
CVSweb
![[BACK]](/icons/back.gif){kind=icon}
Return to lsi64854reg.h CVS log ![[TXT]](/icons/text.gif){kind=icon}
![[DIR]](/icons/dir.gif){kind=icon}
Up to [local] / sys / dev / ic