Annotation of sys/dev/ic/lemacreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: lemacreg.h,v 1.2 2003/10/21 18:58:49 jmc Exp $ */
2: /* $NetBSD: lemacreg.h,v 1.2 2001/06/13 10:46:03 wiz Exp $ */
3:
4: /*
5: * Copyright (c) 1994, 1995, 1997 Matt Thomas <matt@3am-software.com>
6: * All rights reserved.
7: *
8: * Redistribution and use in source and binary forms, with or without
9: * modification, are permitted provided that the following conditions
10: * are met:
11: * 1. Redistributions of source code must retain the above copyright
12: * notice, this list of conditions and the following disclaimer.
13: * 2. The name of the author may not be used to endorse or promote products
14: * derived from this software without specific prior written permission
15: *
16: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26: */
27: #ifndef _LEMAC_H_
28: #define _LEMAC_H_
29:
30: #define LEMAC_IOBASE_LOW 0x200
31: #define LEMAC_IOBASE_HIGH 0x400
32:
33: /*
34: * This is list of registers used on a DEC EtherWORKS III card.
35: * Each board occupies a 32 byte register space. This can be
36: * in either EISA or ISA space. Currently we only support ISA
37: * space.
38: */
39:
40: #define LEMAC_REG_CS 0x00 /* Control and Status */
41: #define LEMAC_REG_CTL 0x01 /* Control */
42: #define LEMAC_REG_IC 0x02 /* Interrupt Control */
43: #define LEMAC_REG_TS 0x03 /* Transmit Status */
44: #define LEMAC_REG_RSVD1 0x04 /* Reserved (not used) */
45: #define LEMAC_REG_RSVD2 0x05 /* Reserved (not used) */
46: #define LEMAC_REG_FMQ 0x06 /* Free Memory Queue */
47: #define LEMAC_REG_FMC 0x07 /* Free Memory Queue Count */
48: #define LEMAC_REG_RQ 0x08 /* Receive Queue */
49: #define LEMAC_REG_RQC 0x09 /* Receive Queue Count */
50: #define LEMAC_REG_TQ 0x0A /* Transmit Queue */
51: #define LEMAC_REG_TQC 0x0B /* Transmit Queue Count */
52: #define LEMAC_REG_TDQ 0x0C /* Transmit Done Queue */
53: #define LEMAC_REG_TDC 0x0D /* Transmit Done Queue Count */
54: #define LEMAC_REG_PI1 0x0E /* Page Index #1 */
55: #define LEMAC_REG_PI2 0x0F /* Page Index #2 */
56: #define LEMAC_REG_DAT 0x10 /* Data */
57: #define LEMAC_REG_IOP 0x11 /* I/O Page */
58: #define LEMAC_REG_IOB 0x12 /* I/O Base */
59: #define LEMAC_REG_MPN 0x13 /* Memory Page */
60: #define LEMAC_REG_MBR 0x14 /* Memory Base */
61: #define LEMAC_REG_APD 0x15 /* Address PROM */
62: #define LEMAC_REG_EE1 0x16 /* EEPROM Data #1 */
63: #define LEMAC_REG_EE2 0x17 /* EEPROM Data #2 */
64: #define LEMAC_REG_PA0 0x18 /* Physical Address (Byte 0) */
65: #define LEMAC_REG_PA1 0x19 /* Physical Address (Byte 1) */
66: #define LEMAC_REG_PA2 0x1A /* Physical Address (Byte 2) */
67: #define LEMAC_REG_PA3 0x1B /* Physical Address (Byte 3) */
68: #define LEMAC_REG_PA4 0x1C /* Physical Address (Byte 4) */
69: #define LEMAC_REG_PA5 0x1D /* Physical Address (Byte 5) */
70: #define LEMAC_REG_CNF 0x1E /* Configuration Management */
71: #define LEMAC_IOSIZE 0x20 /* LEMAC uses 32 bytes of IOSPACE */
72:
73:
74: #define LEMAC_REG_EID0 0x80 /* EISA Identification 0 */
75: #define LEMAC_REG_EID1 0x81 /* EISA Identification 1 */
76: #define LEMAC_REG_EID2 0x82 /* EISA Identification 2 */
77: #define LEMAC_REG_EID3 0x83 /* EISA Identification 3 */
78: #define LEMAC_REG_EIC 0x84 /* EISA Control */
79:
80: /* Control Page (Page 0) Definitions */
81:
82: #define LEMAC_MCTBL_BITS 9
83: #define LEMAC_MCTBL_OFF 512
84: #define LEMAC_MCTBL_SIZE (1 << (LEMAC_MCTBL_BITS - 3))
85: #define LEMAC_CRC32_POLY 0xEDB88320UL /* CRC-32 Poly -- Little Endian) */
86:
87: /* EEPROM Definitions */
88:
89: #define LEMAC_EEP_CKSUM 0 /* The valid checksum is 0 */
90: #define LEMAC_EEP_SIZE 32 /* EEPROM is 32 bytes */
91: #define LEMAC_EEP_DELAY 2000 /* 2ms = 2000us */
92: #define LEMAC_EEP_PRDNM 8 /* Product Name Offset */
93: #define LEMAC_EEP_PRDNMSZ 8 /* Product Name Size */
94: #define LEMAC_EEP_SWFLAGS 16 /* Software Options Offset */
95: #define LEMAC_EEP_SETUP 23 /* Setup Options Offset */
96:
97: #define LEMAC_EEP_SW_SQE 0x10 /* Enable TX_SQE on Transmits */
98: #define LEMAC_EEP_SW_LAB 0x08 /* Enable TX_LAB on Transmits */
99: #define LEMAC_EEP_ST_DRAM 0x02 /* Enable extra DRAM */
100:
101: #define LEMAC_ADP_ROMSZ 32 /* Size of Address PROM */
102:
103: /* Receive Status Definitions */
104:
105: #define LEMAC_RX_PLL 0x01 /* Phase Lock Lost */
106: #define LEMAC_RX_CRC 0x02 /* CRC Error */
107: #define LEMAC_RX_DBE 0x04 /* Dribble Bit Error */
108: #define LEMAC_RX_MCM 0x08 /* Multicast Match */
109: #define LEMAC_RX_IAM 0x10 /* Individual Address Match */
110: #define LEMAC_RX_OK 0x80 /* No Errors */
111:
112: /* Transmit Status Definitions (not valid if TXD == 0) */
113:
114: #define LEMAC_TS_RTRYMSK 0x0F /* Retries of last TX PDU */
115: #define LEMAC_TS_ECL 0x10 /* Excessive collision of ... */
116: #define LEMAC_TS_LCL 0x20 /* Late collision of ... */
117: #define LEMAC_TS_ID 0x40 /* Initially Deferred ... */
118: #define LEMAC_TS_NCL 0x08 /* No carrier loopback ... */
119:
120: /* Transmit Control Definitions */
121:
122: #define LEMAC_TX_ISA 0x01 /* Insert Source Address (no) */
123: #define LEMAC_TX_IFC 0x02 /* Insert Frame Check (yes) */
124: #define LEMAC_TX_PAD 0x04 /* Zero PAD to minimum length (yes) */
125: #define LEMAC_TX_LAB 0x08 /* Less Agressive Backoff (no) */
126: #define LEMAC_TX_QMD 0x10 /* Q-Mode (yes) */
127: #define LEMAC_TX_STP 0x20 /* Stop on Error (no) */
128: #define LEMAC_TX_SQE 0x40 /* SQE Enable (yes) */
129:
130: #define LEMAC_TX_FLAGS (LEMAC_TX_IFC|LEMAC_TX_PAD|LEMAC_TX_QMD|\
131: LEMAC_TX_SQE)
132: #define LEMAC_TX_HDRSZ 4 /* Size of TX header */
133:
134: /* Transmit Done Queue Status Definitions */
135:
136: #define LEMAC_TDQ_COL 0x03 /* Collision Mask */
137: #define LEMAC_TDQ_NOCOL 0x00 /* No Collisions */
138: #define LEMAC_TDQ_ONECOL 0x01 /* One Collision */
139: #define LEMAC_TDQ_MULCOL 0x02 /* Multiple Collisions */
140: #define LEMAC_TDQ_EXCCOL 0x03 /* Excessive Collisions */
141: #define LEMAC_TDQ_ID 0x04 /* Initially Deferred */
142: #define LEMAC_TDQ_LCL 0x08 /* Late Collision (will TX_STP) */
143: #define LEMAC_TDQ_NCL 0x10 /* No carrier loopback */
144: #define LEMAC_TDQ_SQE 0x20 /* SQE error */
145:
146: /* Control / Status Definitions */
147:
148: #define LEMAC_CS_RXD 0x01 /* Receiver Disabled */
149: #define LEMAC_CS_TXD 0x02 /* Transmitter Disabled */
150: #define LEMAC_CS_RNE 0x04 /* Receive Queue Not Empty */
151: #define LEMAC_CS_TNE 0x08 /* Transmit Done Queue Not Empty */
152: #define LEMAC_CS_MBZ4 0x10 /* MBZ */
153: #define LEMAC_CS_MCE 0x20 /* Multicast Enable */
154: #define LEMAC_CS_PME 0x40 /* Promiscuous Mode Enable */
155: #define LEMAC_CS_RA 0x80 /* Runt Accept */
156:
157: /* Control Definitions */
158:
159: #define LEMAC_CTL_LED 0x02 /* LED state (inverted) */
160: #define LEMAC_CTL_PSL 0x40 /* Port Select (1=AUI, 0=UTP) */
161: #define LEMAC_CTL_APD 0x80 /* Auto Port Disable */
162:
163: /* Interrupt Control Definitions */
164:
165: #define LEMAC_IC_RXD 0x01 /* Enable RXD Interrupt */
166: #define LEMAC_IC_TXD 0x02 /* Enable TXD Interrupt */
167: #define LEMAC_IC_RNE 0x04 /* Enable RNE Interrupt */
168: #define LEMAC_IC_TNE 0x08 /* Enable TNE Interrupt */
169: #define LEMAC_IC_ALL 0x0F /* Enable RXD,TXD,RNE,TNE */
170: #define LEMAC_IC_IRQMSK 0x60 /* Interrupt Select */
171: #define LEMAC_IC_IRQ5 0x00 /* Select IRQ 5 */
172: #define LEMAC_IC_IRQ10 0x20 /* Select IRQ 10 */
173: #define LEMAC_IC_IRQ11 0x40 /* Select IRQ 11 */
174: #define LEMAC_IC_IRQ15 0x60 /* Select IRQ 15 */
175: #define LEMAC_IC_IE 0x80 /* Interrupt Enable */
176:
177: /* I/O Page Definitions */
178:
179: #define LEMAC_IOP_EEINIT 0xC0 /* Perform a board init/reset */
180: #define LEMAC_IOP_EEREAD 0xE0 /* Start a read from EEPROM */
181:
182: /* Configuration / Management Definitions */
183:
184: #define LEMAC_CNF_DRAM 0x02 /* Extra on-board DRAM is available */
185: #define LEMAC_CNF_NOLINK 0x20 /* UTP port is UP */
186:
187: #endif /* _LEMAC_H_ */
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