Annotation of sys/dev/ic/lancereg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: lancereg.h,v 1.1 2005/07/28 01:31:22 brad Exp $ */
2: /* $NetBSD: lancereg.h,v 1.11 2003/11/02 11:07:45 wiz Exp $ */
3:
4: /*-
5: * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc.
6: * All rights reserved.
7: *
8: * This code is derived from software contributed to The NetBSD Foundation
9: * by Charles M. Hannum and Jason R. Thorpe.
10: *
11: * Redistribution and use in source and binary forms, with or without
12: * modification, are permitted provided that the following conditions
13: * are met:
14: * 1. Redistributions of source code must retain the above copyright
15: * notice, this list of conditions and the following disclaimer.
16: * 2. Redistributions in binary form must reproduce the above copyright
17: * notice, this list of conditions and the following disclaimer in the
18: * documentation and/or other materials provided with the distribution.
19: * 3. All advertising materials mentioning features or use of this software
20: * must display the following acknowledgement:
21: * This product includes software developed by the NetBSD
22: * Foundation, Inc. and its contributors.
23: * 4. Neither the name of The NetBSD Foundation nor the names of its
24: * contributors may be used to endorse or promote products derived
25: * from this software without specific prior written permission.
26: *
27: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37: * POSSIBILITY OF SUCH DAMAGE.
38: */
39:
40: /*-
41: * Copyright (c) 1992, 1993
42: * The Regents of the University of California. All rights reserved.
43: *
44: * This code is derived from software contributed to Berkeley by
45: * Ralph Campbell and Rick Macklem.
46: *
47: * Redistribution and use in source and binary forms, with or without
48: * modification, are permitted provided that the following conditions
49: * are met:
50: * 1. Redistributions of source code must retain the above copyright
51: * notice, this list of conditions and the following disclaimer.
52: * 2. Redistributions in binary form must reproduce the above copyright
53: * notice, this list of conditions and the following disclaimer in the
54: * documentation and/or other materials provided with the distribution.
55: * 3. Neither the name of the University nor the names of its contributors
56: * may be used to endorse or promote products derived from this software
57: * without specific prior written permission.
58: *
59: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
60: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
61: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
62: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
63: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
64: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
65: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
66: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
67: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
68: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
69: * SUCH DAMAGE.
70: *
71: * @(#)if_lereg.h 8.1 (Berkeley) 6/10/93
72: */
73:
74: /*
75: * Register description for the following Advanced Micro Devices
76: * Ethernet chips:
77: *
78: * - Am7990 Local Area Network Controller for Ethernet (LANCE)
79: * (and its descendent Am79c90 C-LANCE).
80: *
81: * - Am79c900 Integrated Local Area Communications Controller (ILACC)
82: *
83: * - Am79c960 PCnet-ISA Single-Chip Ethernet Controller for ISA
84: *
85: * - Am79c961 PCnet-ISA+ Jumperless Single-Chip Ethernet Controller
86: * for ISA
87: *
88: * - Am79c961A PCnet-ISA II Jumperless Full-Duplex Single-Chip
89: * Ethernet Controller for ISA
90: *
91: * - Am79c965A PCnet-32 Single-Chip 32-bit Ethernet Controller
92: * (for VESA and 486 local busses)
93: *
94: * - Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI
95: * Local Bus
96: *
97: * - Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller
98: * for PCI Local Bus
99: *
100: * - Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps
101: * Ethernet Controller for PCI Local Bus
102: *
103: * - Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller
104: * with OnNow Support
105: *
106: * - Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI
107: * Ethernet Controller with Integrated PHY
108: *
109: * - Am79c978 PCnet-Home Single-Chip 1/10 Mbps PCI Home
110: * Networking Controller.
111: *
112: * Initialization block, transmit descriptor, and receive descriptor
113: * formats are described in two separate files:
114: *
115: * 16-bit software model (LANCE) am7990reg.h
116: *
117: * 32-bit software model (ILACC) am79900reg.h
118: *
119: * Note that the vast majority of the registers described in this file
120: * belong to follow-on chips to the original LANCE. Only CSR0-CSR3 are
121: * valid on the LANCE.
122: */
123:
124: #define LEBLEN 1536 /* ETHERMTU + header + CRC */
125: #define LEMINSIZE 60 /* should be 64 if mode DTCR is set */
126:
127: #define LE_INITADDR(sc) (sc->sc_initaddr)
128: #define LE_RMDADDR(sc, bix) (sc->sc_rmdaddr + sizeof(struct lermd) * (bix))
129: #define LE_TMDADDR(sc, bix) (sc->sc_tmdaddr + sizeof(struct letmd) * (bix))
130: #define LE_RBUFADDR(sc, bix) (sc->sc_rbufaddr[bix])
131: #define LE_TBUFADDR(sc, bix) (sc->sc_tbufaddr[bix])
132:
133: /*
134: * The byte count fields in descriptors are in two's complement.
135: * This macro does the conversion for us on unsigned numbers.
136: */
137: #define LE_BCNT(x) (~(x) + 1)
138:
139: /*
140: * Control and Status Register addresses
141: */
142: #define LE_CSR0 0x0000 /* Control and status register */
143: #define LE_CSR1 0x0001 /* low address of init block */
144: #define LE_CSR2 0x0002 /* high address of init block */
145: #define LE_CSR3 0x0003 /* Bus master and control */
146: #define LE_CSR4 0x0004 /* Test and features control */
147: #define LE_CSR5 0x0005 /* Extended control and Interrupt 1 */
148: #define LE_CSR6 0x0006 /* Rx/Tx Descriptor table length */
149: #define LE_CSR7 0x0007 /* Extended control and interrupt 2 */
150: #define LE_CSR8 0x0008 /* Logical Address Filter 0 */
151: #define LE_CSR9 0x0009 /* Logical Address Filter 1 */
152: #define LE_CSR10 0x000a /* Logical Address Filter 2 */
153: #define LE_CSR11 0x000b /* Logical Address Filter 3 */
154: #define LE_CSR12 0x000c /* Physical Address 0 */
155: #define LE_CSR13 0x000d /* Physical Address 1 */
156: #define LE_CSR14 0x000e /* Physical Address 2 */
157: #define LE_CSR15 0x000f /* Mode */
158: #define LE_CSR16 0x0010 /* Initialization Block addr lower */
159: #define LE_CSR17 0x0011 /* Initialization Block addr upper */
160: #define LE_CSR18 0x0012 /* Current Rx Buffer addr lower */
161: #define LE_CSR19 0x0013 /* Current Rx Buffer addr upper */
162: #define LE_CSR20 0x0014 /* Current Tx Buffer addr lower */
163: #define LE_CSR21 0x0015 /* Current Tx Buffer addr upper */
164: #define LE_CSR22 0x0016 /* Next Rx Buffer addr lower */
165: #define LE_CSR23 0x0017 /* Next Rx Buffer addr upper */
166: #define LE_CSR24 0x0018 /* Base addr of Rx ring lower */
167: #define LE_CSR25 0x0019 /* Base addr of Rx ring upper */
168: #define LE_CSR26 0x001a /* Next Rx Desc addr lower */
169: #define LE_CSR27 0x001b /* Next Rx Desc addr upper */
170: #define LE_CSR28 0x001c /* Current Rx Desc addr lower */
171: #define LE_CSR29 0x001d /* Current Rx Desc addr upper */
172: #define LE_CSR30 0x001e /* Base addr of Tx ring lower */
173: #define LE_CSR31 0x001f /* Base addr of Tx ring upper */
174: #define LE_CSR32 0x0020 /* Next Tx Desc addr lower */
175: #define LE_CSR33 0x0021 /* Next Tx Desc addr upper */
176: #define LE_CSR34 0x0022 /* Current Tx Desc addr lower */
177: #define LE_CSR35 0x0023 /* Current Tx Desc addr upper */
178: #define LE_CSR36 0x0024 /* Next Next Rx Desc addr lower */
179: #define LE_CSR37 0x0025 /* Next Next Rx Desc addr upper */
180: #define LE_CSR38 0x0026 /* Next Next Tx Desc addr lower */
181: #define LE_CSR39 0x0027 /* Next Next Tx Desc adddr upper */
182: #define LE_CSR40 0x0028 /* Current Rx Byte Count */
183: #define LE_CSR41 0x0029 /* Current Rx Status */
184: #define LE_CSR42 0x002a /* Current Tx Byte Count */
185: #define LE_CSR43 0x002b /* Current Tx Status */
186: #define LE_CSR44 0x002c /* Next Rx Byte Count */
187: #define LE_CSR45 0x002d /* Next Rx Status */
188: #define LE_CSR46 0x002e /* Tx Poll Time Counter */
189: #define LE_CSR47 0x002f /* Tx Polling Interval */
190: #define LE_CSR48 0x0030 /* Rx Poll Time Counter */
191: #define LE_CSR49 0x0031 /* Rx Polling Interval */
192: #define LE_CSR58 0x003a /* Software Style */
193: #define LE_CSR60 0x003c /* Previous Tx Desc addr lower */
194: #define LE_CSR61 0x003d /* Previous Tx Desc addr upper */
195: #define LE_CSR62 0x003e /* Previous Tx Byte Count */
196: #define LE_CSR63 0x003f /* Previous Tx Status */
197: #define LE_CSR64 0x0040 /* Next Tx Buffer addr lower */
198: #define LE_CSR65 0x0041 /* Next Tx Buffer addr upper */
199: #define LE_CSR66 0x0042 /* Next Tx Byte Count */
200: #define LE_CSR67 0x0043 /* Next Tx Status */
201: #define LE_CSR72 0x0048 /* Receive Ring Counter */
202: #define LE_CSR74 0x004a /* Transmit Ring Counter */
203: #define LE_CSR76 0x004c /* Receive Ring Length */
204: #define LE_CSR78 0x004e /* Transmit Ring Length */
205: #define LE_CSR80 0x0050 /* DMA Transfer Counter and FIFO
206: Threshold Control */
207: #define LE_CSR82 0x0052 /* Tx Desc addr Pointer lower */
208: #define LE_CSR84 0x0054 /* DMA addr register lower */
209: #define LE_CSR85 0x0055 /* DMA addr register upper */
210: #define LE_CSR86 0x0056 /* Buffer Byte Counter */
211: #define LE_CSR88 0x0058 /* Chip ID Register lower */
212: #define LE_CSR89 0x0059 /* Chip ID Register upper */
213: #define LE_CSR92 0x005c /* Ring Length Conversion */
214: #define LE_CSR100 0x0064 /* Bus Timeout */
215: #define LE_CSR112 0x0070 /* Missed Frame Count */
216: #define LE_CSR114 0x0072 /* Receive Collision Count */
217: #define LE_CSR116 0x0074 /* OnNow Power Mode Register */
218: #define LE_CSR122 0x007a /* Advanced Feature Control */
219: #define LE_CSR124 0x007c /* Test Register 1 */
220: #define LE_CSR125 0x007d /* MAC Enhanced Configuration Control */
221:
222: /*
223: * Bus Configuration Register addresses
224: */
225: #define LE_BCR0 0x0000 /* Master Mode Read Active */
226: #define LE_BCR1 0x0001 /* Master Mode Write Active */
227: #define LE_BCR2 0x0002 /* Misc. Configuration */
228: #define LE_BCR4 0x0004 /* LED0 Status */
229: #define LE_BCR5 0x0005 /* LED1 Status */
230: #define LE_BCR6 0x0006 /* LED2 Status */
231: #define LE_BCR7 0x0007 /* LED3 Status */
232: #define LE_BCR9 0x0009 /* Full-duplex Control */
233: #define LE_BCR16 0x0010 /* I/O Base Address lower */
234: #define LE_BCR17 0x0011 /* I/O Base Address upper */
235: #define LE_BCR18 0x0012 /* Burst and Bus Control Register */
236: #define LE_BCR19 0x0013 /* EEPROM Control and Status */
237: #define LE_BCR20 0x0014 /* Software Style */
238: #define LE_BCR22 0x0016 /* PCI Latency Register */
239: #define LE_BCR23 0x0017 /* PCI Subsystem Vendor ID */
240: #define LE_BCR24 0x0018 /* PCI Subsystem ID */
241: #define LE_BCR25 0x0019 /* SRAM Size Register */
242: #define LE_BCR26 0x001a /* SRAM Boundary Register */
243: #define LE_BCR27 0x001b /* SRAM Interface Control Register */
244: #define LE_BCR28 0x001c /* Exp. Bus Port Addr lower */
245: #define LE_BCR29 0x001d /* Exp. Bus Port Addr upper */
246: #define LE_BCR30 0x001e /* Exp. Bus Data Port */
247: #define LE_BCR31 0x001f /* Software Timer Register */
248: #define LE_BCR32 0x0020 /* PHY Control and Status Register */
249: #define LE_BCR33 0x0021 /* PHY Address Register */
250: #define LE_BCR34 0x0022 /* PHY Management Data Register */
251: #define LE_BCR35 0x0023 /* PCI Vendor ID Register */
252: #define LE_BCR36 0x0024 /* PCI Power Management Cap. Alias */
253: #define LE_BCR37 0x0025 /* PCI DATA0 Alias */
254: #define LE_BCR38 0x0026 /* PCI DATA1 Alias */
255: #define LE_BCR39 0x0027 /* PCI DATA2 Alias */
256: #define LE_BCR40 0x0028 /* PCI DATA3 Alias */
257: #define LE_BCR41 0x0029 /* PCI DATA4 Alias */
258: #define LE_BCR42 0x002a /* PCI DATA5 Alias */
259: #define LE_BCR43 0x002b /* PCI DATA6 Alias */
260: #define LE_BCR44 0x002c /* PCI DATA7 Alias */
261: #define LE_BCR45 0x002d /* OnNow Pattern Matching 1 */
262: #define LE_BCR46 0x002e /* OnNow Pattern Matching 2 */
263: #define LE_BCR47 0x002f /* OnNow Pattern Matching 3 */
264: #define LE_BCR48 0x0030 /* LED4 Status */
265: #define LE_BCR49 0x0031 /* PHY Select */
266:
267: /* Control and status register 0 (csr0) */
268: #define LE_C0_ERR 0x8000 /* error summary */
269: #define LE_C0_BABL 0x4000 /* transmitter timeout error */
270: #define LE_C0_CERR 0x2000 /* collision */
271: #define LE_C0_MISS 0x1000 /* missed a packet */
272: #define LE_C0_MERR 0x0800 /* memory error */
273: #define LE_C0_RINT 0x0400 /* receiver interrupt */
274: #define LE_C0_TINT 0x0200 /* transmitter interrupt */
275: #define LE_C0_IDON 0x0100 /* initialization done */
276: #define LE_C0_INTR 0x0080 /* interrupt condition */
277: #define LE_C0_INEA 0x0040 /* interrupt enable */
278: #define LE_C0_RXON 0x0020 /* receiver on */
279: #define LE_C0_TXON 0x0010 /* transmitter on */
280: #define LE_C0_TDMD 0x0008 /* transmit demand */
281: #define LE_C0_STOP 0x0004 /* disable all external activity */
282: #define LE_C0_STRT 0x0002 /* enable external activity */
283: #define LE_C0_INIT 0x0001 /* begin initialization */
284:
285: #define LE_C0_BITS \
286: "\20\20ERR\17BABL\16CERR\15MISS\14MERR\13RINT\
287: \12TINT\11IDON\10INTR\07INEA\06RXON\05TXON\04TDMD\03STOP\02STRT\01INIT"
288:
289: /* Control and status register 3 (csr3) */
290: #define LE_C3_BABLM 0x4000 /* babble mask */
291: #define LE_C3_MISSM 0x1000 /* missed frame mask */
292: #define LE_C3_MERRM 0x0800 /* memory error mask */
293: #define LE_C3_RINTM 0x0400 /* receive interrupt mask */
294: #define LE_C3_TINTM 0x0200 /* transmit interrupt mask */
295: #define LE_C3_IDONM 0x0100 /* initialization done mask */
296: #define LE_C3_DXSUFLO 0x0040 /* disable tx stop on underflow */
297: #define LE_C3_LAPPEN 0x0020 /* look ahead packet processing enbl */
298: #define LE_C3_DXMT2PD 0x0010 /* disable tx two part deferral */
299: #define LE_C3_EMBA 0x0008 /* enable modified backoff algorithm */
300: #define LE_C3_BSWP 0x0004 /* byte swap */
301: #define LE_C3_ACON 0x0002 /* ALE control, eh? */
302: #define LE_C3_BCON 0x0001 /* byte control */
303:
304: /* Control and status register 4 (csr4) */
305: #define LE_C4_EN124 0x8000 /* enable CSR124 */
306: #define LE_C4_DMAPLUS 0x4000 /* always set (PCnet-PCI) */
307: #define LE_C4_TIMER 0x2000 /* enable bus activity timer */
308: #define LE_C4_TXDPOLL 0x1000 /* disable transmit polling */
309: #define LE_C4_APAD_XMT 0x0800 /* auto pad transmit */
310: #define LE_C4_ASTRP_RCV 0x0400 /* auto strip receive */
311: #define LE_C4_MFCO 0x0200 /* missed frame counter overflow */
312: #define LE_C4_MFCOM 0x0100 /* missed frame coutner overflow mask */
313: #define LE_C4_UINTCMD 0x0080 /* user interrupt command */
314: #define LE_C4_UINT 0x0040 /* user interrupt */
315: #define LE_C4_RCVCCO 0x0020 /* receive collision counter overflow */
316: #define LE_C4_RCVCCOM 0x0010 /* receive collision counter overflow
317: mask */
318: #define LE_C4_TXSTRT 0x0008 /* transmit start status */
319: #define LE_C4_TXSTRTM 0x0004 /* transmit start mask */
320:
321: /* Control and status register 5 (csr5) */
322: #define LE_C5_TOKINTD 0x8000 /* transmit ok interrupt disable */
323: #define LE_C5_LTINTEN 0x4000 /* last transmit interrupt enable */
324: #define LE_C5_SINT 0x0800 /* system interrupt */
325: #define LE_C5_SINTE 0x0400 /* system interrupt enable */
326: #define LE_C5_EXDINT 0x0080 /* excessive deferral interrupt */
327: #define LE_C5_EXDINTE 0x0040 /* excessive deferral interrupt enbl */
328: #define LE_C5_MPPLBA 0x0020 /* magic packet physical logical
329: broadcast accept */
330: #define LE_C5_MPINT 0x0010 /* magic packet interrupt */
331: #define LE_C5_MPINTE 0x0008 /* magic packet interrupt enable */
332: #define LE_C5_MPEN 0x0004 /* magic packet enable */
333: #define LE_C5_MPMODE 0x0002 /* magic packet mode */
334: #define LE_C5_SPND 0x0001 /* suspend */
335:
336: /* Control and status register 6 (csr6) */
337: #define LE_C6_TLEN 0xf000 /* TLEN from init block */
338: #define LE_C6_RLEN 0x0f00 /* RLEN from init block */
339:
340: /* Control and status register 7 (csr7) */
341: #define LE_C7_FASTSPNDE 0x8000 /* fast suspend enable */
342: #define LE_C7_RDMD 0x2000 /* receive demand */
343: #define LE_C7_RDXPOLL 0x1000 /* receive disable polling */
344: #define LE_C7_STINT 0x0800 /* software timer interrupt */
345: #define LE_C7_STINTE 0x0400 /* software timer interrupt enable */
346: #define LE_C7_MREINT 0x0200 /* PHY management read error intr */
347: #define LE_C7_MREINTE 0x0100 /* PHY management read error intr
348: enable */
349: #define LE_C7_MAPINT 0x0080 /* PHY management auto-poll intr */
350: #define LE_C7_MAPINTE 0x0040 /* PHY management auto-poll intr
351: enable */
352: #define LE_C7_MCCINT 0x0020 /* PHY management command complete
353: interrupt */
354: #define LE_C7_MCCINTE 0x0010 /* PHY management command complete
355: interrupt enable */
356: #define LE_C7_MCCIINT 0x0008 /* PHY management command complete
357: internal interrupt */
358: #define LE_C7_MCCIINTE 0x0004 /* PHY management command complete
359: internal interrupt enable */
360: #define LE_C7_MIIPDTINT 0x0002 /* PHY management detect transition
361: interrupt */
362: #define LE_C7_MIIPDTINTE 0x0001 /* PHY management detect transition
363: interrupt enable */
364:
365: /* Control and status register 15 (csr15) */
366: #define LE_C15_PROM 0x8000 /* promiscuous mode */
367: #define LE_C15_DRCVBC 0x4000 /* disable Rx of broadcast */
368: #define LE_C15_DRCVPA 0x2000 /* disable Rx of physical address */
369: #define LE_C15_DLNKTST 0x1000 /* disable link status */
370: #define LE_C15_DAPC 0x0800 /* disable auto-polarity correction */
371: #define LE_C15_MENDECL 0x0400 /* MENDEC Loopback mode */
372: #define LE_C15_LRT 0x0200 /* low receive threshold (TMAU) */
373: #define LE_C15_TSEL 0x0200 /* transmit mode select (AUI) */
374: #define LE_C15_PORTSEL(x) ((x) << 7) /* port select */
375: #define LE_C15_INTL 0x0040 /* internal loopback */
376: #define LE_C15_DRTY 0x0020 /* disable retry */
377: #define LE_C15_FCOLL 0x0010 /* force collision */
378: #define LE_C15_DXMTFCS 0x0008 /* disable Tx FCS (ADD_FCS overrides) */
379: #define LE_C15_LOOP 0x0004 /* loopback enable */
380: #define LE_C15_DTX 0x0002 /* disable transmit */
381: #define LE_C15_DRX 0x0001 /* disable receiver */
382:
383: #define PORTSEL_AUI 0
384: #define PORTSEL_10T 1
385: #define PORTSEL_GPSI 2
386: #define PORTSEL_MII 3
387: #define PORTSEL_MASK 3
388:
389: /* control and status register 80 (csr80) */
390: #define LE_C80_RCVFW(x) ((x) << 12) /* Receive FIFO Watermark */
391: #define LE_C80_RCVFW_MAX 3
392: #define LE_C80_XMTSP(x) ((x) << 10) /* Transmit Start Point */
393: #define LE_C80_XMTSP_MAX 3
394: #define LE_C80_XMTFW(x) ((x) << 8) /* Transmit FIFO Watermark */
395: #define LE_C80_XMTFW_MAX 3
396: #define LE_C80_DMATC 0x00ff /* DMA transfer counter */
397:
398: /* control and status register 116 (csr116) */
399: #define LE_C116_PME_EN_OVR 0x0400 /* PME_EN overwrite */
400: #define LE_C116_LCDET 0x0200 /* link change detected */
401: #define LE_C116_LCMODE 0x0100 /* link change wakeup mode */
402: #define LE_C116_PMAT 0x0080 /* pattern matched */
403: #define LE_C116_EMPPLBA 0x0040 /* magic packet physical logical
404: broadcast accept */
405: #define LE_C116_MPMAT 0x0020 /* magic packet match */
406: #define LE_C116_MPPEN 0x0010 /* magic packet pin enable */
407: #define LE_C116_RST_POL 0x0001 /* PHY_RST pin polarity */
408:
409: /* control and status register 122 (csr122) */
410: #define LE_C122_RCVALGN 0x0001 /* receive packet align */
411:
412: /* control and status register 124 (csr124) */
413: #define LE_C124_RPA 0x0008 /* runt packet accept */
414:
415: /* control and status register 125 (csr125) */
416: #define LE_C125_IPG 0xff00 /* inter-packet gap */
417: #define LE_C125_IFS1 0x00ff /* inter-frame spacing part 1 */
418:
419: /* bus configuration register 0 (bcr0) */
420: #define LE_B0_MSRDA 0xffff /* reserved locations */
421:
422: /* bus configuration register 1 (bcr1) */
423: #define LE_B1_MSWRA 0xffff /* reserved locations */
424:
425: /* bus configuration register 2 (bcr2) */
426: #define LE_B2_PHYSSELEN 0x2000 /* enable writes to BCR18[4:3] */
427: #define LE_B2_LEDPE 0x1000 /* LED program enable */
428: #define LE_B2_APROMWE 0x0100 /* Address PROM Write Enable */
429: #define LE_B2_INTLEVEL 0x0080 /* 1 == edge triggered */
430: #define LE_B2_DXCVRCTL 0x0020 /* DXCVR control */
431: #define LE_B2_DXCVRPOL 0x0010 /* DXCVR polarity */
432: #define LE_B2_EADISEL 0x0008 /* EADI select */
433: #define LE_B2_AWAKE 0x0004 /* power saving mode select */
434: #define LE_B2_ASEL 0x0002 /* auto-select PORTSEL */
435: #define LE_B2_XMAUSEL 0x0001 /* reserved location */
436:
437: /* bus configuration register 4 (bcr4) */
438: /* bus configuration register 5 (bcr5) */
439: /* bus configuration register 6 (bcr6) */
440: /* bus configuration register 7 (bcr7) */
441: /* bus configuration register 48 (bcr48) */
442: #define LE_B4_LEDOUT 0x8000 /* LED output active */
443: #define LE_B4_LEDPOL 0x4000 /* LED polarity */
444: #define LE_B4_LEDDIS 0x2000 /* LED disable */
445: #define LE_B4_100E 0x1000 /* 100Mb/s enable */
446: #define LE_B4_MPSE 0x0200 /* magic packet status enable */
447: #define LE_B4_FDLSE 0x0100 /* full-duplex link status enable */
448: #define LE_B4_PSE 0x0080 /* pulse stretcher enable */
449: #define LE_B4_LNKSE 0x0040 /* link status enable */
450: #define LE_B4_RCVME 0x0020 /* receive match status enable */
451: #define LE_B4_XMTE 0x0010 /* transmit status enable */
452: #define LE_B4_POWER 0x0008 /* power enable */
453: #define LE_B4_RCVE 0x0004 /* receive status enable */
454: #define LE_B4_SPEED 0x0002 /* high speed enable */
455: #define LE_B4_COLE 0x0001 /* collision status enable */
456:
457: /* bus configuration register 9 (bcr9) */
458: #define LE_B9_FDRPAD 0x0004 /* full-duplex runt packet accept
459: disable */
460: #define LE_B9_AUIFD 0x0002 /* AUI full-duplex */
461: #define LE_B9_FDEN 0x0001 /* full-duplex enable */
462:
463: /* bus configuration register 18 (bcr18) */
464: #define LE_B18_ROMTMG 0xf000 /* expansion rom timing */
465: #define LE_B18_NOUFLO 0x0800 /* no underflow on transmit */
466: #define LE_B18_MEMCMD 0x0200 /* memory read multiple enable */
467: #define LE_B18_EXTREQ 0x0100 /* extended request */
468: #define LE_B18_DWIO 0x0080 /* double-word I/O */
469: #define LE_B18_BREADE 0x0040 /* burst read enable */
470: #define LE_B18_BWRITE 0x0020 /* burst write enable */
471: #define LE_B18_PHYSEL1 0x0010 /* PHYSEL 1 */
472: #define LE_B18_PHYSEL0 0x0008 /* PHYSEL 0 */
473: /* 00 ex ROM/Flash */
474: /* 01 EADI/MII snoop */
475: /* 10 reserved */
476: /* 11 reserved */
477: #define LE_B18_LINBC 0x0007 /* reserved locations */
478:
479: /* bus configuration register 19 (bcr19) */
480: #define LE_B19_PVALID 0x8000 /* EEPROM status valid */
481: #define LE_B19_PREAD 0x4000 /* EEPROM read command */
482: #define LE_B19_EEDET 0x2000 /* EEPROM detect */
483: #define LE_B19_EEN 0x0010 /* EEPROM port enable */
484: #define LE_B19_ECS 0x0004 /* EEPROM chip select */
485: #define LE_B19_ESK 0x0002 /* EEPROM serial clock */
486: #define LE_B19_EDI 0x0001 /* EEPROM data in */
487: #define LE_B19_EDO 0x0001 /* EEPROM data out */
488:
489: /* bus configuration register 20 (bcr20) */
490: #define LE_B20_APERREN 0x0400 /* Advanced parity error handling */
491: #define LE_B20_CSRPCNET 0x0200 /* PCnet-style CSRs (0 = ILACC) */
492: #define LE_B20_SSIZE32 0x0100 /* Software Size 32-bit */
493: #define LE_B20_SSTYLE 0x0007 /* Software Style */
494: #define LE_B20_SSTYLE_LANCE 0 /* LANCE/PCnet-ISA (16-bit) */
495: #define LE_B20_SSTYPE_ILACC 1 /* ILACC (32-bit) */
496: #define LE_B20_SSTYLE_PCNETPCI2 2 /* PCnet-PCI (32-bit) */
497: #define LE_B20_SSTYLE_PCNETPCI3 3 /* PCnet-PCI II (32-bit) */
498:
499: /* bus configuration register 25 (bcr25) */
500: #define LE_B25_SRAM_SIZE 0x00ff /* SRAM size */
501:
502: /* bus configuration register 26 (bcr26) */
503: #define LE_B26_SRAM_BND 0x00ff /* SRAM boundary */
504:
505: /* bus configuration register 27 (bcr27) */
506: #define LE_B27_PTRTST 0x8000 /* reserved for manuf. tests */
507: #define LE_B27_LOLATRX 0x4000 /* low latency receive */
508: #define LE_B27_EBCS 0x0038 /* expansion bus clock source */
509: /* 000 CLK pin */
510: /* 001 time base clock */
511: /* 010 EBCLK pin */
512: /* 011 reserved */
513: /* 1xx reserved */
514: #define LE_B27_CLK_FAC 0x0007 /* clock factor */
515: /* 000 1 */
516: /* 001 1/2 */
517: /* 010 reserved */
518: /* 011 1/4 */
519: /* 1xx reserved */
520:
521: /* bus configuration register 28 (bcr28) */
522: #define LE_B28_EADDRL 0xffff /* expansion port address lower */
523:
524: /* bus configuration register 29 (bcr29) */
525: #define LE_B29_FLASH 0x8000 /* flash access */
526: #define LE_B29_LAAINC 0x4000 /* lower address auto increment */
527: #define LE_B29_EPADDRU 0x0007 /* expansion port address upper */
528:
529: /* bus configuration register 30 (bcr30) */
530: #define LE_B30_EBDATA 0xffff /* expansion bus data port */
531:
532: /* bus configuration register 31 (bcr31) */
533: #define LE_B31_STVAL 0xffff /* software timer value */
534:
535: /* bus configuration register 32 (bcr32) */
536: #define LE_B32_ANTST 0x8000 /* reserved for manuf. tests */
537: #define LE_B32_MIIPD 0x4000 /* MII PHY Detect (manuf. tests) */
538: #define LE_B32_FMDC 0x3000 /* fast management data clock */
539: #define LE_B32_APEP 0x0800 /* auto-poll PHY */
540: #define LE_B32_APDW 0x0700 /* auto-poll dwell time */
541: #define LE_B32_DANAS 0x0080 /* disable autonegotiation */
542: #define LE_B32_XPHYRST 0x0040 /* PHY reset */
543: #define LE_B32_XPHYANE 0x0020 /* PHY autonegotiation enable */
544: #define LE_B32_XPHYFD 0x0010 /* PHY full-duplex */
545: #define LE_B32_XPHYSP 0x0008 /* PHY speed */
546: #define LE_B32_MIIILP 0x0002 /* MII internal loopback */
547:
548: /* bus configuration register 33 (bcr33) */
549: #define LE_B33_SHADOW 0x8000 /* shadow enable */
550: #define LE_B33_MII_SEL 0x4000 /* MII selected */
551: #define LE_B33_ACOMP 0x2000 /* internal PHY autonegotiation comp */
552: #define LE_B33_LINK 0x1000 /* link status */
553: #define LE_B33_FDX 0x0800 /* full-duplex */
554: #define LE_B33_SPEED 0x0400 /* 1 == high speed */
555: #define LE_B33_PHYAD 0x03e0 /* PHY address */
556: #define PHYAD_SHIFT 5
557: #define LE_B33_REGAD 0x001f /* register address */
558:
559: /* bus configuration register 34 (bcr34) */
560: #define LE_B34_MIIMD 0xffff /* MII data */
561:
562: /* bus configuration register 49 (bcr49) */
563: #define LE_B49_PCNET 0x8000 /* PCnet mode - Must Be One */
564: #define LE_B49_PHYSEL_D 0x0300 /* PHY_SEL_Default */
565: #define LE_B49_PHYSEL_L 0x0010 /* PHY_SEL_Lock */
566: #define LE_B49_PHYSEL 0x0003 /* PHYSEL */
567: /* 00 10baseT PHY */
568: /* 01 HomePNA PYY */
569: /* 10 external PHY */
570: /* 11 reserved */
571:
572: /* Initialization block (mode) */
573: #define LE_MODE_PROM 0x8000 /* promiscuous mode */
574: /* 0x7f80 reserved, must be zero */
575: /* 0x4000 - 0x0080 are not available on LANCE 7990 */
576: #define LE_MODE_DRCVBC 0x4000 /* disable receive brodcast */
577: #define LE_MODE_DRCVPA 0x2000 /* disable physical address detection */
578: #define LE_MODE_DLNKTST 0x1000 /* disable link status */
579: #define LE_MODE_DAPC 0x0800 /* disable automatic polarity correction */
580: #define LE_MODE_MENDECL 0x0400 /* MENDEC loopback mode */
581: #define LE_MODE_LRTTSEL 0x0200 /* lower receive threshold /
582: transmit mode selection */
583: #define LE_MODE_PSEL1 0x0100 /* port selection bit1 */
584: #define LE_MODE_PSEL0 0x0080 /* port selection bit0 */
585: #define LE_MODE_INTL 0x0040 /* internal loopback */
586: #define LE_MODE_DRTY 0x0020 /* disable retry */
587: #define LE_MODE_COLL 0x0010 /* force a collision */
588: #define LE_MODE_DTCR 0x0008 /* disable transmit CRC */
589: #define LE_MODE_LOOP 0x0004 /* loopback mode */
590: #define LE_MODE_DTX 0x0002 /* disable transmitter */
591: #define LE_MODE_DRX 0x0001 /* disable receiver */
592: #define LE_MODE_NORMAL 0 /* none of the above */
593:
594: /*
595: * Chip ID (CSR88 IDL, CSR89 IDU) values for various AMD PCnet parts.
596: */
597: #define CHIPID_MANFID(x) (((x) >> 1) & 0x3ff)
598: #define CHIPID_PARTID(x) (((x) >> 12) & 0xffff)
599: #define CHIPID_VER(x) (((x) >> 28) & 0x7)
600:
601: #define PARTID_Am79c960 0x0003
602: #define PARTID_Am79c961 0x2260
603: #define PARTID_Am79c961A 0x2261
604: #define PARTID_Am79c965 0x2430 /* yes, these... */
605: #define PARTID_Am79c970 0x2430 /* ...are the same */
606: #define PARTID_Am79c970A 0x2621
607: #define PARTID_Am79c971 0x2623
608: #define PARTID_Am79c972 0x2624
609: #define PARTID_Am79c973 0x2625
610: #define PARTID_Am79c978 0x2626
611: #define PARTID_Am79c975 0x2627
612: #define PARTID_Am79c976 0x2628
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