Annotation of sys/dev/ic/if_wireg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: if_wireg.h,v 1.38 2005/10/18 13:37:48 fgsch Exp $ */
2:
3: /*
4: * Copyright (c) 1997, 1998, 1999
5: * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: * 3. All advertising materials mentioning features or use of this software
16: * must display the following acknowledgement:
17: * This product includes software developed by Bill Paul.
18: * 4. Neither the name of the author nor the names of any co-contributors
19: * may be used to endorse or promote products derived from this software
20: * without specific prior written permission.
21: *
22: * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25: * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32: * THE POSSIBILITY OF SUCH DAMAGE.
33: *
34: * From: if_wireg.h,v 1.8.2.2 2001/08/25 00:48:25 nsayer Exp $
35: */
36:
37: #define WI_DELAY 5
38: #define WI_TIMEOUT (500000/WI_DELAY) /* 500ms */
39:
40: #define WI_PORT0 0
41: #define WI_PORT1 1
42: #define WI_PORT2 2
43: #define WI_PORT3 3
44: #define WI_PORT4 4
45: #define WI_PORT5 5
46:
47: /* Default port: 0 (only 0 exists on stations) */
48: #define WI_DEFAULT_PORT (WI_PORT0 << 8)
49:
50: /* Default TX rate: 2Mbps, auto fallback */
51: #define WI_DEFAULT_TX_RATE 3
52:
53: /* Default network name (wildcard) */
54: #define WI_DEFAULT_NETNAME ""
55:
56: #define WI_DEFAULT_AP_DENSITY 1
57:
58: #define WI_DEFAULT_RTS_THRESH 2347
59:
60: #define WI_DEFAULT_DATALEN 2304
61:
62: #define WI_DEFAULT_CREATE_IBSS 0
63:
64: #define WI_DEFAULT_PM_ENABLED 0
65:
66: #define WI_DEFAULT_MAX_SLEEP 100
67:
68: #define WI_DEFAULT_NODENAME "WaveLAN/IEEE node"
69:
70: #define WI_DEFAULT_IBSS "IBSS"
71:
72: #define WI_DEFAULT_CHAN 3
73:
74: #define WI_DEFAULT_ROAMING 1
75:
76: #define WI_DEFAULT_AUTHTYPE 1
77:
78: #define WI_DEFAULT_DIVERSITY 0
79:
80: /*
81: * register space access macros
82: */
83:
84: #if defined(__sparc64__)
85: #define WI_BIG_ENDIAN_POSSIBLE (sc->wi_flags & WI_FLAGS_BUS_PCMCIA)
86: #else
87: #define WI_BIG_ENDIAN_POSSIBLE 0
88: #endif
89:
90: #define CSR_WRITE_4(sc, reg, val) \
91: bus_space_write_4(sc->wi_btag, sc->wi_bhandle, \
92: (sc->sc_pci ? reg * 2: reg), \
93: WI_BIG_ENDIAN_POSSIBLE ? htole32(val) : (val))
94: #define CSR_WRITE_2(sc, reg, val) \
95: bus_space_write_2(sc->wi_btag, sc->wi_bhandle, \
96: (sc->sc_pci ? reg * 2: reg), \
97: WI_BIG_ENDIAN_POSSIBLE ? htole16(val) : (val))
98: #define CSR_WRITE_1(sc, reg, val) \
99: bus_space_write_1(sc->wi_btag, sc->wi_bhandle, \
100: (sc->sc_pci ? reg * 2: reg), val)
101:
102: #define CSR_READ_4(sc, reg) \
103: (WI_BIG_ENDIAN_POSSIBLE ? \
104: letoh32(bus_space_read_4(sc->wi_btag, sc->wi_bhandle, \
105: (sc->sc_pci ? reg * 2: reg))) : \
106: bus_space_read_4(sc->wi_btag, sc->wi_bhandle, \
107: (sc->sc_pci ? reg * 2: reg)))
108: #define CSR_READ_2(sc, reg) \
109: (WI_BIG_ENDIAN_POSSIBLE ? \
110: letoh16(bus_space_read_2(sc->wi_btag, sc->wi_bhandle, \
111: (sc->sc_pci ? reg * 2: reg))) : \
112: bus_space_read_2(sc->wi_btag, sc->wi_bhandle, \
113: (sc->sc_pci ? reg * 2: reg)))
114: #define CSR_READ_1(sc, reg) \
115: bus_space_read_1(sc->wi_btag, sc->wi_bhandle, \
116: (sc->sc_pci ? reg * 2: reg))
117:
118: #define CSR_READ_RAW_2(sc, ba, dst, sz) \
119: bus_space_read_raw_multi_2((sc)->wi_btag, \
120: (sc)->wi_bhandle, \
121: (sc->sc_pci? ba * 2: ba), (dst), (sz))
122: #define CSR_WRITE_RAW_2(sc, ba, dst, sz) \
123: bus_space_write_raw_multi_2((sc)->wi_btag, \
124: (sc)->wi_bhandle, \
125: (sc->sc_pci? ba * 2: ba), (dst), (sz))
126:
127: /*
128: * The WaveLAN/IEEE cards contain an 802.11 MAC controller which Lucent
129: * calls 'Hermes.' In typical fashion, getting documentation about this
130: * controller is about as easy as squeezing blood from a stone. Here
131: * is more or less what I know:
132: *
133: * - The Hermes controller is firmware driven, and the host interacts
134: * with the Hermes via a firmware interface, which can change.
135: *
136: * - The Hermes is described in a document called: "Hermes Firmware
137: * WaveLAN/IEEE Station Functions," document #010245, which of course
138: * Lucent will not release without an NDA.
139: *
140: * - Lucent has created a library called HCF (Hardware Control Functions)
141: * though which it wants developers to interact with the card. The HCF
142: * is needlessly complex, ill conceived and badly documented. Actually,
143: * the comments in the HCP code itself aren't bad, but the publicly
144: * available manual that comes with it is awful, probably due largely to
145: * the fact that it has been emasculated in order to hide information
146: * that Lucent wants to keep proprietary. The purpose of the HCF seems
147: * to be to insulate the driver programmer from the Hermes itself so that
148: * Lucent has an excuse not to release programming in for it.
149: *
150: * - Lucent only makes available documentation and code for 'HCF Light'
151: * which is a stripped down version of HCF with certain features not
152: * implemented, most notably support for 802.11 frames.
153: *
154: * - The HCF code which I have seen blows goats. Whoever decided to
155: * use a 132 column format should be shot.
156: *
157: * Rather than actually use the Lucent HCF library, I have stripped all
158: * the useful information from it and used it to create a driver in the
159: * usual BSD form. Note: I don't want to hear anybody whining about the
160: * fact that the Lucent code is GPLed and mine isn't. I did not actually
161: * put any of Lucent's code in this driver: I only used it as a reference
162: * to obtain information about the underlying hardware. The Hermes
163: * programming interface is not GPLed, so bite me.
164: */
165:
166: /*
167: * Size of Hermes & Prism2 I/O space.
168: */
169: #define WI_IOSIZ 0x40
170:
171: /*
172: * Hermes register definitions and what little I know about them.
173: */
174:
175: /* Hermes command/status registers. */
176: #define WI_COMMAND 0x00
177: #define WI_PARAM0 0x02
178: #define WI_PARAM1 0x04
179: #define WI_PARAM2 0x06
180: #define WI_STATUS 0x08
181: #define WI_RESP0 0x0A
182: #define WI_RESP1 0x0C
183: #define WI_RESP2 0x0E
184:
185: /* Command register values. */
186: #define WI_CMD_BUSY 0x8000 /* busy bit */
187: #define WI_CMD_INI 0x0000 /* initialize */
188: #define WI_CMD_ENABLE 0x0001 /* enable */
189: #define WI_CMD_DISABLE 0x0002 /* disable */
190: #define WI_CMD_DIAG 0x0003
191: #define WI_CMD_ALLOC_MEM 0x000A /* allocate NIC memory */
192: #define WI_CMD_TX 0x000B /* transmit */
193: #define WI_CMD_NOTIFY 0x0010
194: #define WI_CMD_INQUIRE 0x0011
195: #define WI_CMD_ACCESS 0x0021
196: #define WI_CMD_PROGRAM 0x0022
197: #define WI_CMD_READ_MIF 0x0030 /* prism2 */
198: #define WI_CMD_WRITE_MIF 0x0031 /* prism2 */
199:
200: #define WI_CMD_CODE_MASK 0x003F
201:
202: /*
203: * Reclaim qualifier bit, applicable to the
204: * TX and INQUIRE commands.
205: */
206: #define WI_RECLAIM 0x0100 /* reclaim NIC memory */
207:
208: /*
209: * ACCESS command qualifier bits.
210: */
211: #define WI_ACCESS_READ 0x0000
212: #define WI_ACCESS_WRITE 0x0100
213:
214: /*
215: * PROGRAM command qualifier bits.
216: */
217: #define WI_PROGRAM_DISABLE 0x0000
218: #define WI_PROGRAM_ENABLE_RAM 0x0100
219: #define WI_PROGRAM_ENABLE_NVRAM 0x0200
220: #define WI_PROGRAM_NVRAM 0x0300
221:
222: /* Status register values */
223: #define WI_STAT_CMD_CODE 0x003F
224: #define WI_STAT_DIAG_ERR 0x0100
225: #define WI_STAT_INQ_ERR 0x0500
226: #define WI_STAT_CMD_RESULT 0x7F00
227:
228: /* memory handle management registers */
229: #define WI_INFO_FID 0x10
230: #define WI_RX_FID 0x20
231: #define WI_ALLOC_FID 0x22
232: #define WI_TX_CMP_FID 0x24
233:
234: /*
235: * Buffer Access Path (BAP) registers.
236: * These are I/O channels. I believe you can use each one for
237: * any desired purpose independently of the other. In general
238: * though, we use BAP1 for reading and writing LTV records and
239: * reading received data frames, and BAP0 for writing transmit
240: * frames. This is a convention though, not a rule.
241: */
242: #define WI_SEL0 0x18
243: #define WI_SEL1 0x1A
244: #define WI_OFF0 0x1C
245: #define WI_OFF1 0x1E
246: #define WI_DATA0 0x36
247: #define WI_DATA1 0x38
248: #define WI_BAP0 WI_DATA0
249: #define WI_BAP1 WI_DATA1
250:
251: #define WI_OFF_BUSY 0x8000
252: #define WI_OFF_ERR 0x4000
253: #define WI_OFF_DATAOFF 0x0FFF
254:
255: /* Event registers */
256: #define WI_EVENT_STAT 0x30 /* Event status */
257: #define WI_INT_EN 0x32 /* Interrupt enable/disable */
258: #define WI_EVENT_ACK 0x34 /* Ack event */
259:
260: /* Events */
261: #define WI_EV_TICK 0x8000 /* aux timer tick */
262: #define WI_EV_RES 0x4000 /* controller h/w error (time out) */
263: #define WI_EV_INFO_DROP 0x2000 /* no RAM to build unsolicited frame */
264: #define WI_EV_NO_CARD 0x0800 /* card removed (hunh?) */
265: #define WI_EV_DUIF_RX 0x0400 /* wavelan management packet received */
266: #define WI_EV_INFO 0x0080 /* async info frame */
267: #define WI_EV_CMD 0x0010 /* command completed */
268: #define WI_EV_ALLOC 0x0008 /* async alloc/reclaim completed */
269: #define WI_EV_TX_EXC 0x0004 /* async xmit completed with failure */
270: #define WI_EV_TX 0x0002 /* async xmit completed successfully */
271: #define WI_EV_RX 0x0001 /* async rx completed */
272:
273: #define WI_INTRS \
274: (WI_EV_RX|WI_EV_TX|WI_EV_TX_EXC|WI_EV_ALLOC|WI_EV_INFO|WI_EV_INFO_DROP)
275:
276: /* Host software registers */
277: #define WI_SW0 0x28
278: #define WI_SW1 0x2A
279: #define WI_SW2 0x2C
280: #define WI_SW3 0x2E
281:
282: #define WI_CNTL 0x14
283:
284: #define WI_CNTL_AUX_ENA 0xC000
285: #define WI_CNTL_AUX_ENA_STAT 0xC000
286: #define WI_CNTL_AUX_DIS_STAT 0x0000
287: #define WI_CNTL_AUX_ENA_CNTL 0x8000
288: #define WI_CNTL_AUX_DIS_CNTL 0x4000
289:
290: #define WI_AUX_PAGE 0x3A
291: #define WI_AUX_OFFSET 0x3C
292: #define WI_AUX_DATA 0x3E
293:
294: #define WI_COR_OFFSET 0x40 /* COR attribute offset of card */
295: #define WI_COR_IOMODE 0x41 /* Enable i/o mode with level irqs */
296:
297: #define WI_PLX_LOCALRES 0x14 /* PLX chip's local registers */
298: #define WI_PLX_MEMRES 0x18 /* Prism attribute memory (PLX) */
299: #define WI_PLX_IORES 0x1C /* Prism I/O space (PLX) */
300: #define WI_PLX_INTCSR 0x4C /* PLX Interrupt CSR */
301: #define WI_PLX_INTEN 0x40 /* PCI Interrupt Enable bit */
302: #define WI_PLX_LINT1STAT 0x04 /* Local interrupt 1 status bit */
303: #define WI_PLX_COR_OFFSET 0x3E0 /* COR attribute offset of card */
304:
305: #define WI_ACEX_CMDRES 0x10 /* BAR0 (I/O) for ACEX-based bridge */
306: #define WI_ACEX_LOCALRES 0x14 /* BAR1 (I/O) for ACEX-based bridge */
307: #define WI_ACEX_IORES 0x18 /* BAR2 (I/O) for ACEX-based bridge */
308: #define WI_ACEX_COR_OFFSET 0xe0 /* COR attribute offset of card */
309:
310: #define WI_TMD_LOCALRES 0x14 /* TMD chip's local registers */
311: #define WI_TMD_IORES 0x18 /* Prism I/O space (TMD) */
312:
313: #define WI_DRVR_MAGIC 0x4A2D /* Magic number for card detection */
314:
315: /*
316: * PCI Host Interface Registers (HFA3842 Specific)
317: * The value of all Register's Offset, such as WI_INFO_FID and WI_PARAM0,
318: * has doubled.
319: * About WI_PCI_COR: In this Register, only soft-reset bit implement; Bit(7).
320: */
321: #define WI_PCI_CBMA 0x10
322: #define WI_PCI_COR_OFFSET 0x4C
323: #define WI_PCI_HCR 0x5C
324: #define WI_PCI_MASTER0_ADDRH 0x80
325: #define WI_PCI_MASTER0_ADDRL 0x84
326: #define WI_PCI_MASTER0_LEN 0x88
327: #define WI_PCI_MASTER0_CON 0x8C
328:
329: #define WI_PCI_STATUS 0x98
330:
331: #define WI_PCI_MASTER1_ADDRH 0xA0
332: #define WI_PCI_MASTER1_ADDRL 0xA4
333: #define WI_PCI_MASTER1_LEN 0xA8
334: #define WI_PCI_MASTER1_CON 0xAC
335:
336: #define WI_COR_SOFT_RESET (1 << 7)
337: #define WI_COR_CLEAR 0x00
338:
339: /*
340: * One form of communication with the Hermes is with what Lucent calls
341: * LTV records, where LTV stands for Length, Type and Value. The length
342: * and type are 16 bits and are in native byte order. The value is in
343: * multiples of 16 bits and is in little endian byte order.
344: */
345: struct wi_ltv_gen {
346: u_int16_t wi_len;
347: u_int16_t wi_type;
348: u_int16_t wi_val;
349: };
350:
351: struct wi_ltv_str {
352: u_int16_t wi_len;
353: u_int16_t wi_type;
354: u_int16_t wi_str[17];
355: };
356:
357: #define WI_SETVAL(recno, val) \
358: do { \
359: struct wi_ltv_gen g; \
360: \
361: g.wi_len = 2; \
362: g.wi_type = recno; \
363: g.wi_val = htole16(val); \
364: wi_write_record(sc, &g); \
365: } while (0)
366:
367: #define WI_SETSTR(recno, str) \
368: do { \
369: struct wi_ltv_str s; \
370: int l; \
371: \
372: l = (str.i_len + 1) & ~0x1; \
373: bzero((char *)&s, sizeof(s)); \
374: s.wi_len = (l / 2) + 2; \
375: s.wi_type = recno; \
376: s.wi_str[0] = htole16(str.i_len); \
377: bcopy(str.i_nwid, &s.wi_str[1], str.i_len); \
378: wi_write_record(sc, (struct wi_ltv_gen *)&s); \
379: } while (0)
380:
381: /*
382: * Download buffer location and length (0xFD01).
383: */
384: #define WI_RID_DNLD_BUF 0xFD01
385: struct wi_ltv_dnld_buf {
386: u_int16_t wi_len;
387: u_int16_t wi_type;
388: u_int16_t wi_buf_pg; /* page addr of intermediate dl buf*/
389: u_int16_t wi_buf_off; /* offset of idb */
390: u_int16_t wi_buf_len; /* len of idb */
391: };
392:
393: /*
394: * Mem sizes (0xFD02).
395: */
396: #define WI_RID_MEMSZ 0xFD02
397: struct wi_ltv_memsz {
398: u_int16_t wi_len;
399: u_int16_t wi_type;
400: u_int16_t wi_mem_ram;
401: u_int16_t wi_mem_nvram;
402: };
403:
404: /*
405: * NIC Identification (0xFD0B == WI_RID_CARD_ID)
406: */
407: struct wi_ltv_ver {
408: u_int16_t wi_len;
409: u_int16_t wi_type;
410: u_int16_t wi_ver[4];
411: };
412:
413: /*
414: * List of intended regulatory domains (WI_RID_DOMAINS = 0xFD11).
415: */
416: struct wi_ltv_domains {
417: u_int16_t wi_len;
418: u_int16_t wi_type;
419: u_int16_t wi_domains[6];
420: };
421:
422: /*
423: * CIS struct (0xFD13 == WI_RID_CIS).
424: */
425: struct wi_ltv_cis {
426: u_int16_t wi_len;
427: u_int16_t wi_type;
428: u_int16_t wi_cis[240];
429: };
430:
431: /*
432: * Communications quality (0xFD43 == WI_RID_COMMQUAL).
433: */
434: struct wi_ltv_commqual {
435: u_int16_t wi_len;
436: u_int16_t wi_type;
437: u_int16_t wi_coms_qual;
438: u_int16_t wi_sig_lvl;
439: u_int16_t wi_noise_lvl;
440: };
441:
442: /*
443: * Actual system scale thresholds (0xFD46 == WI_RID_SCALETHRESH).
444: */
445: struct wi_ltv_scalethresh {
446: u_int16_t wi_len;
447: u_int16_t wi_type;
448: u_int16_t wi_energy_detect;
449: u_int16_t wi_carrier_detect;
450: u_int16_t wi_defer;
451: u_int16_t wi_cell_search;
452: u_int16_t wi_out_of_range;
453: u_int16_t wi_delta_snr;
454: };
455:
456: /*
457: * PCF info struct (0xFD87 == WI_RID_PCF).
458: */
459: struct wi_ltv_pcf {
460: u_int16_t wi_len;
461: u_int16_t wi_type;
462: u_int16_t wi_energy_detect;
463: u_int16_t wi_carrier_detect;
464: u_int16_t wi_defer;
465: u_int16_t wi_cell_search;
466: u_int16_t wi_range;
467: };
468:
469: /*
470: * Connection control characteristics (0xFC00 == WI_RID_PORTTYPE).
471: * 1 == Basic Service Set (BSS)
472: * 2 == Wireless Distribution System (WDS)
473: * 3 == Pseudo IBSS (aka ad-hoc demo)
474: * 4 == IBSS
475: */
476: #define WI_PORTTYPE_BSS 0x1
477: #define WI_PORTTYPE_WDS 0x2
478: #define WI_PORTTYPE_ADHOC 0x3
479: #define WI_PORTTYPE_IBSS 0x4
480: #define WI_PORTTYPE_HOSTAP 0x6
481:
482: /*
483: * Mac addresses.
484: */
485: struct wi_ltv_macaddr {
486: u_int16_t wi_len;
487: u_int16_t wi_type;
488: u_int16_t wi_mac_addr[3];
489: };
490:
491: /*
492: * Station set identification (SSID).
493: */
494: struct wi_ltv_ssid {
495: u_int16_t wi_len;
496: u_int16_t wi_type;
497: u_int16_t wi_id[17];
498: };
499:
500: /*
501: * Set our station name (0xFC0E == WI_RID_NODENAME).
502: */
503: struct wi_ltv_nodename {
504: u_int16_t wi_len;
505: u_int16_t wi_type;
506: u_int16_t wi_nodename[17];
507: };
508:
509: /*
510: * Multicast addresses to be put in filter. We're allowed up
511: * to 16 addresses in the filter (0xFC80 == WI_RID_MCAST).
512: */
513: struct wi_ltv_mcast {
514: u_int16_t wi_len;
515: u_int16_t wi_type;
516: struct ether_addr wi_mcast[16];
517: };
518:
519:
520: /*
521: * Get supported data rates (0xFDC6 == WI_RID_DATA_RATES).
522: */
523: struct wi_ltv_rates {
524: u_int16_t wi_len;
525: u_int16_t wi_type;
526: u_int8_t wi_rates[10];
527: };
528:
529: /*
530: * Supported rates.
531: */
532: #define WI_SUPPRATES_1M 0x0001
533: #define WI_SUPPRATES_2M 0x0002
534: #define WI_SUPPRATES_5M 0x0004
535: #define WI_SUPPRATES_11M 0x0008
536: #define WI_RATES_BITS "\20\0011M\0022M\0035.5M\00411M"
537:
538: /*
539: * Information frame types.
540: */
541: #define WI_INFO_NOTIFY 0xF000 /* Handover address */
542: #define WI_INFO_COUNTERS 0xF100 /* Statistics counters */
543: #define WI_INFO_SCAN_RESULTS 0xF101 /* Scan results */
544: #define WI_INFO_LINK_STAT 0xF200 /* Link status */
545: #define WI_INFO_ASSOC_STAT 0xF201 /* Association status */
546:
547: /*
548: * Hermes transmit/receive frame structure
549: */
550: struct wi_frame {
551: u_int16_t wi_status; /* 0x00 */
552: u_int16_t wi_rsvd0; /* 0x02 */
553: u_int16_t wi_rsvd1; /* 0x04 */
554: u_int16_t wi_q_info; /* 0x06 */
555: u_int16_t wi_rsvd2; /* 0x08 */
556: u_int8_t wi_tx_rtry; /* 0x0A */
557: u_int8_t wi_tx_rate; /* 0x0A */
558: u_int16_t wi_tx_ctl; /* 0x0C */
559: u_int16_t wi_frame_ctl; /* 0x0E */
560: u_int16_t wi_id; /* 0x10 */
561: u_int8_t wi_addr1[6]; /* 0x12 */
562: u_int8_t wi_addr2[6]; /* 0x18 */
563: u_int8_t wi_addr3[6]; /* 0x1E */
564: u_int16_t wi_seq_ctl; /* 0x24 */
565: u_int8_t wi_addr4[6]; /* 0x26 */
566: u_int16_t wi_dat_len; /* 0x2C */
567: u_int8_t wi_dst_addr[6]; /* 0x2E */
568: u_int8_t wi_src_addr[6]; /* 0x34 */
569: u_int16_t wi_len; /* 0x3A */
570: u_int16_t wi_dat[3]; /* 0x3C */ /* SNAP header */
571: u_int16_t wi_type; /* 0x42 */
572: };
573:
574: #define WI_802_3_OFFSET 0x2E
575: #define WI_802_11_OFFSET 0x44
576: #define WI_802_11_OFFSET_RAW 0x3C
577: #define WI_802_11_OFFSET_HDR 0x0E
578:
579: #define WI_STAT_BADCRC 0x0001
580: #define WI_STAT_UNDECRYPTABLE 0x0002
581: #define WI_STAT_ERRSTAT 0x0003
582: #define WI_STAT_MAC_PORT 0x0700
583: #define WI_STAT_1042 0x2000 /* RFC1042 encoded */
584: #define WI_STAT_TUNNEL 0x4000 /* Bridge-tunnel encoded */
585: #define WI_STAT_WMP_MSG 0x6000 /* WaveLAN-II management protocol */
586: #define WI_STAT_MGMT 0x8000 /* 802.11b management frames */
587: #define WI_RXSTAT_MSG_TYPE 0xE000
588:
589: #define WI_ENC_TX_802_3 0x00
590: #define WI_ENC_TX_802_11 0x11
591: #define WI_ENC_TX_MGMT 0x08
592: #define WI_ENC_TX_E_II 0x0E
593:
594: #define WI_ENC_TX_1042 0x00
595: #define WI_ENC_TX_TUNNEL 0xF8
596:
597: #define WI_TXCNTL_MACPORT 0x00FF
598: #define WI_TXCNTL_STRUCTTYPE 0xFF00
599: #define WI_TXCNTL_TX_EX 0x0004
600: #define WI_TXCNTL_TX_OK 0x0002
601: #define WI_TXCNTL_NOCRYPT 0x0080
602:
603:
604: /*
605: * SNAP (sub-network access protocol) constants for transmission
606: * of IP datagrams over IEEE 802 networks, taken from RFC1042.
607: * We need these for the LLC/SNAP header fields in the TX/RX frame
608: * structure.
609: */
610: #define WI_SNAP_K1 0xaa /* assigned global SAP for SNAP */
611: #define WI_SNAP_K2 0x00
612: #define WI_SNAP_CONTROL 0x03 /* unnumbered information format */
613: #define WI_SNAP_WORD0 (WI_SNAP_K1 | (WI_SNAP_K1 << 8))
614: #define WI_SNAP_WORD1 (WI_SNAP_K2 | (WI_SNAP_CONTROL << 8))
615: #define WI_SNAPHDR_LEN 0x6
616: #define WI_FCS_LEN 0x4
617:
618: #define WI_ETHERTYPE_LEN 0x2
619:
620: /*
621: * HFA3861/3863 (BBP) Control Registers
622: */
623: #define WI_HFA384X_CR_A_D_TEST_MODES2 0x1a
624: #define WI_HFA384X_CR_MANUAL_TX_POWER 0x3e
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