Annotation of sys/dev/ic/i82810reg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: i82810reg.h,v 1.4 2007/05/22 04:14:03 jsg Exp $ */
2:
3: /*
4: * Copyright (c) 2000 Michael Shalayeff
5: * All rights reserved.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: *
16: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19: * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
20: * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21: * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22: * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24: * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
25: * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26: * THE POSSIBILITY OF SUCH DAMAGE.
27: */
28:
29: /* Intel i82810/810E memory and graphics controller */
30:
31: /* Host-Hub Interface Bridge/DRAM Controller Device Registers (Device 0) */
32: #define I82810_SMRAM 0x70
33: #define I82810_SMRAM_GMS_DIS 0x00
34: #define I82810_SMRAM_GMS_RSRVD 0x40
35: #define I82810_SMRAM_GMS_512 0x80
36: #define I82810_SMRAM_GMS_1024 0xc0
37: #define I82810_SMRAM_USMM_DIS 0x00
38: #define I82810_SMRAM_USMM_TDHE 0x10
39: #define I82810_SMRAM_USMM_T5HE 0x20
40: #define I82810_SMRAM_USMM_T1HE 0x30
41: #define I82810_SMRAM_LSMM_DIS 0x00
42: #define I82810_SMRAM_LSMM_GSM 0x04
43: #define I82810_SMRAM_LSMM_CRSH 0x08
44: #define I82810_SMRAM_D_LCK 0x02
45: #define I82810_SMRAM_E_SMERR 0x01
46: #define I82810_MISCC 0x72
47: #define I82810_MISCC_GDCWS 0x0001
48: #define I82810_MISCC_P_LCK 0x0008
49: #define I82810_MISCC_WPTHC_NO 0x0000
50: #define I82810_MISCC_WPTHC_625 0x0010
51: #define I82810_MISCC_WPTHC_500 0x0020
52: #define I82810_MISCC_WPTHC_375 0x0030
53: #define I82810_MISCC_RPTHC_NO 0x0000
54: #define I82810_MISCC_RPTHC_625 0x0040
55: #define I82810_MISCC_RPTHC_500 0x0080
56: #define I82810_MISCC_RPTHC_375 0x00c0
57:
58: /* Graphics Device Registers (Device 1) */
59: #define I82810_GMADR 0x10
60: #define I82810_MMADR 0x14
61:
62: #define I82810_DRT 0x3000
63: #define I82810_DRT_DP 0x01
64: #define I82810_DRAMCL 0x3001
65: #define I82810_DRAMCL_RPT 0x01
66: #define I82810_DRAMCL_RT 0x02
67: #define I82810_DRAMCL_CL 0x04
68: #define I82810_DRAMCL_RCO 0x08
69: #define I82810_DRAMCL_PMC 0x10
70: #define I82810_DRAMCH 0x3002
71: #define I82810_DRAMCH_SMS 0x07
72: #define I82810_DRAMCH_DRR 0x18
73: #define I82810_GTT 0x10000
74:
75: /*
76: * Intel i82820 memory and graphics controller
77: */
78:
79: /* Host-Hub Interface Bridge/DRAM Controller Device Registers (Device 0) */
80: #define I82820_SMRAM 0x9c
81: #define I82820_SMRAM_SHIFT 8
82: #define I82820_SMRAM_G_SMRAME (1 << 3)
83: #define I82820_SMRAM_D_LCK (1 << 4)
84: #define I82820_SMRAM_D_CLS (1 << 5)
85: #define I82820_SMRAM_D_OPEN (1 << 6)
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