Annotation of sys/dev/ic/i82595reg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: i82595reg.h,v 1.3 2003/10/21 18:58:49 jmc Exp $ */
2: /* $NetBSD: i82595reg.h,v 1.1 1996/05/06 21:36:51 is Exp $ */
3:
4: /*
5: * Copyright (c) 1996, Ignatios Souvatzis.
6: * All rights reserved.
7: *
8: * Redistribution and use in source and binary forms, with or without
9: * modification, are permitted provided that the following conditions
10: * are met:
11: * 1. Redistributions of source code must retain the above copyright
12: * notice, this list of conditions and the following disclaimer.
13: * 2. Redistributions in binary form must reproduce the above copyright
14: * notice, this list of conditions and the following disclaimer in the
15: * documentation and/or other materials provided with the distribution.
16: * 3. All advertising materials mentioning features or use of this software
17: * must display the following acknowledgement:
18: * This product includes software developed by Ignatios Souvatzis
19: * for the NetBSD project.
20: * 4. The name of the author may not be used to endorse or promote products
21: * derived from this software without specific prior written permission.
22: *
23: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
24: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26: * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
27: * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28: * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33: * SUCH DAMAGE.
34: */
35:
36: /*
37: * Intel 82595 Ethernet chip register, bit, and structure definitions.
38: *
39: * Written by is with reference to Intel's i82595FX data sheet, with some
40: * clarification coming from looking at the Clarkson Packet Driver code for this
41: * chip written by Russ Nelson and others;
42: *
43: * and
44: *
45: * configuration EEPROM layout. Written with reference to Intels
46: * public "LAN595 Hardware and Software Specifications" document.
47: */
48:
49: /* registers */
50:
51: /* bank0 */
52:
53: #define COMMAND_REG 0 /* available in any bank */
54:
55: #define MC_SETUP_CMD 0x03
56: #define XMT_CMD 0x04
57: #define TDR_CMD 0x05
58: #define DUMP_CMD 0x06
59: #define DIAG_CMD 0x07
60: #define RCV_ENABLE_CMD 0x08
61: #define RCV_DISABLE_CMD 0x0a
62: #define RCV_STOP_CMD 0x0b
63: #define RESET_CMD 0x0e
64: #define TRISTATE_CMD 0x16
65: #define NO_TRISTATE_CMD 0x17
66: #define POWER_DOWN_CMD 0x18
67: #define SLEEP_MODE_CMD 0x19
68: #define NEGOTIATE_CMD 0x1a
69: #define RESUME_XMT_CMD 0x1c
70: #define SEL_RESET_CMD 0x1e
71: #define BANK_SEL(n) (n<<6) /* 0, 1, 2 */
72:
73: #define STATUS_REG 1
74:
75: #define RX_STP_INT 0x01
76: #define RX_INT 0x02
77: #define TX_INT 0x04
78: #define EXEC_INT 0x08
79: #define EXEC_STATUS 0x30
80:
81: #define ID_REG 2
82:
83: #define ID_REG_MASK 0x2c
84: #define ID_REG_SIG 0x24
85: #define R_ROBIN_BITS 0xc0
86: #define R_ROBIN_SHIFT 6
87: #define AUTO_ENABLE 0x10
88:
89: #define INT_MASK_REG 3
90:
91: #define RX_STOP_BIT 0x01
92: #define RX_BIT 0x02
93: #define TX_BIT 0x04
94: #define EXEC_BIT 0x08
95: #define ALL_INTS 0x0f
96:
97: #define RCV_START_LOW 4
98: #define RCV_START_HIGH 5
99:
100: #define RCV_STOP_LOW 6
101: #define RCV_STOP_HIGH 7
102:
103: #define XMT_ADDR_REG 0x0a
104: #define HOST_ADDR_REG 0x0c
105: #define MEM_PORT_REG 0x0e
106:
107: /* -------------------- bank1 -------------------- */
108:
109: #define REG1 1
110:
111: #define WORD_WIDTH 0x02
112: #define INT_ENABLE 0x80
113:
114: #define INT_NO_REG 2
115:
116: #define RCV_LOWER_LIMIT_REG 8
117: #define RCV_UPPER_LIMIT_REG 9
118:
119: #define XMT_LOWER_LIMIT_REG 10
120: #define XMT_UPPER_LIMIT_REG 11
121:
122: /* bank2 */
123:
124: /* reg1, apparently */
125:
126: #define XMT_CHAIN_INT 0x20 /* interrupt at end of xmt chain */
127: #define XMT_CHAIN_ERRSTOP 0x40 /* int at end of chain even if err */
128: #define RCV_DISCARD_BAD 0x80 /* Throw bad frames away and continue */
129:
130: #define RECV_MODES_REG 2
131:
132: #define PROMISC_MODE 0x01
133: #define NO_RX_CRC 0x04
134: #define NO_ADD_INS 0x10
135: #define MULTI_IA 0x20
136:
137: #define MATCH_ID (NO_ADD_INS | NO_RX_CRC | 0x02)
138: #define MATCH_ALL (NO_ADD_INS | NO_RX_CRC | 0x01)
139: #define MATCH_BRDCST (NO_ADD_INS | NO_RX_CRC)
140:
141: #define MEDIA_SELECT 3
142:
143: #define TPE_BIT 0x04
144: #define BNC_BIT 0x20
145: #define TEST_MODE_MASK 0x3f
146:
147: #define I_ADD(n) (n+4) /* 0..5 -> 4..9 */
148:
149: #define EEPROM_REG 10
150:
151: #define EEDO 8
152: #define EEDI 4
153: #define EECS 2
154: #define EESK 1
155:
156: /*
157: * EEPROM layout. Written with reference to Intels public "LAN595 Hardware and
158: * Software Specifications" document.
159: */
160:
161: #define EEPPW0 0
162: #define EEPP_BusWidth 0x0004
163: #define EEPP_FlashAdrs 0x0038
164: #define EEPP_FLASHTRANSFORM {-1, -1, 0xC8000, 0xCC000, 0xD0000, \
165: 0xD4000, 0xD8000, 0xDC000}
166: #define EEPP_AutoIO 0x0040
167: #define EEPP_IOMapping 0xfc00
168:
169: #define EEPPW1 1
170: #define EEPP_Int 0x0007
171: #define EEPP_INTMAP {3, 5, 9, 10, 11, -1, -1, -1}
172: #define EEPP_RINTMAP {0xff, 0xff, 0x02, 0x00, 0xff, 0x01, 0xff, \
173: 0xff, 0xff, 0x02, 0x03, 0x04 }
174:
175: #define EEPP_LinkInteg 0x0008
176: #define EEPP_PolarCorr 0x0010
177: #define EEPP_AuiTpe 0x0020
178: #define EEPP_Jabber 0x0040
179: #define EEPP_AutoPort 0x0080
180: #define EEPP_SmOut 0x0100
181: #define EEPP_BootFls 0x0200
182: #define EEPP_DramSize 0x1000
183: #define EEPP_AltReady 0x2000
184:
185: #define EEPPEther2 2
186: #define EEPPEther1 3
187: #define EEPPEther0 4
188:
189: #define EEPPEther2a 0x3c
190: #define EEPPEther1a 0x3d
191: #define EEPPEther0a 0x3e
192:
193: #define EEPPW5 5
194: #define EEPP_BncTpe 0x0001
195: #define EEPP_RomSlct 0x0006 /* none, NetWare, NDIS, rsrvd. */
196: #define EEPP_NumConn 0x0008 /* 0=2, 1=3 */
197:
198: #define EEPW6 6
199: #define EEPP_BoardRev 0x00FF
200:
201: #define EEPP_LENGTH 0x40
202: #define EEPP_CHKSUM 0xBABA /* Intel claim 0x0, but this seems to be wrong */
203:
204: #define I595_XMT_HDRLEN 8
205:
206: #define CMD_MASK 0x001f
207: #define TX_DONE 0x0080
208: #define CHAIN 0x8000
209:
210: #define XMT_STATUS 0x02
211: #define XMT_CHAIN 0x04
212: #define XMT_COUNT 0x06
213:
214: #define I595_RCV_HDRLEN 8
215:
216: #define RCV_DONE 0x0008
217: #define RX_OK 0x2000
218: #define RX_ERR 0x0d81
219:
220:
CVSweb
![[BACK]](/icons/back.gif){kind=icon}
Return to i82595reg.h CVS log ![[TXT]](/icons/text.gif){kind=icon}
![[DIR]](/icons/dir.gif){kind=icon}
Up to [local] / sys / dev / ic