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Annotation of sys/dev/ic/i8253reg.h, Revision 1.1.1.1

1.1       nbrk        1: /*     $OpenBSD: i8253reg.h,v 1.3 2003/06/02 23:28:02 millert Exp $    */
                      2: /*     $NetBSD: i8253reg.h,v 1.5 1998/01/19 11:38:00 drochner Exp $    */
                      3:
                      4: /*-
                      5:  * Copyright (c) 1993 The Regents of the University of California.
                      6:  * All rights reserved.
                      7:  *
                      8:  * Redistribution and use in source and binary forms, with or without
                      9:  * modification, are permitted provided that the following conditions
                     10:  * are met:
                     11:  * 1. Redistributions of source code must retain the above copyright
                     12:  *    notice, this list of conditions and the following disclaimer.
                     13:  * 2. Redistributions in binary form must reproduce the above copyright
                     14:  *    notice, this list of conditions and the following disclaimer in the
                     15:  *    documentation and/or other materials provided with the distribution.
                     16:  * 3. Neither the name of the University nor the names of its contributors
                     17:  *    may be used to endorse or promote products derived from this software
                     18:  *    without specific prior written permission.
                     19:  *
                     20:  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
                     21:  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
                     22:  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
                     23:  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
                     24:  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
                     25:  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
                     26:  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
                     27:  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
                     28:  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
                     29:  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
                     30:  * SUCH DAMAGE.
                     31:  */
                     32:
                     33: /*
                     34:  * Register definitions for the Intel 8253 Programmable Interval Timer.
                     35:  *
                     36:  * This chip has three independent 16-bit down counters that can be
                     37:  * read on the fly.  There are three mode registers and three countdown
                     38:  * registers.  The countdown registers are addressed directly, via the
                     39:  * first three I/O ports.  The three mode registers are accessed via
                     40:  * the fourth I/O port, with two bits in the mode byte indicating the
                     41:  * register.  (Why are hardware interfaces always so braindead?).
                     42:  *
                     43:  * To write a value into the countdown register, the mode register
                     44:  * is first programmed with a command indicating which byte of
                     45:  * the two byte register is to be modified.  The three possibilities
                     46:  * are load msb (TMR_MR_MSB), load lsb (TMR_MR_LSB), or load lsb then
                     47:  * msb (TMR_MR_BOTH).
                     48:  *
                     49:  * To read the current value ("on the fly") from the countdown register,
                     50:  * you write a "latch" command into the mode register, then read the stable
                     51:  * value from the corresponding I/O port.  For example, you write
                     52:  * TMR_MR_LATCH into the corresponding mode register.  Presumably,
                     53:  * after doing this, a write operation to the I/O port would result
                     54:  * in undefined behavior (but hopefully not fry the chip).
                     55:  * Reading in this manner has no side effects.
                     56:  *
                     57:  * The outputs of the three timers are connected as follows:
                     58:  *
                     59:  *      timer 0 -> irq 0
                     60:  *      timer 1 -> dma chan 0 (for dram refresh)
                     61:  *      timer 2 -> speaker (via keyboard controller)
                     62:  *
                     63:  * Timer 0 is used to call hardclock.
                     64:  * Timer 2 is used to generate console beeps.
                     65:  */
                     66:
                     67: /*
                     68:  * Frequency of all three count-down timers; (TIMER_FREQ/freq) is the
                     69:  * appropriate count to generate a frequency of freq hz.
                     70:  */
                     71: #ifndef TIMER_FREQ
                     72: #define        TIMER_FREQ      1193182
                     73: #endif
                     74: #define TIMER_DIV(x) ((TIMER_FREQ+(x)/2)/(x))
                     75:
                     76: /*
                     77:  * Macros for specifying values to be written into a mode register.
                     78:  */
                     79: #define        TIMER_CNTR0     0       /* timer 0 counter port */
                     80: #define        TIMER_CNTR1     1       /* timer 1 counter port */
                     81: #define        TIMER_CNTR2     2       /* timer 2 counter port */
                     82: #define        TIMER_MODE      3       /* timer mode port */
                     83: #define                TIMER_SEL0      0x00    /* select counter 0 */
                     84: #define                TIMER_SEL1      0x40    /* select counter 1 */
                     85: #define                TIMER_SEL2      0x80    /* select counter 2 */
                     86: #define                TIMER_INTTC     0x00    /* mode 0, intr on terminal cnt */
                     87: #define                TIMER_ONESHOT   0x02    /* mode 1, one shot */
                     88: #define                TIMER_RATEGEN   0x04    /* mode 2, rate generator */
                     89: #define                TIMER_SQWAVE    0x06    /* mode 3, square wave */
                     90: #define                TIMER_SWSTROBE  0x08    /* mode 4, s/w triggered strobe */
                     91: #define                TIMER_HWSTROBE  0x0a    /* mode 5, h/w triggered strobe */
                     92: #define                TIMER_LATCH     0x00    /* latch counter for reading */
                     93: #define                TIMER_LSB       0x10    /* r/w counter LSB */
                     94: #define                TIMER_MSB       0x20    /* r/w counter MSB */
                     95: #define                TIMER_16BIT     0x30    /* r/w counter 16 bits, LSB first */
                     96: #define                TIMER_BCD       0x01    /* count in BCD */
                     97: