Annotation of sys/dev/ic/i82365reg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: i82365reg.h,v 1.7 1999/05/02 22:35:40 fgsch Exp $ */
2: /* $NetBSD: i82365reg.h,v 1.2 1997/10/16 23:18:18 thorpej Exp $ */
3:
4: /*
5: * Copyright (c) 1997 Marc Horowitz. All rights reserved.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: * 3. All advertising materials mentioning features or use of this software
16: * must display the following acknowledgement:
17: * This product includes software developed by Marc Horowitz.
18: * 4. The name of the author may not be used to endorse or promote products
19: * derived from this software without specific prior written permission.
20: *
21: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31: */
32:
33: /*
34: * All information is from the intel 82365sl PC Card Interface Controller
35: * (PCIC) data sheet, marked "preliminary". Order number 290423-002, January
36: * 1993.
37: */
38:
39: #define PCIC_IOSIZE 2
40:
41: #define PCIC_REG_INDEX 0
42: #define PCIC_REG_DATA 1
43:
44: /*
45: * The PCIC allows two chips to share the same address. In order not to run
46: * afoul of the netbsd device model, this driver will treat those chips as
47: * the same device.
48: */
49:
50: #define PCIC_CHIP0_BASE 0x00
51: #define PCIC_CHIP1_BASE 0x80
52:
53: /* Each PCIC chip can drive two sockets */
54:
55: #define PCIC_SOCKETA_INDEX 0x00
56: #define PCIC_SOCKETB_INDEX 0x40
57:
58: /* general setup registers */
59:
60: #define PCIC_IDENT 0x00 /* RO */
61: #define PCIC_IDENT_IFTYPE_MASK 0xC0
62: #define PCIC_IDENT_IFTYPE_IO_ONLY 0x00
63: #define PCIC_IDENT_IFTYPE_MEM_ONLY 0x40
64: #define PCIC_IDENT_IFTYPE_MEM_AND_IO 0x80
65: #define PCIC_IDENT_IFTYPE_RESERVED 0xC0
66: #define PCIC_IDENT_ZERO 0x30
67: #define PCIC_IDENT_REV_MASK 0x0F
68: #define PCIC_IDENT_REV_I82365SLR0 0x82
69: #define PCIC_IDENT_REV_I82365SLR1 0x83
70: #define PCIC_IDENT_REV_I82365SLR2 0x84
71:
72: #define PCIC_IF_STATUS 0x01 /* RO */
73: #define PCIC_IF_STATUS_GPI 0x80 /* General Purpose Input */
74: #define PCIC_IF_STATUS_POWERACTIVE 0x40
75: #define PCIC_IF_STATUS_READY 0x20 /* really READY/!BUSY */
76: #define PCIC_IF_STATUS_MEM_WP 0x10
77: #define PCIC_IF_STATUS_CARDDETECT_MASK 0x0C
78: #define PCIC_IF_STATUS_CARDDETECT_PRESENT 0x0C
79: #define PCIC_IF_STATUS_BATTERY_MASK 0x03
80: #define PCIC_IF_STATUS_BATTERY_DEAD1 0x00
81: #define PCIC_IF_STATUS_BATTERY_DEAD2 0x01
82: #define PCIC_IF_STATUS_BATTERY_WARNING 0x02
83: #define PCIC_IF_STATUS_BATTERY_GOOD 0x03
84:
85: #define PCIC_PWRCTL 0x02 /* RW */
86: #define PCIC_PWRCTL_OE 0x80 /* output enable */
87: #define PCIC_PWRCTL_DISABLE_RESETDRV 0x40
88: #define PCIC_PWRCTL_AUTOSWITCH_ENABLE 0x20
89: #define PCIC_PWRCTL_PWR_ENABLE 0x10
90: #define PCIC_PWRCTL_VPP2_MASK 0x0C
91: /* XXX these are a little unclear from the data sheet */
92: #define PCIC_PWRCTL_VPP2_RESERVED 0x0C
93: #define PCIC_PWRCTL_VPP2_EN1 0x08
94: #define PCIC_PWRCTL_VPP2_EN0 0x04
95: #define PCIC_PWRCTL_VPP2_ENX 0x00
96: #define PCIC_PWRCTL_VPP1_MASK 0x03
97: /* XXX these are a little unclear from the data sheet */
98: #define PCIC_PWRCTL_VPP1_RESERVED 0x03
99: #define PCIC_PWRCTL_VPP1_EN1 0x02
100: #define PCIC_PWRCTL_VPP1_EN0 0x01
101: #define PCIC_PWRCTL_VPP1_ENX 0x00
102:
103: #define PCIC_CSC 0x04 /* RW */
104: #define PCIC_CSC_ZERO 0xE0
105: #define PCIC_CSC_GPI 0x10
106: #define PCIC_CSC_CD 0x08 /* Card Detect Change */
107: #define PCIC_CSC_READY 0x04
108: #define PCIC_CSC_BATTWARN 0x02
109: #define PCIC_CSC_BATTDEAD 0x01 /* for memory cards */
110: #define PCIC_CSC_RI 0x01 /* for i/o cards */
111:
112: #define PCIC_ADDRWIN_ENABLE 0x06 /* RW */
113: #define PCIC_ADDRWIN_ENABLE_IO1 0x80
114: #define PCIC_ADDRWIN_ENABLE_IO0 0x40
115: #define PCIC_ADDRWIN_ENABLE_MEMCS16 0x20 /* rtfds if you care */
116: #define PCIC_ADDRWIN_ENABLE_MEM4 0x10
117: #define PCIC_ADDRWIN_ENABLE_MEM3 0x08
118: #define PCIC_ADDRWIN_ENABLE_MEM2 0x04
119: #define PCIC_ADDRWIN_ENABLE_MEM1 0x02
120: #define PCIC_ADDRWIN_ENABLE_MEM0 0x01
121:
122: #define PCIC_CARD_DETECT 0x16 /* RW */
123: #define PCIC_CARD_DETECT_RESERVED 0xC0
124: #define PCIC_CARD_DETECT_SW_INTR 0x20
125: #define PCIC_CARD_DETECT_RESUME_ENABLE 0x10
126: #define PCIC_CARD_DETECT_GPI_TRANSCTL 0x08
127: #define PCIC_CARD_DETECT_GPI_ENABLE 0x04
128: #define PCIC_CARD_DETECT_CFGRST_ENABLE 0x02
129: #define PCIC_CARD_DETECT_MEMDLY_INHIBIT 0x01
130:
131: /* interrupt registers */
132:
133: #define PCIC_INTR 0x03 /* RW */
134: #define PCIC_INTR_RI_ENABLE 0x80
135: #define PCIC_INTR_RESET 0x40 /* active low (zero) */
136: #define PCIC_INTR_CARDTYPE_MASK 0x20
137: #define PCIC_INTR_CARDTYPE_IO 0x20
138: #define PCIC_INTR_CARDTYPE_MEM 0x00
139: #define PCIC_INTR_ENABLE 0x10
140: #define PCIC_INTR_IRQ_MASK 0x0F
141: #define PCIC_INTR_IRQ_SHIFT 0
142: #define PCIC_INTR_IRQ_NONE 0x00
143: #define PCIC_INTR_IRQ_RESERVED1 0x01
144: #define PCIC_INTR_IRQ_RESERVED2 0x02
145: #define PCIC_INTR_IRQ3 0x03
146: #define PCIC_INTR_IRQ4 0x04
147: #define PCIC_INTR_IRQ5 0x05
148: #define PCIC_INTR_IRQ_RESERVED6 0x06
149: #define PCIC_INTR_IRQ7 0x07
150: #define PCIC_INTR_IRQ_RESERVED8 0x08
151: #define PCIC_INTR_IRQ9 0x09
152: #define PCIC_INTR_IRQ10 0x0A
153: #define PCIC_INTR_IRQ11 0x0B
154: #define PCIC_INTR_IRQ12 0x0C
155: #define PCIC_INTR_IRQ_RESERVED13 0x0D
156: #define PCIC_INTR_IRQ14 0x0E
157: #define PCIC_INTR_IRQ15 0x0F
158:
159: #define PCIC_INTR_IRQ_VALIDMASK 0xDEB8 /* 1101 1110 1011 1000 */
160:
161: #define PCIC_CSC_INTR 0x05 /* RW */
162: #define PCIC_CSC_INTR_IRQ_MASK 0xF0
163: #define PCIC_CSC_INTR_IRQ_SHIFT 4
164: #define PCIC_CSC_INTR_IRQ_NONE 0x00
165: #define PCIC_CSC_INTR_IRQ_RESERVED1 0x10
166: #define PCIC_CSC_INTR_IRQ_RESERVED2 0x20
167: #define PCIC_CSC_INTR_IRQ3 0x30
168: #define PCIC_CSC_INTR_IRQ4 0x40
169: #define PCIC_CSC_INTR_IRQ5 0x50
170: #define PCIC_CSC_INTR_IRQ_RESERVED6 0x60
171: #define PCIC_CSC_INTR_IRQ7 0x70
172: #define PCIC_CSC_INTR_IRQ_RESERVED8 0x80
173: #define PCIC_CSC_INTR_IRQ9 0x90
174: #define PCIC_CSC_INTR_IRQ10 0xA0
175: #define PCIC_CSC_INTR_IRQ11 0xB0
176: #define PCIC_CSC_INTR_IRQ12 0xC0
177: #define PCIC_CSC_INTR_IRQ_RESERVED13 0xD0
178: #define PCIC_CSC_INTR_IRQ14 0xE0
179: #define PCIC_CSC_INTR_IRQ15 0xF0
180: #define PCIC_CSC_INTR_CD_ENABLE 0x08
181: #define PCIC_CSC_INTR_READY_ENABLE 0x04
182: #define PCIC_CSC_INTR_BATTWARN_ENABLE 0x02
183: #define PCIC_CSC_INTR_BATTDEAD_ENABLE 0x01 /* for memory cards */
184: #define PCIC_CSC_INTR_RI_ENABLE 0x01 /* for I/O cards */
185:
186: #define PCIC_CSC_INTR_IRQ_VALIDMASK 0xDEB8 /* 1101 1110 1011 1000 */
187:
188: /* I/O registers */
189:
190: #define PCIC_IO_WINS 2
191:
192: #define PCIC_IOCTL 0x07 /* RW */
193: #define PCIC_IOCTL_IO1_WAITSTATE 0x80
194: #define PCIC_IOCTL_IO1_ZEROWAIT 0x40
195: #define PCIC_IOCTL_IO1_IOCS16SRC_MASK 0x20
196: #define PCIC_IOCTL_IO1_IOCS16SRC_CARD 0x20
197: #define PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE 0x00
198: #define PCIC_IOCTL_IO1_DATASIZE_MASK 0x10
199: #define PCIC_IOCTL_IO1_DATASIZE_16BIT 0x10
200: #define PCIC_IOCTL_IO1_DATASIZE_8BIT 0x00
201: #define PCIC_IOCTL_IO0_WAITSTATE 0x08
202: #define PCIC_IOCTL_IO0_ZEROWAIT 0x04
203: #define PCIC_IOCTL_IO0_IOCS16SRC_MASK 0x02
204: #define PCIC_IOCTL_IO0_IOCS16SRC_CARD 0x02
205: #define PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE 0x00
206: #define PCIC_IOCTL_IO0_DATASIZE_MASK 0x01
207: #define PCIC_IOCTL_IO0_DATASIZE_16BIT 0x01
208: #define PCIC_IOCTL_IO0_DATASIZE_8BIT 0x00
209:
210: #define PCIC_IOADDR0_START_LSB 0x08
211: #define PCIC_IOADDR0_START_MSB 0x09
212: #define PCIC_IOADDR0_STOP_LSB 0x0A
213: #define PCIC_IOADDR0_STOP_MSB 0x0B
214: #define PCIC_IOADDR1_START_LSB 0x0C
215: #define PCIC_IOADDR1_START_MSB 0x0D
216: #define PCIC_IOADDR1_STOP_LSB 0x0E
217: #define PCIC_IOADDR1_STOP_MSB 0x0F
218:
219: /* memory registers */
220:
221: /*
222: * memory window addresses refer to bits A23-A12 of the ISA system memory
223: * address. This is a shift of 12 bits. The LSB contains A19-A12, and the
224: * MSB contains A23-A20, plus some other bits.
225: */
226:
227: #define PCIC_MEM_WINS 5
228:
229: #define PCIC_MEM_SHIFT 12
230: #define PCIC_MEM_PAGESIZE (1<<PCIC_MEM_SHIFT)
231:
232: #define PCIC_SYSMEM_ADDRX_SHIFT PCIC_MEM_SHIFT
233: #define PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_MASK 0x80
234: #define PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT 0x80
235: #define PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_8BIT 0x00
236: #define PCIC_SYSMEM_ADDRX_START_MSB_ZEROWAIT 0x40
237: #define PCIC_SYSMEM_ADDRX_START_MSB_SCRATCH_MASK 0x30
238: #define PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK 0x0F
239:
240: #define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT_MASK 0xC0
241: #define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT0 0x00
242: #define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT1 0x40
243: #define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2 0x80
244: #define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT3 0xC0
245: #define PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK 0x0F
246:
247: /*
248: * The card side of a memory mapping consists of bits A19-A12 of the card
249: * memory address in the LSB, and A25-A20 plus some other bits in the MSB.
250: * Again, the shift is 12 bits.
251: */
252:
253: #define PCIC_CARDMEM_ADDRX_SHIFT PCIC_MEM_SHIFT
254: #define PCIC_CARDMEM_ADDRX_MSB_WP 0x80
255: #define PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_MASK 0x40
256: #define PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR 0x40
257: #define PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_COMMON 0x00
258: #define PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK 0x3F
259:
260: #define PCIC_SYSMEM_ADDR0_START_LSB 0x10
261: #define PCIC_SYSMEM_ADDR0_START_MSB 0x11
262: #define PCIC_SYSMEM_ADDR0_STOP_LSB 0x12
263: #define PCIC_SYSMEM_ADDR0_STOP_MSB 0x13
264:
265: #define PCIC_CARDMEM_ADDR0_LSB 0x14
266: #define PCIC_CARDMEM_ADDR0_MSB 0x15
267:
268: /* #define PCIC_RESERVED 0x17 */
269:
270: #define PCIC_SYSMEM_ADDR1_START_LSB 0x18
271: #define PCIC_SYSMEM_ADDR1_START_MSB 0x19
272: #define PCIC_SYSMEM_ADDR1_STOP_LSB 0x1A
273: #define PCIC_SYSMEM_ADDR1_STOP_MSB 0x1B
274:
275: #define PCIC_CARDMEM_ADDR1_LSB 0x1C
276: #define PCIC_CARDMEM_ADDR1_MSB 0x1D
277:
278: #define PCIC_SYSMEM_ADDR2_START_LSB 0x20
279: #define PCIC_SYSMEM_ADDR2_START_MSB 0x21
280: #define PCIC_SYSMEM_ADDR2_STOP_LSB 0x22
281: #define PCIC_SYSMEM_ADDR2_STOP_MSB 0x23
282:
283: #define PCIC_CARDMEM_ADDR2_LSB 0x24
284: #define PCIC_CARDMEM_ADDR2_MSB 0x25
285:
286: /* #define PCIC_RESERVED 0x26 */
287: /* #define PCIC_RESERVED 0x27 */
288:
289: #define PCIC_SYSMEM_ADDR3_START_LSB 0x28
290: #define PCIC_SYSMEM_ADDR3_START_MSB 0x29
291: #define PCIC_SYSMEM_ADDR3_STOP_LSB 0x2A
292: #define PCIC_SYSMEM_ADDR3_STOP_MSB 0x2B
293:
294: #define PCIC_CARDMEM_ADDR3_LSB 0x2C
295: #define PCIC_CARDMEM_ADDR3_MSB 0x2D
296:
297: /* #define PCIC_RESERVED 0x2E */
298: /* #define PCIC_RESERVED 0x2F */
299:
300: #define PCIC_SYSMEM_ADDR4_START_LSB 0x30
301: #define PCIC_SYSMEM_ADDR4_START_MSB 0x31
302: #define PCIC_SYSMEM_ADDR4_STOP_LSB 0x32
303: #define PCIC_SYSMEM_ADDR4_STOP_MSB 0x33
304:
305: #define PCIC_CARDMEM_ADDR4_LSB 0x34
306: #define PCIC_CARDMEM_ADDR4_MSB 0x35
307:
308: /* #define PCIC_RESERVED 0x36 */
309: /* #define PCIC_RESERVED 0x37 */
310: /* #define PCIC_RESERVED 0x38 */
311: /* #define PCIC_RESERVED 0x39 */
312: /* #define PCIC_RESERVED 0x3A */
313: /* #define PCIC_RESERVED 0x3B */
314: /* #define PCIC_RESERVED 0x3C */
315: /* #define PCIC_RESERVED 0x3D */
316: /* #define PCIC_RESERVED 0x3E */
317: /* #define PCIC_RESERVED 0x3F */
318:
319: /* vendor-specific registers */
320:
321: #define PCIC_INTEL_GLOBAL_CTL 0x1E /* RW */
322: #define PCIC_INTEL_GLOBAL_CTL_RESERVED 0xF0
323: #define PCIC_INTEL_GLOBAL_CTL_IRQ14PULSE_ENABLE 0x08
324: #define PCIC_INTEL_GLOBAL_CTL_EXPLICIT_CSC_ACK 0x04
325: #define PCIC_INTEL_GLOBAL_CTL_IRQLEVEL_ENABLE 0x02
326: #define PCIC_INTEL_GLOBAL_CTL_POWERDOWN 0x01
327:
328: #define PCIC_CIRRUS_MISC_CTL_2 0x1E
329: #define PCIC_CIRRUS_MISC_CTL_2_SUSPEND 0x04
330:
331: #define PCIC_CIRRUS_CHIP_INFO 0x1F
332: #define PCIC_CIRRUS_CHIP_INFO_CHIP_ID 0xC0
333: #define PCIC_CIRRUS_CHIP_INFO_SLOTS 0x20
334: #define PCIC_CIRRUS_CHIP_INFO_REV 0x1F
335:
336: #define PCIC_CIRRUS_EXTENDED_INDEX 0x2E
337: #define PCIC_CIRRUS_EXTENDED_DATA 0x2F
338: #define PCIC_CIRRUS_EXT_CONTROL_1 0x03
339: #define PCIC_CIRRUS_EXT_CONTROL_1_PCI_INTR_MASK 0x18
340:
341: #define PCIC_IDENT_VADEM_MASK 0x08
342:
343: #define PCIC_VG468_MISC 0x3A
344: #define PCIC_VG468_MISC_VADEMREV 0x40
345:
346: #define PCIC_VG469_VSELECT 0x2f
347: #define PCIC_VG469_VSELECT_VCC 0x03
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