Annotation of sys/dev/ic/dp8390reg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: dp8390reg.h,v 1.9 2003/10/21 18:58:49 jmc Exp $ */
! 2: /* $NetBSD: dp8390reg.h,v 1.3 1997/04/29 04:32:08 scottr Exp $ */
! 3:
! 4: /*
! 5: * National Semiconductor DS8390 NIC register definitions.
! 6: *
! 7: * Copyright (C) 1993, David Greenman. This software may be used, modified,
! 8: * copied, distributed, and sold, in both source and binary form provided that
! 9: * the above copyright and these terms are retained. Under no circumstances is
! 10: * the author responsible for the proper functioning of this software, nor does
! 11: * the author assume any responsibility for damages incurred with its use.
! 12: */
! 13:
! 14: /*
! 15: * Page 0 register offsets
! 16: */
! 17: #define ED_P0_CR 0x00 /* Command Register */
! 18:
! 19: #define ED_P0_CLDA0 0x01 /* Current Local DMA Addr low (read) */
! 20: #define ED_P0_PSTART 0x01 /* Page Start register (write) */
! 21:
! 22: #define ED_P0_CLDA1 0x02 /* Current Local DMA Addr high (read) */
! 23: #define ED_P0_PSTOP 0x02 /* Page Stop register (write) */
! 24:
! 25: #define ED_P0_BNRY 0x03 /* Boundary Pointer */
! 26:
! 27: #define ED_P0_TSR 0x04 /* Transmit Status Register (read) */
! 28: #define ED_P0_TPSR 0x04 /* Transmit Page Start (write) */
! 29:
! 30: #define ED_P0_NCR 0x05 /* Number of Collisions Reg (read) */
! 31: #define ED_P0_TBCR0 0x05 /* Transmit Byte count, low (write) */
! 32:
! 33: #define ED_P0_FIFO 0x06 /* FIFO register (read) */
! 34: #define ED_P0_TBCR1 0x06 /* Transmit Byte count, high (write) */
! 35:
! 36: #define ED_P0_ISR 0x07 /* Interrupt Status Register */
! 37:
! 38: #define ED_P0_CRDA0 0x08 /* Current Remote DMA Addr low (read) */
! 39: #define ED_P0_RSAR0 0x08 /* Remote Start Address low (write) */
! 40:
! 41: #define ED_P0_CRDA1 0x09 /* Current Remote DMA Addr high (read) */
! 42: #define ED_P0_RSAR1 0x09 /* Remote Start Address high (write) */
! 43:
! 44: #define ED_P0_RBCR0 0x0a /* Remote Byte Count low (write) */
! 45:
! 46: #define ED_P0_RBCR1 0x0b /* Remote Byte Count high (write) */
! 47:
! 48: #define ED_P0_RSR 0x0c /* Receive Status (read) */
! 49: #define ED_P0_RCR 0x0c /* Receive Configuration Reg (write) */
! 50:
! 51: #define ED_P0_CNTR0 0x0d /* frame alignment error counter (read) */
! 52: #define ED_P0_TCR 0x0d /* Transmit Configuration Reg (write) */
! 53:
! 54: #define ED_P0_CNTR1 0x0e /* CRC error counter (read) */
! 55: #define ED_P0_DCR 0x0e /* Data Configuration Reg (write) */
! 56:
! 57: #define ED_P0_CNTR2 0x0f /* missed packet counter (read) */
! 58: #define ED_P0_IMR 0x0f /* Interrupt Mask Register (write) */
! 59:
! 60: /*
! 61: * Page 1 register offsets
! 62: */
! 63: #define ED_P1_CR 0x00 /* Command Register */
! 64: #define ED_P1_PAR0 0x01 /* Physical Address Register 0 */
! 65: #define ED_P1_PAR1 0x02 /* Physical Address Register 1 */
! 66: #define ED_P1_PAR2 0x03 /* Physical Address Register 2 */
! 67: #define ED_P1_PAR3 0x04 /* Physical Address Register 3 */
! 68: #define ED_P1_PAR4 0x05 /* Physical Address Register 4 */
! 69: #define ED_P1_PAR5 0x06 /* Physical Address Register 5 */
! 70: #define ED_P1_CURR 0x07 /* Current RX ring-buffer page */
! 71: #define ED_P1_MAR0 0x08 /* Multicast Address Register 0 */
! 72: #define ED_P1_MAR1 0x09 /* Multicast Address Register 1 */
! 73: #define ED_P1_MAR2 0x0a /* Multicast Address Register 2 */
! 74: #define ED_P1_MAR3 0x0b /* Multicast Address Register 3 */
! 75: #define ED_P1_MAR4 0x0c /* Multicast Address Register 4 */
! 76: #define ED_P1_MAR5 0x0d /* Multicast Address Register 5 */
! 77: #define ED_P1_MAR6 0x0e /* Multicast Address Register 6 */
! 78: #define ED_P1_MAR7 0x0f /* Multicast Address Register 7 */
! 79:
! 80: /*
! 81: * Page 2 register offsets
! 82: */
! 83: #define ED_P2_CR 0x00 /* Command Register */
! 84: #define ED_P2_PSTART 0x01 /* Page Start (read) */
! 85: #define ED_P2_CLDA0 0x01 /* Current Local DMA Addr 0 (write) */
! 86: #define ED_P2_PSTOP 0x02 /* Page Stop (read) */
! 87: #define ED_P2_CLDA1 0x02 /* Current Local DMA Addr 1 (write) */
! 88: #define ED_P2_RNPP 0x03 /* Remote Next Packet Pointer */
! 89: #define ED_P2_TPSR 0x04 /* Transmit Page Start (read) */
! 90: #define ED_P2_LNPP 0x05 /* Local Next Packet Pointer */
! 91: #define ED_P2_ACU 0x06 /* Address Counter Upper */
! 92: #define ED_P2_ACL 0x07 /* Address Counter Lower */
! 93: #define ED_P2_RCR 0x0c /* Receive Configuration Register (read) */
! 94: #define ED_P2_TCR 0x0d /* Transmit Configuration Register (read) */
! 95: #define ED_P2_DCR 0x0e /* Data Configuration Register (read) */
! 96: #define ED_P2_IMR 0x0f /* Interrupt Mask Register (read) */
! 97:
! 98: /*
! 99: * Command Register (CR) definitions
! 100: */
! 101:
! 102: /*
! 103: * STP: SToP. Software reset command. Takes the controller offline. No
! 104: * packets will be received or transmitted. Any reception or transmission in
! 105: * progress will continue to completion before entering reset state. To exit
! 106: * this state, the STP bit must reset and the STA bit must be set. The
! 107: * software reset has executed only when indicated by the RST bit in the ISR
! 108: * being set.
! 109: */
! 110: #define ED_CR_STP 0x01
! 111:
! 112: /*
! 113: * STA: STArt. This bit is used to activate the NIC after either power-up, or
! 114: * when the NIC has been put in reset mode by software command or error.
! 115: */
! 116: #define ED_CR_STA 0x02
! 117:
! 118: /*
! 119: * TXP: Transmit Packet. This bit must be set to indicate transmission of a
! 120: * packet. TXP is internally reset either after the transmission is completed
! 121: * or aborted. This bit should be set only after the Transmit Byte Count and
! 122: * Transmit Page Start register have been programmed.
! 123: */
! 124: #define ED_CR_TXP 0x04
! 125:
! 126: /*
! 127: * RD0, RD1, RD2: Remote DMA Command. These three bits control the operation
! 128: * of the remote DMA channel. RD2 can be set to abort any remote DMA command
! 129: * in progress. The Remote Byte Count registers should be cleared when a
! 130: * remote DMA has been aborted. The Remote Start Addresses are not restored
! 131: * to the starting address if the remote DMA is aborted.
! 132: *
! 133: * RD2 RD1 RD0 function
! 134: * 0 0 0 not allowed
! 135: * 0 0 1 remote read
! 136: * 0 1 0 remote write
! 137: * 0 1 1 send packet
! 138: * 1 X X abort
! 139: */
! 140: #define ED_CR_RD0 0x08
! 141: #define ED_CR_RD1 0x10
! 142: #define ED_CR_RD2 0x20
! 143:
! 144: /*
! 145: * PS0, PS1: Page Select. The two bits select which register set or 'page' to
! 146: * access.
! 147: *
! 148: * PS1 PS0 page
! 149: * 0 0 0
! 150: * 0 1 1
! 151: * 1 0 2
! 152: * 1 1 3 (only on chips which have extensions to the dp8390)
! 153: */
! 154: #define ED_CR_PS0 0x40
! 155: #define ED_CR_PS1 0x80
! 156: /* bit encoded aliases */
! 157: #define ED_CR_PAGE_0 0x00 /* (for consistency) */
! 158: #define ED_CR_PAGE_1 (ED_CR_PS0)
! 159: #define ED_CR_PAGE_2 (ED_CR_PS1)
! 160: #define ED_CR_PAGE_3 (ED_CR_PS1|ED_CR_PS0)
! 161:
! 162: /*
! 163: * Interrupt Status Register (ISR) definitions
! 164: */
! 165:
! 166: /*
! 167: * PRX: Packet Received. Indicates packet received with no errors.
! 168: */
! 169: #define ED_ISR_PRX 0x01
! 170:
! 171: /*
! 172: * PTX: Packet Transmitted. Indicates packet transmitted with no errors.
! 173: */
! 174: #define ED_ISR_PTX 0x02
! 175:
! 176: /*
! 177: * RXE: Receive Error. Indicates that a packet was received with one or more
! 178: * the following errors: CRC error, frame alignment error, FIFO overrun,
! 179: * missed packet.
! 180: */
! 181: #define ED_ISR_RXE 0x04
! 182:
! 183: /*
! 184: * TXE: Transmission Error. Indicates that an attempt to transmit a packet
! 185: * resulted in one or more of the following errors: excessive collisions, FIFO
! 186: * underrun.
! 187: */
! 188: #define ED_ISR_TXE 0x08
! 189:
! 190: /*
! 191: * OVW: OverWrite. Indicates a receive ring-buffer overrun. Incoming network
! 192: * would exceed (has exceeded?) the boundary pointer, resulting in data that
! 193: * was previously received and not yet read from the buffer to be overwritten.
! 194: */
! 195: #define ED_ISR_OVW 0x10
! 196:
! 197: /*
! 198: * CNT: Counter Overflow. Set when the MSB of one or more of the Network Tally
! 199: * Counters has been set.
! 200: */
! 201: #define ED_ISR_CNT 0x20
! 202:
! 203: /*
! 204: * RDC: Remote Data Complete. Indicates that a Remote DMA operation has
! 205: * completed.
! 206: */
! 207: #define ED_ISR_RDC 0x40
! 208:
! 209: /*
! 210: * RST: Reset status. Set when the NIC enters the reset state and cleared when
! 211: * a Start Command is issued to the CR. This bit is also set when a receive
! 212: * ring-buffer overrun (OverWrite) occurs and is cleared when one or more
! 213: * packets have been removed from the ring. This is a read-only bit.
! 214: */
! 215: #define ED_ISR_RST 0x80
! 216:
! 217: /*
! 218: * Interrupt Mask Register (IMR) definitions
! 219: */
! 220:
! 221: /*
! 222: * PRXE: Packet Received interrupt Enable. If set, a received packet will
! 223: * cause an interrupt.
! 224: */
! 225: #define ED_IMR_PRXE 0x01
! 226:
! 227: /*
! 228: * PTXE: Packet Transmit interrupt Enable. If set, an interrupt is generated
! 229: * when a packet transmission completes.
! 230: */
! 231: #define ED_IMR_PTXE 0x02
! 232:
! 233: /*
! 234: * RXEE: Receive Error interrupt Enable. If set, an interrupt will occur
! 235: * whenever a packet is received with an error.
! 236: */
! 237: #define ED_IMR_RXEE 0x04
! 238:
! 239: /*
! 240: * TXEE: Transmit Error interrupt Enable. If set, an interrupt will occur
! 241: * whenever a transmission results in an error.
! 242: */
! 243: #define ED_IMR_TXEE 0x08
! 244:
! 245: /*
! 246: * OVWE: OverWrite error interrupt Enable. If set, an interrupt is generated
! 247: * whenever the receive ring-buffer is overrun. i.e. when the boundary pointer
! 248: * is exceeded.
! 249: */
! 250: #define ED_IMR_OVWE 0x10
! 251:
! 252: /*
! 253: * CNTE: Counter overflow interrupt Enable. If set, an interrupt is generated
! 254: * whenever the MSB of one or more of the Network Statistics counters has been
! 255: * set.
! 256: */
! 257: #define ED_IMR_CNTE 0x20
! 258:
! 259: /*
! 260: * RDCE: Remote DMA Complete interrupt Enable. If set, an interrupt is
! 261: * generated when a remote DMA transfer has completed.
! 262: */
! 263: #define ED_IMR_RDCE 0x40
! 264:
! 265: /*
! 266: * Bit 7 is unused/reserved.
! 267: */
! 268:
! 269: /*
! 270: * Data Configuration Register (DCR) definitions
! 271: */
! 272:
! 273: /*
! 274: * WTS: Word Transfer Select. WTS establishes byte or word transfers for both
! 275: * remote and local DMA transfers
! 276: */
! 277: #define ED_DCR_WTS 0x01
! 278:
! 279: /*
! 280: * BOS: Byte Order Select. BOS sets the byte order for the host. Should be 0
! 281: * for 80x86, and 1 for 68000 series processors
! 282: */
! 283: #define ED_DCR_BOS 0x02
! 284:
! 285: /*
! 286: * LAS: Long Address Select. When LAS is 1, the contents of the remote DMA
! 287: * registers RSAR0 and RSAR1 are used to provide A16-A31.
! 288: */
! 289: #define ED_DCR_LAS 0x04
! 290:
! 291: /*
! 292: * LS: Loopback Select. When 0, loopback mode is selected. Bits D1 and D2 of
! 293: * the TCR must also be programmed for loopback operation. When 1, normal
! 294: * operation is selected.
! 295: */
! 296: #define ED_DCR_LS 0x08
! 297:
! 298: /*
! 299: * AR: Auto-initialize Remote. When 0, data must be removed from ring-buffer
! 300: * under program control. When 1, remote DMA is automatically initiated and
! 301: * the boundary pointer is automatically updated.
! 302: */
! 303: #define ED_DCR_AR 0x10
! 304:
! 305: /*
! 306: * FT0, FT1: Fifo Threshold select.
! 307: *
! 308: * FT1 FT0 Word-width Byte-width
! 309: * 0 0 1 word 2 bytes
! 310: * 0 1 2 words 4 bytes
! 311: * 1 0 4 words 8 bytes
! 312: * 1 1 8 words 12 bytes
! 313: *
! 314: * During transmission, the FIFO threshold indicates the number of bytes or
! 315: * words that the FIFO has filled from the local DMA before BREQ is asserted.
! 316: * The transmission threshold is 16 bytes minus the receiver threshold.
! 317: */
! 318: #define ED_DCR_FT0 0x20
! 319: #define ED_DCR_FT1 0x40
! 320:
! 321: /*
! 322: * bit 7 (0x80) is unused/reserved
! 323: */
! 324:
! 325: /*
! 326: * Transmit Configuration Register (TCR) definitions
! 327: */
! 328:
! 329: /*
! 330: * CRC: Inhibit CRC. If 0, CRC will be appended by the transmitter, if 0, CRC
! 331: * is not appended by the transmitter.
! 332: */
! 333: #define ED_TCR_CRC 0x01
! 334:
! 335: /*
! 336: * LB0, LB1: Loopback control. These two bits set the type of loopback that is
! 337: * to be performed.
! 338: *
! 339: * LB1 LB0 mode
! 340: * 0 0 0 - normal operation (DCR_LS = 0)
! 341: * 0 1 1 - internal loopback (DCR_LS = 0)
! 342: * 1 0 2 - external loopback (DCR_LS = 1)
! 343: * 1 1 3 - external loopback (DCR_LS = 0)
! 344: */
! 345: #define ED_TCR_LB0 0x02
! 346: #define ED_TCR_LB1 0x04
! 347:
! 348: /*
! 349: * ATD: Auto Transmit Disable. Clear for normal operation. When set, allows
! 350: * another station to disable the NIC's transmitter by transmitting to a
! 351: * multicast address hashing to bit 62. Reception of a multicast address
! 352: * hashing to bit 63 enables the transmitter.
! 353: */
! 354: #define ED_TCR_ATD 0x08
! 355:
! 356: /*
! 357: * OFST: Collision Offset enable. This bit when set modifies the backoff
! 358: * algorithm to allow prioritization of nodes.
! 359: */
! 360: #define ED_TCR_OFST 0x10
! 361:
! 362: /*
! 363: * bits 5, 6, and 7 are unused/reserved
! 364: */
! 365:
! 366: /*
! 367: * Transmit Status Register (TSR) definitions
! 368: */
! 369:
! 370: /*
! 371: * PTX: Packet Transmitted. Indicates successful transmission of packet.
! 372: */
! 373: #define ED_TSR_PTX 0x01
! 374:
! 375: /*
! 376: * bit 1 (0x02) is unused/reserved
! 377: */
! 378:
! 379: /*
! 380: * COL: Transmit Collided. Indicates that the transmission collided at least
! 381: * once with another station on the network.
! 382: */
! 383: #define ED_TSR_COL 0x04
! 384:
! 385: /*
! 386: * ABT: Transmit aborted. Indicates that the transmission was aborted due to
! 387: * excessive collisions.
! 388: */
! 389: #define ED_TSR_ABT 0x08
! 390:
! 391: /*
! 392: * CRS: Carrier Sense Lost. Indicates that carrier was lost during the
! 393: * transmission of the packet. (Transmission is not aborted because of a loss
! 394: * of carrier).
! 395: */
! 396: #define ED_TSR_CRS 0x10
! 397:
! 398: /*
! 399: * FU: FIFO Underrun. Indicates that the NIC wasn't able to access bus/
! 400: * transmission memory before the FIFO emptied. Transmission of the packet was
! 401: * aborted.
! 402: */
! 403: #define ED_TSR_FU 0x20
! 404:
! 405: /*
! 406: * CDH: CD Heartbeat. Indicates that the collision detection circuitry isn't
! 407: * working correctly during a collision heartbeat test.
! 408: */
! 409: #define ED_TSR_CDH 0x40
! 410:
! 411: /*
! 412: * OWC: Out of Window Collision: Indicates that a collision occurred after a
! 413: * slot time (51.2us). The transmission is rescheduled just as in normal
! 414: * collisions.
! 415: */
! 416: #define ED_TSR_OWC 0x80
! 417:
! 418: /*
! 419: * Receiver Configuration Register (RCR) definitions
! 420: */
! 421:
! 422: /*
! 423: * SEP: Save Errored Packets. If 0, error packets are discarded. If set to 1,
! 424: * packets with CRC and frame errors are not discarded.
! 425: */
! 426: #define ED_RCR_SEP 0x01
! 427:
! 428: /*
! 429: * AR: Accept Runt packet. If 0, packet with less than 64 byte are discarded.
! 430: * If set to 1, packets with less than 64 byte are not discarded.
! 431: */
! 432: #define ED_RCR_AR 0x02
! 433:
! 434: /*
! 435: * AB: Accept Broadcast. If set, packets sent to the broadcast address will be
! 436: * accepted.
! 437: */
! 438: #define ED_RCR_AB 0x04
! 439:
! 440: /*
! 441: * AM: Accept Multicast. If set, packets sent to a multicast address are
! 442: * checked for a match in the hashing array. If clear, multicast packets are
! 443: * ignored.
! 444: */
! 445: #define ED_RCR_AM 0x08
! 446:
! 447: /*
! 448: * PRO: Promiscuous Physical. If set, all packets with a physical addresses
! 449: * are accepted. If clear, a physical destination address must match this
! 450: * station's address. Note: for full promiscuous mode, RCR_AB and RCR_AM must
! 451: * also be set. In addition, the multicast hashing array must be set to all
! 452: * 1's so that all multicast addresses are accepted.
! 453: */
! 454: #define ED_RCR_PRO 0x10
! 455:
! 456: /*
! 457: * MON: Monitor Mode. If set, packets will be checked for good CRC and
! 458: * framing, but are not stored in the ring-buffer. If clear, packets are
! 459: * stored (normal operation).
! 460: */
! 461: #define ED_RCR_MON 0x20
! 462:
! 463: /*
! 464: * INTT: Interrupt Trigger Mode. Must be set if AX88190.
! 465: */
! 466: #define ED_RCR_INTT 0x40
! 467:
! 468: /*
! 469: * Bit 7 is unused/reserved.
! 470: */
! 471:
! 472: /*
! 473: * Receiver Status Register (RSR) definitions
! 474: */
! 475:
! 476: /*
! 477: * PRX: Packet Received without error.
! 478: */
! 479: #define ED_RSR_PRX 0x01
! 480:
! 481: /*
! 482: * CRC: CRC error. Indicates that a packet has a CRC error. Also set for
! 483: * frame alignment errors.
! 484: */
! 485: #define ED_RSR_CRC 0x02
! 486:
! 487: /*
! 488: * FAE: Frame Alignment Error. Indicates that the incoming packet did not end
! 489: * on a byte boundary and the CRC did not match at the last byte boundary.
! 490: */
! 491: #define ED_RSR_FAE 0x04
! 492:
! 493: /*
! 494: * FO: FIFO Overrun. Indicates that the FIFO was not serviced (during local
! 495: * DMA) causing it to overrun. Reception of the packet is aborted.
! 496: */
! 497: #define ED_RSR_FO 0x08
! 498:
! 499: /*
! 500: * MPA: Missed Packet. Indicates that the received packet couldn't be stored
! 501: * in the ring-buffer because of insufficient buffer space (exceeding the
! 502: * boundary pointer), or because the transfer to the ring-buffer was inhibited
! 503: * by RCR_MON - monitor mode.
! 504: */
! 505: #define ED_RSR_MPA 0x10
! 506:
! 507: /*
! 508: * PHY: Physical address. If 0, the packet received was sent to a physical
! 509: * address. If 1, the packet was accepted because of a multicast/broadcast
! 510: * address match.
! 511: */
! 512: #define ED_RSR_PHY 0x20
! 513:
! 514: /*
! 515: * DIS: Receiver Disabled. Set to indicate that the receiver has entered
! 516: * monitor mode. Cleared when the receiver exits monitor mode.
! 517: */
! 518: #define ED_RSR_DIS 0x40
! 519:
! 520: /*
! 521: * DFR: Deferring. Set to indicate a 'jabber' condition. The CRS and COL
! 522: * inputs are active, and the transceiver has set the CD line as a result of
! 523: * the jabber.
! 524: */
! 525: #define ED_RSR_DFR 0x80
! 526:
! 527: /*
! 528: * receive ring descriptor
! 529: *
! 530: * The National Semiconductor DS8390 Network interface controller uses the
! 531: * following receive ring headers. The way this works is that the memory on
! 532: * the interface card is chopped up into 256 bytes blocks. A contiguous
! 533: * portion of those blocks are marked for receive packets by setting start and
! 534: * end block #'s in the NIC. For each packet that is put into the receive
! 535: * ring, one of these headers (4 bytes each) is tacked onto the front. The
! 536: * first byte is a copy of the receiver status register at the time the packet
! 537: * was received.
! 538: */
! 539: struct dp8390_ring {
! 540: u_int8_t rsr; /* receiver status */
! 541: u_int8_t next_packet; /* pointer to next packet */
! 542: u_int16_t count; /* bytes in packet (length + 4) */
! 543: };
! 544:
! 545: /* Some drivers prefer to use byte-constants to get at this structure. */
! 546: #define ED_RING_RSR 0 /* receiver status */
! 547: #define ED_RING_NEXT_PACKET 1 /* pointer to next packet */
! 548: #define ED_RING_COUNT 2 /* bytes in packet (length + 4) */
! 549: #define ED_RING_HDRSZ 4 /* Header size */
! 550:
! 551: /*
! 552: * Common constants
! 553: */
! 554: #define ED_PAGE_SIZE 256 /* Size of RAM pages in bytes */
! 555: #define ED_PAGE_MASK 255
! 556: #define ED_PAGE_SHIFT 8
! 557:
! 558: #define ED_TXBUF_SIZE 6 /* Size of TX buffer in pages */
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