Annotation of sys/dev/ic/dcreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: dcreg.h,v 1.42 2005/05/22 03:47:16 martin Exp $ */
2:
3: /*
4: * Copyright (c) 1997, 1998, 1999
5: * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: * 3. All advertising materials mentioning features or use of this software
16: * must display the following acknowledgement:
17: * This product includes software developed by Bill Paul.
18: * 4. Neither the name of the author nor the names of any co-contributors
19: * may be used to endorse or promote products derived from this software
20: * without specific prior written permission.
21: *
22: * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25: * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32: * THE POSSIBILITY OF SUCH DAMAGE.
33: *
34: * $FreeBSD: src/sys/pci/if_dcreg.h,v 1.12 2000/10/05 17:36:14 wpaul Exp $
35: */
36:
37: /*
38: * 21143 and clone common register definitions.
39: */
40:
41: #ifdef __alpha__
42: #define SRM_MEDIA
43: #endif
44:
45: #define DC_BUSCTL 0x00 /* bus control */
46: #define DC_TXSTART 0x08 /* tx start demand */
47: #define DC_RXSTART 0x10 /* rx start demand */
48: #define DC_RXADDR 0x18 /* rx descriptor list start addr */
49: #define DC_TXADDR 0x20 /* tx descriptor list start addr */
50: #define DC_ISR 0x28 /* interrupt status register */
51: #define DC_NETCFG 0x30 /* network config register */
52: #define DC_IMR 0x38 /* interrupt mask */
53: #define DC_FRAMESDISCARDED 0x40 /* # of discarded frames */
54: #define DC_SIO 0x48 /* MII and ROM/EEPROM access */
55: #define DC_ROM 0x50 /* ROM programming address */
56: #define DC_TIMER 0x58 /* general timer */
57: #define DC_10BTSTAT 0x60 /* SIA status */
58: #define DC_SIARESET 0x68 /* SIA connectivity */
59: #define DC_10BTCTRL 0x70 /* SIA transmit and receive */
60: #define DC_WATCHDOG 0x78 /* SIA and general purpose port */
61: #define DC_SIAGP 0x78 /* SIA and general purpose port (X3201) */
62:
63: /*
64: * There are two general 'types' of MX chips that we need to be
65: * concerned with. One is the original 98713, which has its internal
66: * NWAY support controlled via the MDIO bits in the serial I/O
67: * register. The other is everything else (from the 98713A on up),
68: * which has its internal NWAY controlled via CSR13, CSR14 and CSR15,
69: * just like the 21143. This type setting also governs which of the
70: * 'magic' numbers we write to CSR16. The PNIC II falls into the
71: * 98713A/98715/98715A/98725 category.
72: */
73: #define DC_TYPE_98713 0x1
74: #define DC_TYPE_98713A 0x2
75: #define DC_TYPE_987x5 0x3
76:
77: /* Other type of supported chips. */
78: #define DC_TYPE_21143 0x4 /* Intel 21143 */
79: #define DC_TYPE_ASIX 0x5 /* ASIX AX88140A/AX88141 */
80: #define DC_TYPE_AL981 0x6 /* ADMtek AL981 Comet */
81: #define DC_TYPE_AN983 0x7 /* ADMtek AN983 Centaur */
82: #define DC_TYPE_DM9102 0x8 /* Davicom DM9102 */
83: #define DC_TYPE_PNICII 0x9 /* 82c115 PNIC II */
84: #define DC_TYPE_PNIC 0xA /* 82c168/82c169 PNIC I */
85: #define DC_TYPE_XIRCOM 0xB /* Xircom X3201 */
86: #define DC_TYPE_CONEXANT 0xC /* Conexant LANfinity RS7112 */
87: #define DC_TYPE_21145 0xD /* Intel 21145 */
88:
89: #define DC_IS_MACRONIX(x) \
90: (x->dc_type == DC_TYPE_98713 || \
91: x->dc_type == DC_TYPE_98713A || \
92: x->dc_type == DC_TYPE_987x5)
93:
94: #define DC_IS_ADMTEK(x) \
95: (x->dc_type == DC_TYPE_AL981 || \
96: x->dc_type == DC_TYPE_AN983)
97:
98: #define DC_IS_CENTAUR(x) \
99: (x->dc_type == DC_TYPE_AN983)
100:
101: #define DC_IS_INTEL(x) \
102: (x->dc_type == DC_TYPE_21143 || \
103: x->dc_type == DC_TYPE_21145)
104:
105: #define DC_IS_ASIX(x) (x->dc_type == DC_TYPE_ASIX)
106: #define DC_IS_COMET(x) (x->dc_type == DC_TYPE_AL981)
107: #define DC_IS_CENTAUR(x) (x->dc_type == DC_TYPE_AN983)
108: #define DC_IS_DAVICOM(x) (x->dc_type == DC_TYPE_DM9102)
109: #define DC_IS_PNICII(x) (x->dc_type == DC_TYPE_PNICII)
110: #define DC_IS_PNIC(x) (x->dc_type == DC_TYPE_PNIC)
111: #define DC_IS_XIRCOM(x) (x->dc_type == DC_TYPE_XIRCOM)
112: #define DC_IS_CONEXANT(x) (x->dc_type == DC_TYPE_CONEXANT)
113:
114: /* MII/symbol mode port types */
115: #define DC_PMODE_MII 0x1
116: #define DC_PMODE_SYM 0x2
117: #define DC_PMODE_SIA 0x3
118:
119: /*
120: * Bus control bits.
121: */
122: #define DC_BUSCTL_RESET 0x00000001
123: #define DC_BUSCTL_ARBITRATION 0x00000002
124: #define DC_BUSCTL_SKIPLEN 0x0000007C
125: #define DC_BUSCTL_BUF_BIGENDIAN 0x00000080
126: #define DC_BUSCTL_BURSTLEN 0x00003F00
127: #define DC_BUSCTL_CACHEALIGN 0x0000C000
128: #define DC_BUSCTL_TXPOLL 0x000E0000
129: #define DC_BUSCTL_DBO 0x00100000
130: #define DC_BUSCTL_MRME 0x00200000
131: #define DC_BUSCTL_MRLE 0x00800000
132: #define DC_BUSCTL_MWIE 0x01000000
133: #define DC_BUSCTL_ONNOW_ENB 0x04000000
134:
135: #define DC_SKIPLEN_1LONG 0x00000004
136: #define DC_SKIPLEN_2LONG 0x00000008
137: #define DC_SKIPLEN_3LONG 0x00000010
138: #define DC_SKIPLEN_4LONG 0x00000020
139: #define DC_SKIPLEN_5LONG 0x00000040
140:
141: #define DC_CACHEALIGN_NONE 0x00000000
142: #define DC_CACHEALIGN_8LONG 0x00004000
143: #define DC_CACHEALIGN_16LONG 0x00008000
144: #define DC_CACHEALIGN_32LONG 0x0000C000
145:
146: #define DC_BURSTLEN_USECA 0x00000000
147: #define DC_BURSTLEN_1LONG 0x00000100
148: #define DC_BURSTLEN_2LONG 0x00000200
149: #define DC_BURSTLEN_4LONG 0x00000400
150: #define DC_BURSTLEN_8LONG 0x00000800
151: #define DC_BURSTLEN_16LONG 0x00001000
152: #define DC_BURSTLEN_32LONG 0x00002000
153:
154: #define DC_TXPOLL_OFF 0x00000000
155: #define DC_TXPOLL_1 0x00020000
156: #define DC_TXPOLL_2 0x00040000
157: #define DC_TXPOLL_3 0x00060000
158: #define DC_TXPOLL_4 0x00080000
159: #define DC_TXPOLL_5 0x000A0000
160: #define DC_TXPOLL_6 0x000C0000
161: #define DC_TXPOLL_7 0x000E0000
162:
163: /*
164: * Interrupt status bits.
165: */
166: #define DC_ISR_TX_OK 0x00000001
167: #define DC_ISR_TX_IDLE 0x00000002
168: #define DC_ISR_TX_NOBUF 0x00000004
169: #define DC_ISR_TX_JABBERTIMEO 0x00000008
170: #define DC_ISR_LINKGOOD 0x00000010
171: #define DC_ISR_TX_UNDERRUN 0x00000020
172: #define DC_ISR_RX_OK 0x00000040
173: #define DC_ISR_RX_NOBUF 0x00000080
174: #define DC_ISR_RX_READ 0x00000100
175: #define DC_ISR_RX_WATDOGTIMEO 0x00000200
176: #define DC_ISR_TX_EARLY 0x00000400
177: #define DC_ISR_TIMER_EXPIRED 0x00000800
178: #define DC_ISR_LINKFAIL 0x00001000
179: #define DC_ISR_BUS_ERR 0x00002000
180: #define DC_ISR_RX_EARLY 0x00004000
181: #define DC_ISR_ABNORMAL 0x00008000
182: #define DC_ISR_NORMAL 0x00010000
183: #define DC_ISR_RX_STATE 0x000E0000
184: #define DC_ISR_TX_STATE 0x00700000
185: #define DC_ISR_BUSERRTYPE 0x03800000
186: #define DC_ISR_100MBPSLINK 0x08000000
187: #define DC_ISR_MAGICKPACK 0x10000000
188:
189: #define DC_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */
190: #define DC_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */
191: #define DC_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */
192: #define DC_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */
193: #define DC_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */
194: #define DC_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */
195: #define DC_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */
196: #define DC_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */
197:
198: #define DC_TXSTATE_RESET 0x00000000 /* 000 - reset */
199: #define DC_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */
200: #define DC_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */
201: #define DC_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */
202: #define DC_TXSTATE_RSVD 0x00400000 /* 100 - reserved */
203: #define DC_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */
204: #define DC_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */
205: #define DC_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */
206:
207: /*
208: * Network config bits.
209: */
210: #define DC_NETCFG_RX_HASHPERF 0x00000001
211: #define DC_NETCFG_RX_ON 0x00000002
212: #define DC_NETCFG_RX_HASHONLY 0x00000004
213: #define DC_NETCFG_RX_BADFRAMES 0x00000008
214: #define DC_NETCFG_RX_INVFILT 0x00000010
215: #define DC_NETCFG_BACKOFFCNT 0x00000020
216: #define DC_NETCFG_RX_PROMISC 0x00000040
217: #define DC_NETCFG_RX_ALLMULTI 0x00000080
218: #define DC_NETCFG_FULLDUPLEX 0x00000200
219: #define DC_NETCFG_LOOPBACK 0x00000C00
220: #define DC_NETCFG_FORCECOLL 0x00001000
221: #define DC_NETCFG_TX_ON 0x00002000
222: #define DC_NETCFG_TX_THRESH 0x0000C000
223: #define DC_NETCFG_TX_BACKOFF 0x00020000
224: #define DC_NETCFG_PORTSEL 0x00040000 /* 0 == 10, 1 == 100 */
225: #define DC_NETCFG_HEARTBEAT 0x00080000
226: #define DC_NETCFG_STORENFWD 0x00200000
227: #define DC_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */
228: #define DC_NETCFG_PCS 0x00800000
229: #define DC_NETCFG_SCRAMBLER 0x01000000
230: #define DC_NETCFG_NO_RXCRC 0x02000000
231: #define DC_NETCFG_RX_ALL 0x40000000
232: #define DC_NETCFG_CAPEFFECT 0x80000000
233:
234: #define DC_OPMODE_NORM 0x00000000
235: #define DC_OPMODE_INTLOOP 0x00000400
236: #define DC_OPMODE_EXTLOOP 0x00000800
237:
238: #if 0
239: #define DC_TXTHRESH_72BYTES 0x00000000
240: #define DC_TXTHRESH_96BYTES 0x00004000
241: #define DC_TXTHRESH_128BYTES 0x00008000
242: #define DC_TXTHRESH_160BYTES 0x0000C000
243: #endif
244:
245: #define DC_TXTHRESH_MIN 0x00000000
246: #define DC_TXTHRESH_INC 0x00004000
247: #define DC_TXTHRESH_MAX 0x0000C000
248:
249: /*
250: * Interrupt mask bits.
251: */
252: #define DC_IMR_TX_OK 0x00000001
253: #define DC_IMR_TX_IDLE 0x00000002
254: #define DC_IMR_TX_NOBUF 0x00000004
255: #define DC_IMR_TX_JABBERTIMEO 0x00000008
256: #define DC_IMR_LINKGOOD 0x00000010
257: #define DC_IMR_TX_UNDERRUN 0x00000020
258: #define DC_IMR_RX_OK 0x00000040
259: #define DC_IMR_RX_NOBUF 0x00000080
260: #define DC_IMR_RX_READ 0x00000100
261: #define DC_IMR_RX_WATDOGTIMEO 0x00000200
262: #define DC_IMR_TX_EARLY 0x00000400
263: #define DC_IMR_TIMER_EXPIRED 0x00000800
264: #define DC_IMR_LINKFAIL 0x00001000
265: #define DC_IMR_BUS_ERR 0x00002000
266: #define DC_IMR_RX_EARLY 0x00004000
267: #define DC_IMR_ABNORMAL 0x00008000
268: #define DC_IMR_NORMAL 0x00010000
269: #define DC_IMR_100MBPSLINK 0x08000000
270: #define DC_IMR_MAGICKPACK 0x10000000
271:
272: #define DC_INTRS \
273: (DC_IMR_RX_OK|DC_IMR_TX_OK|DC_IMR_RX_NOBUF|DC_IMR_RX_WATDOGTIMEO|\
274: DC_IMR_TX_IDLE|DC_IMR_TX_NOBUF|DC_IMR_TX_UNDERRUN|DC_IMR_BUS_ERR|\
275: DC_IMR_ABNORMAL|DC_IMR_NORMAL/*|DC_IMR_TX_EARLY*/)
276: /*
277: * Serial I/O (EEPROM/ROM) bits.
278: */
279: #define DC_SIO_EE_CS 0x00000001 /* EEPROM chip select */
280: #define DC_SIO_EE_CLK 0x00000002 /* EEPROM clock */
281: #define DC_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */
282: #define DC_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */
283: #define DC_SIO_ROMDATA4 0x00000010
284: #define DC_SIO_ROMDATA5 0x00000020
285: #define DC_SIO_ROMDATA6 0x00000040
286: #define DC_SIO_ROMDATA7 0x00000080
287: #define DC_SIO_EESEL 0x00000800
288: #define DC_SIO_ROMSEL 0x00001000
289: #define DC_SIO_ROMCTL_WRITE 0x00002000
290: #define DC_SIO_ROMCTL_READ 0x00004000
291: #define DC_SIO_MII_CLK 0x00010000 /* MDIO clock */
292: #define DC_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */
293: #define DC_SIO_MII_DIR 0x00040000 /* MDIO dir */
294: #define DC_SIO_MII_DATAIN 0x00080000 /* MDIO data in */
295:
296: #define DC_EECMD_WRITE 0x140
297: #define DC_EECMD_READ 0x180
298: #define DC_EECMD_ERASE 0x1c0
299:
300: #define DC_EE_NODEADDR_OFFSET 0x70
301: #define DC_EE_NODEADDR 10
302:
303: /*
304: * General purpose timer register
305: * (upper 15 bits exist on rev 0x41 chips only)
306: */
307: #define DC_TIMER_CLKDIV 0x80000000 /* clock/16 */
308: #define DC_TIMER_TXTIMER 0x78000000 /* TX intr delay timer */
309: #define DC_TIMER_TXCOUNT 0x07000000 /* TX intr delay counter */
310: #define DC_TIMER_RXTIMER 0x00F00000 /* RX intr delay timer */
311: #define DC_TIMER_RXCOUNT 0x000E0000 /* RX intr delay counter */
312: #define DC_TIMER_CONTINUOUS 0x00010000
313: #define DC_TIMER_VALUE 0x0000FFFF /* 81.92us */
314:
315: /*
316: * 10baseT status register
317: */
318: #define DC_TSTAT_MIIACT 0x00000001 /* MII port activity */
319: #define DC_TSTAT_LS100 0x00000002 /* link status of 100baseTX */
320: #define DC_TSTAT_LS10 0x00000004 /* link status of 10baseT */
321: #define DC_TSTAT_AUTOPOLARITY 0x00000008
322: #define DC_TSTAT_AUIACT 0x00000100 /* AUI activity */
323: #define DC_TSTAT_10BTACT 0x00000200 /* 10baseT activity */
324: #define DC_TSTAT_NSN 0x00000400 /* non-stable FLPs detected */
325: #define DC_TSTAT_REMFAULT 0x00000800
326: #define DC_TSTAT_ANEGSTAT 0x00007000
327: #define DC_TSTAT_LP_CAN_NWAY 0x00008000 /* link partner supports NWAY */
328: #define DC_TSTAT_LPCODEWORD 0xFFFF0000 /* link partner's code word */
329:
330: #define DC_ASTAT_DISABLE 0x00000000
331: #define DC_ASTAT_TXDISABLE 0x00001000
332: #define DC_ASTAT_ABDETECT 0x00002000
333: #define DC_ASTAT_ACKDETECT 0x00003000
334: #define DC_ASTAT_CMPACKDETECT 0x00004000
335: #define DC_ASTAT_AUTONEGCMP 0x00005000
336: #define DC_ASTAT_LINKCHECK 0x00006000
337:
338: /*
339: * PHY reset register
340: */
341: #define DC_SIA_RESET 0x00000001
342: #define DC_SIA_AUI 0x00000008 /* AUI or 10baseT */
343:
344: /*
345: * 10baseT control register
346: */
347: #define DC_TCTL_ENCODER_ENB 0x00000001
348: #define DC_TCTL_LOOPBACK 0x00000002
349: #define DC_TCTL_DRIVER_ENB 0x00000004
350: #define DC_TCTL_LNKPULSE_ENB 0x00000008
351: #define DC_TCTL_HALFDUPLEX 0x00000040
352: #define DC_TCTL_AUTONEGENBL 0x00000080
353: #define DC_TCTL_RX_SQUELCH 0x00000100
354: #define DC_TCTL_COLL_SQUELCH 0x00000200
355: #define DC_TCTL_COLL_DETECT 0x00000400
356: #define DC_TCTL_SQE_ENB 0x00000800
357: #define DC_TCTL_LINKTEST 0x00001000
358: #define DC_TCTL_AUTOPOLARITY 0x00002000
359: #define DC_TCTL_SET_POL_PLUS 0x00004000
360: #define DC_TCTL_AUTOSENSE 0x00008000 /* 10bt/AUI autosense */
361: #define DC_TCTL_100BTXHALF 0x00010000
362: #define DC_TCTL_100BTXFULL 0x00020000
363: #define DC_TCTL_100BT4 0x00040000
364:
365: /*
366: * Watchdog timer register
367: */
368: #define DC_WDOG_JABBERDIS 0x00000001
369: #define DC_WDOG_HOSTUNJAB 0x00000002
370: #define DC_WDOG_JABBERCLK 0x00000004
371: #define DC_WDOG_RXWDOGDIS 0x00000010
372: #define DC_WDOG_RXWDOGCLK 0x00000020
373: #define DC_WDOG_MUSTBEZERO 0x00000100
374: #define DC_WDOG_AUIBNC 0x00100000
375: #define DC_WDOG_ACTIVITY 0x00200000
376: #define DC_WDOG_LINK 0x00800000
377: #define DC_WDOG_CTLWREN 0x08000000
378:
379: /*
380: * SIA and General Purpose Port register (X3201)
381: */
382: #define DC_SIAGP_RXMATCH 0x40000000
383: #define DC_SIAGP_INT1 0x20000000
384: #define DC_SIAGP_INT0 0x10000000
385: #define DC_SIAGP_WRITE_EN 0x08000000
386: #define DC_SIAGP_RXMATCH_EN 0x04000000
387: #define DC_SIAGP_INT1_EN 0x02000000
388: #define DC_SIAGP_INT0_EN 0x01000000
389: #define DC_SIAGP_LED3 0x00800000
390: #define DC_SIAGP_LED2 0x00400000
391: #define DC_SIAGP_LED1 0x00200000
392: #define DC_SIAGP_LED0 0x00100000
393: #define DC_SIAGP_MD_GP3_OUTPUT 0x00080000
394: #define DC_SIAGP_MD_GP2_OUTPUT 0x00040000
395: #define DC_SIAGP_MD_GP1_OUTPUT 0x00020000
396: #define DC_SIAGP_MD_GP0_OUTPUT 0x00010000
397:
398: /*
399: * Size of a setup frame.
400: */
401: #define DC_SFRAME_LEN 192
402:
403: /*
404: * 21x4x TX/RX list structure.
405: */
406:
407: struct dc_desc {
408: u_int32_t dc_status;
409: u_int32_t dc_ctl;
410: u_int32_t dc_ptr1;
411: u_int32_t dc_ptr2;
412: u_int32_t dc_pad[4];
413: };
414:
415: #define dc_data dc_ptr1
416: #define dc_next dc_ptr2
417:
418: #define DC_RXSTAT_FIFOOFLOW 0x00000001
419: #define DC_RXSTAT_CRCERR 0x00000002
420: #define DC_RXSTAT_DRIBBLE 0x00000004
421: #define DC_RXSTAT_MIIERE 0x00000008
422: #define DC_RXSTAT_WATCHDOG 0x00000010
423: #define DC_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */
424: #define DC_RXSTAT_COLLSEEN 0x00000040
425: #define DC_RXSTAT_GIANT 0x00000080
426: #define DC_RXSTAT_LASTFRAG 0x00000100
427: #define DC_RXSTAT_FIRSTFRAG 0x00000200
428: #define DC_RXSTAT_MULTICAST 0x00000400
429: #define DC_RXSTAT_RUNT 0x00000800
430: #define DC_RXSTAT_RXTYPE 0x00003000
431: #define DC_RXSTAT_DE 0x00004000
432: #define DC_RXSTAT_RXERR 0x00008000
433: #define DC_RXSTAT_RXLEN 0x3FFF0000
434: #define DC_RXSTAT_OWN 0x80000000
435:
436: #define DC_RXBYTES(x) ((x & DC_RXSTAT_RXLEN) >> 16)
437: #define DC_RXSTAT (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG|DC_RXSTAT_OWN)
438:
439: #define DC_RXCTL_BUFLEN1 0x00000FFF
440: #define DC_RXCTL_BUFLEN2 0x00FFF000
441: #define DC_RXCTL_RLINK 0x01000000
442: #define DC_RXCTL_RLAST 0x02000000
443:
444: #define DC_TXSTAT_DEFER 0x00000001
445: #define DC_TXSTAT_UNDERRUN 0x00000002
446: #define DC_TXSTAT_LINKFAIL 0x00000003
447: #define DC_TXSTAT_COLLCNT 0x00000078
448: #define DC_TXSTAT_SQE 0x00000080
449: #define DC_TXSTAT_EXCESSCOLL 0x00000100
450: #define DC_TXSTAT_LATECOLL 0x00000200
451: #define DC_TXSTAT_NOCARRIER 0x00000400
452: #define DC_TXSTAT_CARRLOST 0x00000800
453: #define DC_TXSTAT_JABTIMEO 0x00004000
454: #define DC_TXSTAT_ERRSUM 0x00008000
455: #define DC_TXSTAT_OWN 0x80000000
456:
457: #define DC_TXCTL_BUFLEN1 0x000007FF
458: #define DC_TXCTL_BUFLEN2 0x003FF800
459: #define DC_TXCTL_FILTTYPE0 0x00400000
460: #define DC_TXCTL_PAD 0x00800000
461: #define DC_TXCTL_TLINK 0x01000000
462: #define DC_TXCTL_TLAST 0x02000000
463: #define DC_TXCTL_NOCRC 0x04000000
464: #define DC_TXCTL_SETUP 0x08000000
465: #define DC_TXCTL_FILTTYPE1 0x10000000
466: #define DC_TXCTL_FIRSTFRAG 0x20000000
467: #define DC_TXCTL_LASTFRAG 0x40000000
468: #define DC_TXCTL_FINT 0x80000000
469:
470: #define DC_FILTER_PERFECT 0x00000000
471: #define DC_FILTER_HASHPERF 0x00400000
472: #define DC_FILTER_INVERSE 0x10000000
473: #define DC_FILTER_HASHONLY 0x10400000
474:
475: #define DC_MAXFRAGS 16
476: #define DC_RX_LIST_CNT 64
477: #define DC_TX_LIST_CNT 256
478:
479: #define DC_INC(x, y) (x) = (x + 1) % y
480:
481: struct dc_list_data {
482: struct dc_desc dc_rx_list[DC_RX_LIST_CNT];
483: struct dc_desc dc_tx_list[DC_TX_LIST_CNT];
484: u_int32_t dc_sbuf[DC_SFRAME_LEN/sizeof(u_int32_t)];
485: u_int8_t dc_pad[ETHER_MIN_LEN];
486: };
487:
488: /* software descriptor */
489: struct dc_swdesc {
490: bus_dmamap_t sd_map;
491: struct mbuf *sd_mbuf;
492: };
493:
494: struct dc_chain_data {
495: struct dc_swdesc dc_rx_chain[DC_RX_LIST_CNT];
496: struct dc_swdesc dc_tx_chain[DC_TX_LIST_CNT];
497: int dc_tx_prod;
498: int dc_tx_cons;
499: int dc_tx_cnt;
500: int dc_rx_prod;
501: };
502:
503: struct dc_mediainfo {
504: int dc_media;
505: u_int8_t *dc_gp_ptr;
506: u_int8_t dc_gp_len;
507: u_int8_t *dc_reset_ptr;
508: u_int8_t dc_reset_len;
509: struct dc_mediainfo *dc_next;
510: };
511:
512: struct dc_type {
513: u_int16_t dc_vid;
514: u_int16_t dc_did;
515: };
516:
517: struct dc_mii_frame {
518: u_int8_t mii_stdelim;
519: u_int8_t mii_opcode;
520: u_int8_t mii_phyaddr;
521: u_int8_t mii_regaddr;
522: u_int8_t mii_turnaround;
523: u_int16_t mii_data;
524: };
525:
526: /*
527: * MII constants
528: */
529: #define DC_MII_STARTDELIM 0x01
530: #define DC_MII_READOP 0x02
531: #define DC_MII_WRITEOP 0x01
532: #define DC_MII_TURNAROUND 0x02
533:
534:
535: /*
536: * Registers specific to clone devices.
537: * This mainly relates to RX filter programming: not all 21x4x clones
538: * use the standard DEC filter programming mechanism.
539: */
540:
541: /*
542: * ADMtek specific registers and constants for the AL981 and AN983.
543: * The AN983 doesn't use the magic PHY registers.
544: */
545: #define DC_AL_CR 0x88 /* Command register */
546: #define DC_AL_PAR0 0xA4 /* station address */
547: #define DC_AL_PAR1 0xA8 /* station address */
548: #define DC_AL_MAR0 0xAC /* multicast hash filter */
549: #define DC_AL_MAR1 0xB0 /* multicast hash filter */
550: #define DC_AL_BMCR 0xB4 /* built in PHY control */
551: #define DC_AL_BMSR 0xB8 /* built in PHY status */
552: #define DC_AL_VENID 0xBC /* built in PHY ID0 */
553: #define DC_AL_DEVID 0xC0 /* built in PHY ID1 */
554: #define DC_AL_ANAR 0xC4 /* built in PHY autoneg advert */
555: #define DC_AL_LPAR 0xC8 /* bnilt in PHY link part. ability */
556: #define DC_AL_ANER 0xCC /* built in PHY autoneg expansion */
557:
558: #define DC_ADMTEK_PHYADDR 0x1
559: #define DC_AL_EE_NODEADDR 8
560: #define DC_AL_CR_ATUR 0x00000001 /* Enable automatic TX underrun recovery */
561: /* End of ADMtek specific registers */
562:
563: /*
564: * ASIX specific registers.
565: */
566: #define DC_AX_FILTIDX 0x68 /* RX filter index */
567: #define DC_AX_FILTDATA 0x70 /* RX filter data */
568:
569: /*
570: * Special ASIX-specific bits in the ASIX NETCFG register (CSR6).
571: */
572: #define DC_AX_NETCFG_RX_BROAD 0x00000100
573:
574: /*
575: * RX Filter Index Register values
576: */
577: #define DC_AX_FILTIDX_PAR0 0x00000000
578: #define DC_AX_FILTIDX_PAR1 0x00000001
579: #define DC_AX_FILTIDX_MAR0 0x00000002
580: #define DC_AX_FILTIDX_MAR1 0x00000003
581: /* End of ASIX specific registers */
582:
583: /*
584: * Macronix specific registers. The Macronix chips have a special
585: * register for reading the NWAY status, which we don't use, plus
586: * a magic packet register, which we need to tweak a bit per the
587: * Macronix application notes.
588: */
589: #define DC_MX_MAGICPACKET 0x80
590: #define DC_MX_NWAYSTAT 0xA0
591:
592: /*
593: * Magic packet register
594: */
595: #define DC_MX_MPACK_DISABLE 0x00400000
596:
597: /*
598: * NWAY status register.
599: */
600: #define DC_MX_NWAY_10BTHALF 0x08000000
601: #define DC_MX_NWAY_10BTFULL 0x10000000
602: #define DC_MX_NWAY_100BTHALF 0x20000000
603: #define DC_MX_NWAY_100BTFULL 0x40000000
604: #define DC_MX_NWAY_100BT4 0x80000000
605:
606: /*
607: * These are magic values that must be written into CSR16
608: * (DC_MX_MAGICPACKET) in order to put the chip into proper
609: * operating mode. The magic numbers are documented in the
610: * Macronix 98715 application notes.
611: */
612: #define DC_MX_MAGIC_98713 0x0F370000
613: #define DC_MX_MAGIC_98713A 0x0B3C0000
614: #define DC_MX_MAGIC_98715 0x0B3C0000
615: #define DC_MX_MAGIC_98725 0x0B3C0000
616: /* End of Macronix specific registers */
617:
618: /*
619: * PNIC 82c168/82c169 specific registers.
620: * The PNIC has its own special NWAY support, which doesn't work,
621: * and shortcut ways of reading the EEPROM and MII bus.
622: */
623: #define DC_PN_GPIO 0x60 /* general purpose pins control */
624: #define DC_PN_PWRUP_CFG 0x90 /* config register, set by EEPROM */
625: #define DC_PN_SIOCTL 0x98 /* serial EEPROM control register */
626: #define DC_PN_MII 0xA0 /* MII access register */
627: #define DC_PN_NWAY 0xB8 /* Internal NWAY register */
628:
629: /* Serial I/O EEPROM register */
630: #define DC_PN_SIOCTL_DATA 0x0000003F
631: #define DC_PN_SIOCTL_OPCODE 0x00000300
632: #define DC_PN_SIOCTL_BUSY 0x80000000
633:
634: #define DC_PN_EEOPCODE_ERASE 0x00000300
635: #define DC_PN_EEOPCODE_READ 0x00000600
636: #define DC_PN_EEOPCODE_WRITE 0x00000100
637:
638: /*
639: * The first two general purpose pins control speed selection and
640: * 100Mbps loopback on the 82c168 chip. The control bits should always
641: * be set (to make the data pins outputs) and the speed selction and
642: * loopback bits set accordingly when changing media. Physically, this
643: * will set the state of a relay mounted on the card.
644: */
645: #define DC_PN_GPIO_DATA0 0x000000001
646: #define DC_PN_GPIO_DATA1 0x000000002
647: #define DC_PN_GPIO_DATA2 0x000000004
648: #define DC_PN_GPIO_DATA3 0x000000008
649: #define DC_PN_GPIO_CTL0 0x000000010
650: #define DC_PN_GPIO_CTL1 0x000000020
651: #define DC_PN_GPIO_CTL2 0x000000040
652: #define DC_PN_GPIO_CTL3 0x000000080
653: #define DC_PN_GPIO_SPEEDSEL DC_PN_GPIO_DATA0/* 1 == 100Mbps, 0 == 10Mbps */
654: #define DC_PN_GPIO_100TX_LOOP DC_PN_GPIO_DATA1/* 1 == normal, 0 == loop */
655: #define DC_PN_GPIO_BNC_ENB DC_PN_GPIO_DATA2
656: #define DC_PN_GPIO_100TX_LNK DC_PN_GPIO_DATA3
657: #define DC_PN_GPIO_SETBIT(sc, r) \
658: DC_SETBIT(sc, DC_PN_GPIO, ((r) | (r << 4)))
659: #define DC_PN_GPIO_CLRBIT(sc, r) \
660: { \
661: DC_SETBIT(sc, DC_PN_GPIO, ((r) << 4)); \
662: DC_CLRBIT(sc, DC_PN_GPIO, (r)); \
663: }
664:
665: /* shortcut MII access register */
666: #define DC_PN_MII_DATA 0x0000FFFF
667: #define DC_PN_MII_RESERVER 0x00020000
668: #define DC_PN_MII_REGADDR 0x007C0000
669: #define DC_PN_MII_PHYADDR 0x0F800000
670: #define DC_PN_MII_OPCODE 0x30000000
671: #define DC_PN_MII_BUSY 0x80000000
672:
673: #define DC_PN_MIIOPCODE_READ 0x60020000
674: #define DC_PN_MIIOPCODE_WRITE 0x50020000
675:
676: /* Internal NWAY bits */
677: #define DC_PN_NWAY_RESET 0x00000001 /* reset */
678: #define DC_PN_NWAY_PDOWN 0x00000002 /* power down */
679: #define DC_PN_NWAY_BYPASS 0x00000004 /* bypass */
680: #define DC_PN_NWAY_AUILOWCUR 0x00000008 /* AUI low current */
681: #define DC_PN_NWAY_TPEXTEND 0x00000010 /* low squelch voltage */
682: #define DC_PN_NWAY_POLARITY 0x00000020 /* 0 == on, 1 == off */
683: #define DC_PN_NWAY_TP 0x00000040 /* 1 == tp, 0 == AUI */
684: #define DC_PN_NWAY_AUIVOLT 0x00000080 /* 1 == full, 0 == half */
685: #define DC_PN_NWAY_DUPLEX 0x00000100 /* LED, 1 == full, 0 == half */
686: #define DC_PN_NWAY_LINKTEST 0x00000200 /* 0 == on, 1 == off */
687: #define DC_PN_NWAY_AUTODETECT 0x00000400 /* 1 == off, 0 == on */
688: #define DC_PN_NWAY_SPEEDSEL 0x00000800 /* LED, 0 = 10, 1 == 100 */
689: #define DC_PN_NWAY_NWAY_ENB 0x00001000 /* 0 == off, 1 == on */
690: #define DC_PN_NWAY_CAP10HDX 0x00002000
691: #define DC_PN_NWAY_CAP10FDX 0x00004000
692: #define DC_PN_NWAY_CAP100FDX 0x00008000
693: #define DC_PN_NWAY_CAP100HDX 0x00010000
694: #define DC_PN_NWAY_CAP100T4 0x00020000
695: #define DC_PN_NWAY_ANEGRESTART 0x02000000 /* resets when aneg done */
696: #define DC_PN_NWAY_REMFAULT 0x04000000
697: #define DC_PN_NWAY_LPAR10HDX 0x08000000
698: #define DC_PN_NWAY_LPAR10FDX 0x10000000
699: #define DC_PN_NWAY_LPAR100FDX 0x20000000
700: #define DC_PN_NWAY_LPAR100HDX 0x40000000
701: #define DC_PN_NWAY_LPAR100T4 0x80000000
702:
703: /* End of PNIC specific registers */
704:
705: /*
706: * CONEXANT specific registers.
707: */
708:
709: #define DC_CONEXANT_PHYADDR 0x1
710: #define DC_CONEXANT_EE_NODEADDR 0x19A
711:
712: /* End of CONEXANT specific register */
713:
714: struct dc_softc {
715: struct device sc_dev;
716: void *sc_ih;
717: struct arpcom sc_arpcom; /* interface info */
718: mii_data_t sc_mii;
719: bus_space_handle_t dc_bhandle; /* bus space handle */
720: bus_space_tag_t dc_btag; /* bus space tag */
721: void *dc_intrhand;
722: void *sc_dhook;
723: void *sc_pwrhook;
724: struct resource *dc_irq;
725: struct resource *dc_res;
726: u_int8_t dc_type;
727: u_int8_t dc_pmode;
728: u_int8_t dc_link;
729: u_int8_t dc_cachesize;
730: int dc_romwidth;
731: int dc_pnic_rx_bug_save;
732: unsigned char *dc_pnic_rx_buf;
733: int dc_if_flags;
734: int dc_if_media;
735: u_int32_t dc_flags;
736: u_int32_t dc_txthresh;
737: u_int8_t *dc_srom;
738: struct dc_mediainfo *dc_mi;
739: struct dc_list_data *dc_ldata;
740: struct dc_chain_data dc_cdata;
741: u_int32_t dc_csid;
742: u_int dc_revision;
743: struct timeout dc_tick_tmo;
744: #ifdef SRM_MEDIA
745: int dc_srm_media;
746: #endif
747: bus_dma_tag_t sc_dmat;
748: bus_dmamap_t sc_listmap;
749: bus_dma_segment_t sc_listseg[1];
750: int sc_listnseg;
751: caddr_t sc_listkva;
752: bus_dmamap_t sc_rx_sparemap;
753: bus_dmamap_t sc_tx_sparemap;
754: int sc_hasmac;
755: };
756:
757: #define DC_TX_POLL 0x00000001
758: #define DC_TX_COALESCE 0x00000002
759: #define DC_TX_ADMTEK_WAR 0x00000004
760: #define DC_TX_USE_TX_INTR 0x00000008
761: #define DC_RX_FILTER_TULIP 0x00000010
762: #define DC_TX_INTR_FIRSTFRAG 0x00000020
763: #define DC_PNIC_RX_BUG_WAR 0x00000040
764: #define DC_TX_FIXED_RING 0x00000080
765: #define DC_TX_STORENFWD 0x00000100
766: #define DC_REDUCED_MII_POLL 0x00000200
767: #define DC_TX_INTR_ALWAYS 0x00000400
768: #define DC_21143_NWAY 0x00000800
769: #define DC_128BIT_HASH 0x00001000
770: #define DC_64BIT_HASH 0x00002000
771: #define DC_TULIP_LEDS 0x00004000
772: #define DC_TX_ONE 0x00008000
773: #define DC_TX_ALIGN 0x00010000 /* align mbuf on tx */
774: #define DC_MOMENCO_BOTCH 0x00020000
775:
776: /*
777: * register space access macros
778: */
779: #define CSR_WRITE_4(sc, reg, val) \
780: bus_space_write_4(sc->dc_btag, sc->dc_bhandle, reg, val)
781:
782: #define CSR_READ_4(sc, reg) \
783: bus_space_read_4(sc->dc_btag, sc->dc_bhandle, reg)
784:
785: #define DC_TIMEOUT 1000
786:
787: /*
788: * General constants that are fun to know.
789: */
790:
791: /* Macronix PCI revision codes. */
792: #define DC_REVISION_98713 0x00
793: #define DC_REVISION_98713A 0x10
794: #define DC_REVISION_98715 0x20
795: #define DC_REVISION_98715AEC_C 0x25
796: #define DC_REVISION_98725 0x30
797:
798: /*
799: * 82c168/82c169 PNIC device IDs. Both chips have the same device
800: * ID but different revisions. Revision 0x10 is the 82c168, and
801: * 0x20 is the 82c169.
802: */
803: #define DC_REVISION_82C168 0x10
804: #define DC_REVISION_82C169 0x20
805:
806: /*
807: * The ASIX AX88140 and ASIX AX88141 have the same vendor and
808: * device IDs but different revision values.
809: */
810: #define DC_REVISION_88140 0x00
811: #define DC_REVISION_88141 0x10
812:
813: /*
814: * The DMA9102A has the same PCI device ID as the DM9102,
815: * but a higher revision code.
816: */
817: #define DC_REVISION_DM9102 0x10
818: #define DC_REVISION_DM9102A 0x30
819:
820: /*
821: * PCI low memory base and low I/O base register, and
822: * other PCI registers.
823: */
824:
825: #define DC_PCI_CFID 0x00 /* Id */
826: #define DC_PCI_CFCS 0x04 /* Command and status */
827: #define DC_PCI_CFRV 0x08 /* Revision */
828: #define DC_PCI_CFLT 0x0C /* Latency timer */
829: #define DC_PCI_CFBIO 0x10 /* Base I/O address */
830: #define DC_PCI_CFBMA 0x14 /* Base memory address */
831: #define DC_PCI_CCIS 0x28 /* Card info struct */
832: #define DC_PCI_CSID 0x2C /* Subsystem ID */
833: #define DC_PCI_CBER 0x30 /* Expansion ROM base address */
834: #define DC_PCI_CCAP 0x34 /* Caps pointer - PD/TD chip only */
835: #define DC_PCI_CFIT 0x3C /* Interrupt */
836: #define DC_PCI_CFDD 0x40 /* Device and driver area */
837: #define DC_PCI_CWUA0 0x44 /* Wake-Up LAN addr 0 */
838: #define DC_PCI_CWUA1 0x48 /* Wake-Up LAN addr 1 */
839: #define DC_PCI_SOP0 0x4C /* SecureON passwd 0 */
840: #define DC_PCI_SOP1 0x50 /* SecureON passwd 1 */
841: #define DC_PCI_CWUC 0x54 /* Configuration Wake-Up cmd */
842: #define DC_PCI_CCID 0xDC /* Capability ID - PD/TD only */
843: #define DC_PCI_CPMC 0xE0 /* Pwrmgmt ctl & sts - PD/TD only */
844:
845: /* PCI ID register */
846: #define DC_CFID_VENDOR 0x0000FFFF
847: #define DC_CFID_DEVICE 0xFFFF0000
848:
849: /* PCI command/status register */
850: #define DC_CFCS_IOSPACE 0x00000001 /* I/O space enable */
851: #define DC_CFCS_MEMSPACE 0x00000002 /* memory space enable */
852: #define DC_CFCS_BUSMASTER 0x00000004 /* bus master enable */
853: #define DC_CFCS_MWI_ENB 0x00000010 /* mem write and inval enable */
854: #define DC_CFCS_PARITYERR_ENB 0x00000040 /* parity error enable */
855: #define DC_CFCS_SYSERR_ENB 0x00000100 /* system error enable */
856: #define DC_CFCS_NEWCAPS 0x00100000 /* new capabilities */
857: #define DC_CFCS_FAST_B2B 0x00800000 /* fast back-to-back capable */
858: #define DC_CFCS_DATAPARITY 0x01000000 /* Parity error report */
859: #define DC_CFCS_DEVSELTIM 0x06000000 /* devsel timing */
860: #define DC_CFCS_TGTABRT 0x10000000 /* received target abort */
861: #define DC_CFCS_MASTERABRT 0x20000000 /* received master abort */
862: #define DC_CFCS_SYSERR 0x40000000 /* asserted system error */
863: #define DC_CFCS_PARITYERR 0x80000000 /* asserted parity error */
864:
865: /* PCI revision register */
866: #define DC_CFRV_STEPPING 0x0000000F
867: #define DC_CFRV_REVISION 0x000000F0
868: #define DC_CFRV_SUBCLASS 0x00FF0000
869: #define DC_CFRV_BASECLASS 0xFF000000
870:
871: #define DC_21143_PB_REV 0x00000030
872: #define DC_21143_TB_REV 0x00000030
873: #define DC_21143_PC_REV 0x00000030
874: #define DC_21143_TC_REV 0x00000030
875: #define DC_21143_PD_REV 0x00000041
876: #define DC_21143_TD_REV 0x00000041
877:
878: /* PCI latency timer register */
879: #define DC_CFLT_CACHELINESIZE 0x000000FF
880: #define DC_CFLT_LATENCYTIMER 0x0000FF00
881:
882: /* PCI subsystem ID register */
883: #define DC_CSID_VENDOR 0x0000FFFF
884: #define DC_CSID_DEVICE 0xFFFF0000
885:
886: /* PCI capabilities pointer */
887: #define DC_CCAP_OFFSET 0x000000FF
888:
889: /* PCI interrupt config register */
890: #define DC_CFIT_INTLINE 0x000000FF
891: #define DC_CFIT_INTPIN 0x0000FF00
892: #define DC_CFIT_MIN_GNT 0x00FF0000
893: #define DC_CFIT_MAX_LAT 0xFF000000
894:
895: /* PCI capability register */
896: #define DC_CCID_CAPID 0x000000FF
897: #define DC_CCID_NEXTPTR 0x0000FF00
898: #define DC_CCID_PM_VERS 0x00070000
899: #define DC_CCID_PME_CLK 0x00080000
900: #define DC_CCID_DVSPEC_INT 0x00200000
901: #define DC_CCID_STATE_D1 0x02000000
902: #define DC_CCID_STATE_D2 0x04000000
903: #define DC_CCID_PME_D0 0x08000000
904: #define DC_CCID_PME_D1 0x10000000
905: #define DC_CCID_PME_D2 0x20000000
906: #define DC_CCID_PME_D3HOT 0x40000000
907: #define DC_CCID_PME_D3COLD 0x80000000
908:
909: /* PCI power management control/status register */
910: #define DC_CPMC_STATE 0x00000003
911: #define DC_CPMC_PME_ENB 0x00000100
912: #define DC_CPMC_PME_STS 0x00008000
913:
914: #define DC_PSTATE_D0 0x0
915: #define DC_PSTATE_D1 0x1
916: #define DC_PSTATE_D2 0x2
917: #define DC_PSTATE_D3 0x3
918:
919: /* Device specific region */
920: /* Configuration and driver area */
921: #define DC_CFDD_DRVUSE 0x0000FFFF
922: #define DC_CFDD_SNOOZE_MODE 0x40000000
923: #define DC_CFDD_SLEEP_MODE 0x80000000
924:
925: /* Configuration wake-up command register */
926: #define DC_CWUC_MUST_BE_ZERO 0x00000001
927: #define DC_CWUC_SECUREON_ENB 0x00000002
928: #define DC_CWUC_FORCE_WUL 0x00000004
929: #define DC_CWUC_BNC_ABILITY 0x00000008
930: #define DC_CWUC_AUI_ABILITY 0x00000010
931: #define DC_CWUC_TP10_ABILITY 0x00000020
932: #define DC_CWUC_MII_ABILITY 0x00000040
933: #define DC_CWUC_SYM_ABILITY 0x00000080
934: #define DC_CWUC_LOCK 0x00000100
935:
936: /*
937: * SROM nonsense.
938: */
939:
940: #define DC_IB_CTLRCNT 0x13
941: #define DC_IB_LEAF0_CNUM 0x1A
942: #define DC_IB_LEAF0_OFFSET 0x1B
943:
944: struct dc_info_leaf {
945: u_int16_t dc_conntype;
946: u_int8_t dc_blkcnt;
947: u_int8_t dc_rsvd;
948: u_int16_t dc_infoblk;
949: };
950:
951: #define DC_CTYPE_10BT 0x0000
952: #define DC_CTYPE_10BT_NWAY 0x0100
953: #define DC_CTYPE_10BT_FDX 0x0204
954: #define DC_CTYPE_10B2 0x0001
955: #define DC_CTYPE_10B5 0x0002
956: #define DC_CTYPE_100BT 0x0003
957: #define DC_CTYPE_100BT_FDX 0x0205
958: #define DC_CTYPE_100T4 0x0006
959: #define DC_CTYPE_100FX 0x0007
960: #define DC_CTYPE_100FX_FDX 0x0208
961: #define DC_CTYPE_MII_10BT 0x0009
962: #define DC_CTYPE_MII_10BT_FDX 0x020A
963: #define DC_CTYPE_MII_100BT 0x000D
964: #define DC_CTYPE_MII_100BT_FDX 0x020E
965: #define DC_CTYPE_MII_100T4 0x000F
966: #define DC_CTYPE_MII_100FX 0x0010
967: #define DC_CTYPE_MII_100FX_FDX 0x0211
968: #define DC_CTYPE_DYN_PUP_AUTOSENSE 0x0800
969: #define DC_CTYPE_PUP_AUTOSENSE 0x8800
970: #define DC_CTYPE_NOMEDIA 0xFFFF
971:
972: #define DC_EBLOCK_SIA 0x0002
973: #define DC_EBLOCK_MII 0x0003
974: #define DC_EBLOCK_SYM 0x0004
975: #define DC_EBLOCK_RESET 0x0005
976: #define DC_EBLOCK_PHY_SHUTDOWN 0x0006
977:
978: struct dc_leaf_hdr {
979: u_int16_t dc_mtype;
980: u_int8_t dc_mcnt;
981: u_int8_t dc_rsvd;
982: };
983:
984: struct dc_eblock_hdr {
985: u_int8_t dc_len;
986: u_int8_t dc_type;
987: };
988:
989: struct dc_eblock_sia {
990: struct dc_eblock_hdr dc_sia_hdr;
991: u_int8_t dc_sia_code;
992: union {
993: struct dc_sia_ext { /* if (dc_sia_code & DC_SIA_CODE_EXT) */
994: u_int8_t dc_sia_mediaspec[6]; /* CSR13, CSR14, CSR15 */
995: u_int8_t dc_sia_gpio_ctl[2];
996: u_int8_t dc_sia_gpio_dat[2];
997: } dc_sia_ext;
998: struct dc_sia_noext {
999: u_int8_t dc_sia_gpio_ctl[2];
1000: u_int8_t dc_sia_gpio_dat[2];
1001: } dc_sia_noext;
1002: } dc_un;
1003: };
1004:
1005: #define DC_SIA_CODE_10BT 0x00
1006: #define DC_SIA_CODE_10B2 0x01
1007: #define DC_SIA_CODE_10B5 0x02
1008: #define DC_SIA_CODE_10BT_FDX 0x04
1009: #define DC_SIA_CODE_EXT 0x40
1010:
1011: /*
1012: * Note that the first word in the gpr and reset
1013: * sequences is always a control word.
1014: */
1015: struct dc_eblock_mii {
1016: struct dc_eblock_hdr dc_mii_hdr;
1017: u_int8_t dc_mii_phynum;
1018: u_int8_t dc_gpr_len;
1019: /* u_int16_t dc_gpr_dat[n]; */
1020: /* u_int8_t dc_reset_len; */
1021: /* u_int16_t dc_reset_dat[n]; */
1022: /* There are other fields after these, but we don't
1023: * care about them since they can be determined by looking
1024: * at the PHY.
1025: */
1026: };
1027:
1028: struct dc_eblock_sym {
1029: struct dc_eblock_hdr dc_sym_hdr;
1030: u_int8_t dc_sym_code;
1031: u_int8_t dc_sym_gpio_ctl[2];
1032: u_int8_t dc_sym_gpio_dat[2];
1033: u_int8_t dc_sym_cmd[2];
1034: };
1035:
1036: #define DC_SYM_CODE_100BT 0x03
1037: #define DC_SYM_CODE_100BT_FDX 0x05
1038: #define DC_SYM_CODE_100T4 0x06
1039: #define DC_SYM_CODE_100FX 0x07
1040: #define DC_SYM_CODE_100FX_FDX 0x08
1041:
1042: struct dc_eblock_reset {
1043: struct dc_eblock_hdr dc_reset_hdr;
1044: u_int8_t dc_reset_len;
1045: /* u_int16_t dc_reset_dat[n]; */
1046: };
1047:
1048: extern void dc_attach(struct dc_softc *);
1049: extern int dc_detach(struct dc_softc *);
1050: extern int dc_intr(void *);
1051: extern void dc_reset(struct dc_softc *);
1052: extern void dc_eeprom_width(struct dc_softc *);
1053: extern void dc_read_srom(struct dc_softc *, int);
1054: extern void dc_parse_21143_srom(struct dc_softc *);
1055:
1056: #if BYTE_ORDER == BIG_ENDIAN
1057: #define DC_SP_FIELD_C(x) ((x) << 16)
1058: #else
1059: #define DC_SP_FIELD_C(x) (x)
1060: #endif
1061: #define DC_SP_FIELD(x,f) DC_SP_FIELD_C(((u_int16_t *)(x))[(f)])
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