Annotation of sys/dev/ic/comreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: comreg.h,v 1.15 2006/07/31 11:06:30 mickey Exp $ */
2: /* $NetBSD: comreg.h,v 1.8 1996/02/05 23:01:50 scottr Exp $ */
3:
4: /*
5: * Copyright (c) 1997 - 1998, Jason Downs. All rights reserved.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: *
16: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR(S) ``AS IS'' AND ANY EXPRESS
17: * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19: * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR(S) BE LIABLE FOR ANY DIRECT,
20: * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21: * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22: * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
23: * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26: * SUCH DAMAGE.
27: */
28: /*-
29: * Copyright (c) 1991 The Regents of the University of California.
30: * All rights reserved.
31: *
32: * Redistribution and use in source and binary forms, with or without
33: * modification, are permitted provided that the following conditions
34: * are met:
35: * 1. Redistributions of source code must retain the above copyright
36: * notice, this list of conditions and the following disclaimer.
37: * 2. Redistributions in binary form must reproduce the above copyright
38: * notice, this list of conditions and the following disclaimer in the
39: * documentation and/or other materials provided with the distribution.
40: * 3. Neither the name of the University nor the names of its contributors
41: * may be used to endorse or promote products derived from this software
42: * without specific prior written permission.
43: *
44: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
45: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
46: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
47: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
48: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
49: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
50: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
51: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
52: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
53: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
54: * SUCH DAMAGE.
55: *
56: * @(#)comreg.h 7.2 (Berkeley) 5/9/91
57: */
58:
59: #include <dev/ic/ns16550reg.h>
60:
61: #ifndef COM_FREQ /* allow to be set externally */
62: #define COM_FREQ 1843200 /* 16-bit baud rate divisor */
63: #endif
64: #define COM_TOLERANCE 30 /* baud rate tolerance, in 0.1% units */
65:
66: /* interrupt enable register */
67: #define IER_ERXRDY 0x1 /* Enable receiver interrupt */
68: #define IER_ETXRDY 0x2 /* Enable transmitter empty interrupt */
69: #define IER_ERLS 0x4 /* Enable line status interrupt */
70: #define IER_EMSC 0x8 /* Enable modem status interrupt */
71: #define IER_SLEEP 0x10 /* Enable sleep mode */
72: /* PXA2X0's ns16550 ports have extra bits in this register */
73: #define IER_ERXTOUT 0x10 /* Enable rx timeout interrupt */
74: #define IER_EUART 0x40 /* Enable UART */
75:
76: /* interrupt identification register */
77: #define IIR_IMASK 0xf
78: #define IIR_RXTOUT 0xc
79: #define IIR_RLS 0x6 /* Line status change */
80: #define IIR_RXRDY 0x4 /* Receiver ready */
81: #define IIR_TXRDY 0x2 /* Transmitter ready */
82: #define IIR_MLSC 0x0 /* Modem status */
83: #define IIR_NOPEND 0x1 /* No pending interrupts */
84: #define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
85:
86: /* fifo control register */
87: #define FIFO_ENABLE 0x01 /* Turn the FIFO on */
88: #define FIFO_RCV_RST 0x02 /* Reset RX FIFO */
89: #define FIFO_XMT_RST 0x04 /* Reset TX FIFO */
90: #define FIFO_DMA_MODE 0x08
91: #define FIFO_TRIGGER_1 0x00 /* Trigger RXRDY intr on 1 character */
92: #define FIFO_TRIGGER_4 0x40 /* ibid 4 */
93: #define FIFO_TRIGGER_8 0x80 /* ibid 8 */
94: #define FIFO_TRIGGER_14 0xc0 /* ibid 14 */
95: /* ST16650 fifo control register */
96: #define FIFO_RCV_TRIGGER_8 0x00
97: #define FIFO_RCV_TRIGGER_16 0x40
98: #define FIFO_RCV_TRIGGER_24 0x80
99: #define FIFO_RCV_TRIGGER_28 0xc0
100: #define FIFO_XMT_TRIGGER_16 0x00
101: #define FIFO_XMT_TRIGGER_8 0x10
102: #define FIFO_XMT_TRIGGER_24 0x20
103: #define FIFO_XMT_TRIGGER_30 0x30
104: /* XR16850 fifo control register */
105: #define FIFO_RCV3_TRIGGER_8 FIFO_RCV_TRIGGER_8
106: #define FIFO_RCV3_TRIGGER_16 FIFO_RCV_TRIGGER_16
107: #define FIFO_RCV3_TRIGGER_56 0x80
108: #define FIFO_RCV3_TRIGGER_60 0xc0
109: #define FIFO_XMT3_TRIGGER_8 0x00
110: #define FIFO_XMT3_TRIGGER_16 0x10
111: #define FIFO_XMT3_TRIGGER_32 0x20
112: #define FIFO_XMT3_TRIGGER_56 0x30
113: /* TI16750 fifo control register */
114: #define FIFO_ENABLE_64BYTE 0x20
115:
116: /* line control register */
117: #define LCR_DLAB 0x80 /* Divisor latch access enable */
118: #define LCR_SBREAK 0x40 /* Break Control */
119: #define LCR_PZERO 0x38 /* Space parity */
120: #define LCR_PONE 0x28 /* Mark parity */
121: #define LCR_PEVEN 0x18 /* Even parity */
122: #define LCR_PODD 0x08 /* Odd parity */
123: #define LCR_PNONE 0x00 /* No parity */
124: #define LCR_PENAB 0x08 /* XXX - low order bit of all parity */
125: #define LCR_STOPB 0x04 /* 2 stop bits per serial word */
126: #define LCR_8BITS 0x03 /* 8 bits per serial word */
127: #define LCR_7BITS 0x02 /* 7 bits */
128: #define LCR_6BITS 0x01 /* 6 bits */
129: #define LCR_5BITS 0x00 /* 5 bits */
130: #define LCR_EFR 0xbf /* ST16650/XR16850/OX16C950 EFR access enable */
131:
132: /* modem control register */
133: #define MCR_AFE 0x20 /* auto flow control */
134: #define MCR_LOOPBACK 0x10 /* Loop test: echos from TX to RX */
135: #define MCR_IENABLE 0x08 /* Out2: enables UART interrupts */
136: #define MCR_DRS 0x04 /* Out1: resets some internal modems */
137: #define MCR_RTS 0x02 /* Request To Send */
138: #define MCR_DTR 0x01 /* Data Terminal Ready */
139:
140: /* line status register */
141: #define LSR_RCV_FIFO 0x80
142: #define LSR_TSRE 0x40 /* Transmitter empty: byte sent */
143: #define LSR_TXRDY 0x20 /* Transmitter buffer empty */
144: #define LSR_BI 0x10 /* Break detected */
145: #define LSR_FE 0x08 /* Framing error: bad stop bit */
146: #define LSR_PE 0x04 /* Parity error */
147: #define LSR_OE 0x02 /* Overrun, lost incoming byte */
148: #define LSR_RXRDY 0x01 /* Byte ready in Receive Buffer */
149: #define LSR_RCV_MASK 0x1f /* Mask for incoming data or error */
150:
151: /* modem status register */
152: /* All deltas are from the last read of the MSR. */
153: #define MSR_DCD 0x80 /* Current Data Carrier Detect */
154: #define MSR_RI 0x40 /* Current Ring Indicator */
155: #define MSR_DSR 0x20 /* Current Data Set Ready */
156: #define MSR_CTS 0x10 /* Current Clear to Send */
157: #define MSR_DDCD 0x08 /* DCD has changed state */
158: #define MSR_TERI 0x04 /* RI has toggled low to high */
159: #define MSR_DDSR 0x02 /* DSR has changed state */
160: #define MSR_DCTS 0x01 /* CTS has changed state */
161:
162: /* enhanced features register */
163: #define EFR_ECB 0x10 /* enhanced control bit */
164: #define EFR_SCD 0x20 /* special character detect */
165: #define EFR_RTS 0x40 /* RTS flow control */
166: #define EFR_CTS 0x80 /* CTS flow control */
167:
168: /* enhanced FIFO control register */
169: #define FCTL_MODE 0x80
170: #define FCTL_SWAP 0x40
171: #define FCTL_RS485 0x08
172: #define FCTL_IrRxInv 0x04
173: #define FCTL_TRIGGER2 0x10
174: #define FCTL_TRIGGER3 0x20
175:
176: /* infrared selection register */
177: #define ISR_XMITIR 0x01 /* transmitter SIR enable */
178: #define ISR_RCVEIR 0x02 /* receiver SIR enable */
179: #define ISR_XMODE 0x04 /* 1.6us transmit pulse width */
180: #define ISR_TXPL 0x08 /* negative transmit data polarity */
181: #define ISR_RXPL 0x10 /* negative receive data polarity */
182:
183: #ifdef COM_PXA2X0
184: #define COM_NPORTS 9
185: #else
186: #define COM_NPORTS 8
187: #endif
188:
189: /*
190: * WARNING: Serial console is assumed to be at COM1 address
191: * and CONUNIT must be 0.
192: */
193: #ifndef CONADDR
194: #define CONADDR (0x3f8)
195: #else
196: #define CONADDR_OVERRIDE
197: #endif
198: #ifndef CONUNIT
199: #define CONUNIT (0)
200: #endif
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