Annotation of sys/dev/ic/bhareg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: bhareg.h,v 1.2 2003/10/21 18:58:49 jmc Exp $ */
! 2: /* $NetBSD: bhareg.h,v 1.12 1998/08/17 00:26:33 mycroft Exp $ */
! 3:
! 4: /*-
! 5: * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
! 6: * All rights reserved.
! 7: *
! 8: * This code is derived from software contributed to The NetBSD Foundation
! 9: * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace
! 10: * Simulation Facility, NASA Ames Research Center.
! 11: *
! 12: * Redistribution and use in source and binary forms, with or without
! 13: * modification, are permitted provided that the following conditions
! 14: * are met:
! 15: * 1. Redistributions of source code must retain the above copyright
! 16: * notice, this list of conditions and the following disclaimer.
! 17: * 2. Redistributions in binary form must reproduce the above copyright
! 18: * notice, this list of conditions and the following disclaimer in the
! 19: * documentation and/or other materials provided with the distribution.
! 20: * 3. All advertising materials mentioning features or use of this software
! 21: * must display the following acknowledgement:
! 22: * This product includes software developed by the NetBSD
! 23: * Foundation, Inc. and its contributors.
! 24: * 4. Neither the name of The NetBSD Foundation nor the names of its
! 25: * contributors may be used to endorse or promote products derived
! 26: * from this software without specific prior written permission.
! 27: *
! 28: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
! 29: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
! 30: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
! 31: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
! 32: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
! 33: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
! 34: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
! 35: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
! 36: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
! 37: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
! 38: * POSSIBILITY OF SUCH DAMAGE.
! 39: */
! 40:
! 41: /*
! 42: * Originally written by Julian Elischer (julian@tfs.com)
! 43: * for TRW Financial Systems for use under the MACH(2.5) operating system.
! 44: *
! 45: * TRW Financial Systems, in accordance with their agreement with Carnegie
! 46: * Mellon University, makes this software available to CMU to distribute
! 47: * or use in any manner that they see fit as long as this message is kept with
! 48: * the software. For this reason TFS also grants any other persons or
! 49: * organisations permission to use or modify this software.
! 50: *
! 51: * TFS supplies this software to be publicly redistributed
! 52: * on the understanding that TFS is not responsible for the correct
! 53: * functioning of this software in any circumstances.
! 54: */
! 55:
! 56: typedef u_int8_t physaddr[4];
! 57: typedef u_int8_t physlen[4];
! 58: #define ltophys _lto4l
! 59: #define phystol _4ltol
! 60:
! 61: /*
! 62: * I/O port offsets
! 63: */
! 64: #define BHA_CTRL_PORT 0 /* control (wo) */
! 65: #define BHA_STAT_PORT 0 /* status (ro) */
! 66: #define BHA_CMD_PORT 1 /* command (wo) */
! 67: #define BHA_DATA_PORT 1 /* data (ro) */
! 68: #define BHA_INTR_PORT 2 /* interrupt status (ro) */
! 69: #define BHA_EXTGEOM_PORT 3 /* extended geometry (ro) */
! 70:
! 71: /*
! 72: * BHA_CTRL bits
! 73: */
! 74: #define BHA_CTRL_HRST 0x80 /* Hardware reset */
! 75: #define BHA_CTRL_SRST 0x40 /* Software reset */
! 76: #define BHA_CTRL_IRST 0x20 /* Interrupt reset */
! 77: #define BHA_CTRL_SCRST 0x10 /* SCSI bus reset */
! 78:
! 79: /*
! 80: * BHA_STAT bits
! 81: */
! 82: #define BHA_STAT_STST 0x80 /* Self test in Progress */
! 83: #define BHA_STAT_DIAGF 0x40 /* Diagnostic Failure */
! 84: #define BHA_STAT_INIT 0x20 /* Mbx Init required */
! 85: #define BHA_STAT_IDLE 0x10 /* Host Adapter Idle */
! 86: #define BHA_STAT_CDF 0x08 /* cmd/data out port full */
! 87: #define BHA_STAT_DF 0x04 /* Data in port full */
! 88: #define BHA_STAT_INVDCMD 0x01 /* Invalid command */
! 89: #define BHA_STAT_BITS "\020\1invcmd\3df\4cdf\5idle\6init\7diagf\10stst"
! 90:
! 91: /*
! 92: * BHA_CMD opcodes
! 93: */
! 94: #define BHA_NOP 0x00 /* No operation */
! 95: #define BHA_MBX_INIT 0x01 /* Mbx initialization */
! 96: #define BHA_START_SCSI 0x02 /* start scsi command */
! 97: #define BHA_EXECUTE_BIOS_CMD 0x03 /* execute BIOS command */
! 98: #define BHA_INQUIRE_REVISION 0x04 /* Adapter Inquiry */
! 99: #define BHA_MBO_INTR_EN 0x05 /* Enable MBO available interrupt */
! 100: #define BHA_SEL_TIMEOUT_SET 0x06 /* set selection time-out */
! 101: #define BHA_BUS_ON_TIME_SET 0x07 /* set bus-on time */
! 102: #define BHA_BUS_OFF_TIME_SET 0x08 /* set bus-off time */
! 103: #define BHA_BUS_SPEED_SET 0x09 /* set bus transfer speed */
! 104: #define BHA_INQUIRE_DEVICES 0x0a /* return installed devices 0-7 */
! 105: #define BHA_INQUIRE_CONFIG 0x0b /* return configuration data */
! 106: #define BHA_TARGET_EN 0x0c /* enable target mode */
! 107: #define BHA_INQUIRE_SETUP 0x0d /* return setup data */
! 108: #define BHA_WRITE_LRAM 0x1a /* write adapter local RAM */
! 109: #define BHA_READ_LRAM 0x1b /* read adapter local RAM */
! 110: #define BHA_WRITE_CHIP_FIFO 0x1c /* write bus master chip FIFO */
! 111: #define BHA_READ_CHIP_FIFO 0x1d /* read bus master chip FIFO */
! 112: #define BHA_ECHO 0x1f /* Echo command byte */
! 113: #define BHA_ADAPTER_DIAGNOSTICS 0x20 /* host adapter diagnostics */
! 114: #define BHA_SET_ADAPTER_OPTIONS 0x21 /* set adapter options */
! 115: #define BHA_INQUIRE_DEVICES_2 0x23 /* return installed devices 8-15 */
! 116: #define BHA_INQUIRE_TARG_DEVS 0x24 /* inquire target devices */
! 117: #define BHA_DISABLE_HAC_INTR 0x25 /* disable host adapter interrupt */
! 118: #define BHA_MBX_INIT_EXTENDED 0x81 /* Mbx initialization */
! 119: #define BHA_EXECUTE_SCSI_CMD 0x83 /* execute SCSI command */
! 120: #define BHA_INQUIRE_REVISION_3 0x84 /* Get 3rd firmware version byte */
! 121: #define BHA_INQUIRE_REVISION_4 0x85 /* Get 4th firmware version byte */
! 122: #define BHA_INQUIRE_PCI_INFO 0x86 /* get PCI host adapter information */
! 123: #define BHA_INQUIRE_MODEL 0x8b /* Get hardware ID and revision */
! 124: #define BHA_INQUIRE_PERIOD 0x8c /* Get synchronous period */
! 125: #define BHA_INQUIRE_EXTENDED 0x8d /* Adapter Setup Inquiry */
! 126: #define BHA_ROUND_ROBIN 0x8f /* Enable/Disable(default)
! 127: round robin */
! 128: #define BHA_STORE_LRAM 0x90 /* store host adapter local RAM */
! 129: #define BHA_FETCH_LRAM 0x91 /* fetch host adapter local RAM */
! 130: #define BHA_SAVE_TO_EEPROM 0x92 /* store local RAM data in EEPROM */
! 131: #define BHA_UPLOAD_AUTOSCSI 0x94 /* upload AutoSCSI code */
! 132: #define BHA_MODIFY_IOPORT 0x95 /* change or disable I/O port */
! 133: #define BHA_SET_CCB_FORMAT 0x96 /* set CCB format (legacy/wide lun) */
! 134: #define BHA_WRITE_INQUIRY_BUF 0x9a /* write inquiry buffer */
! 135: #define BHA_READ_INQUIRY_BUF 0x9b /* read inquiry buffer */
! 136: #define BHA_FLASH_UP_DOWNLOAD 0xa7 /* flash upload/downlod */
! 137: #define BHA_READ_SCAM_DATA 0xa8 /* read SCAM data */
! 138: #define BHA_WRITE_SCAM_DATA 0xa9 /* write SCAM data */
! 139:
! 140: /*
! 141: * BHA_INTR bits
! 142: */
! 143: #define BHA_INTR_ANYINTR 0x80 /* Any interrupt */
! 144: #define BHA_INTR_SCRD 0x08 /* SCSI reset detected */
! 145: #define BHA_INTR_HACC 0x04 /* Command complete */
! 146: #define BHA_INTR_MBOA 0x02 /* MBX out empty */
! 147: #define BHA_INTR_MBIF 0x01 /* MBX in full */
! 148:
! 149: #pragma pack(1)
! 150:
! 151: struct bha_mbx_out {
! 152: physaddr ccb_addr;
! 153: u_int8_t reserved[3];
! 154: u_int8_t cmd;
! 155: };
! 156:
! 157: struct bha_mbx_in {
! 158: physaddr ccb_addr;
! 159: u_int8_t host_stat;
! 160: u_int8_t target_stat;
! 161: u_int8_t reserved;
! 162: u_int8_t comp_stat;
! 163: };
! 164:
! 165: /*
! 166: * mbo.cmd values
! 167: */
! 168: #define BHA_MBO_FREE 0x0 /* MBO entry is free */
! 169: #define BHA_MBO_START 0x1 /* MBO activate entry */
! 170: #define BHA_MBO_ABORT 0x2 /* MBO abort entry */
! 171:
! 172: /*
! 173: * mbi.comp_stat values
! 174: */
! 175: #define BHA_MBI_FREE 0x0 /* MBI entry is free */
! 176: #define BHA_MBI_OK 0x1 /* completed without error */
! 177: #define BHA_MBI_ABORT 0x2 /* aborted ccb */
! 178: #define BHA_MBI_UNKNOWN 0x3 /* Tried to abort invalid CCB */
! 179: #define BHA_MBI_ERROR 0x4 /* Completed with error */
! 180:
! 181: #if defined(BIG_DMA)
! 182: WARNING...THIS WON'T WORK(won't fit on 1 page)
! 183: #if 0
! 184: #define BHA_NSEG 2048 /* Number of scatter gather segments - to much vm */
! 185: #endif
! 186: #define BHA_NSEG 128
! 187: #else
! 188: #define BHA_NSEG 33
! 189: #endif /* BIG_DMA */
! 190:
! 191: struct bha_scat_gath {
! 192: physlen seg_len;
! 193: physaddr seg_addr;
! 194: };
! 195:
! 196: struct bha_ccb {
! 197: u_int8_t opcode;
! 198: #if BYTE_ORDER == LITTLE_ENDIAN
! 199: u_int8_t :3,
! 200: data_in :1,
! 201: data_out :1,
! 202: wide_tag_enable :1, /* Wide Lun CCB format */
! 203: wide_tag_type :2; /* Wide Lun CCB format */
! 204: #else
! 205: u_int8_t wide_tag_type :2, /* Wide Lun CCB format */
! 206: wide_tag_enable :1, /* Wide Lun CCB format */
! 207: data_out :1,
! 208: data_in :1,
! 209: :3;
! 210: #endif
! 211: u_int8_t scsi_cmd_length;
! 212: u_int8_t req_sense_length;
! 213: /*------------------------------------longword boundary */
! 214: physlen data_length;
! 215: /*------------------------------------longword boundary */
! 216: physaddr data_addr;
! 217: /*------------------------------------longword boundary */
! 218: u_int8_t reserved1[2];
! 219: u_int8_t host_stat;
! 220: u_int8_t target_stat;
! 221: /*------------------------------------longword boundary */
! 222: u_int8_t target;
! 223: #if BYTE_ORDER == LITTLE_ENDIAN
! 224: u_int8_t lun :5,
! 225: tag_enable :1,
! 226: tag_type :2;
! 227: #else
! 228: u_int8_t tag_type :2,
! 229: tag_enable :1,
! 230: lun :5;
! 231: #endif
! 232: struct scsi_generic scsi_cmd;
! 233: u_int8_t reserved2[1];
! 234: u_int8_t link_id;
! 235: /*------------------------------------longword boundary */
! 236: physaddr link_addr;
! 237: /*------------------------------------longword boundary */
! 238: physaddr sense_ptr;
! 239: /*-----end of HW fields-----------------------longword boundary */
! 240: struct scsi_sense_data scsi_sense;
! 241: /*------------------------------------longword boundary */
! 242: struct bha_scat_gath scat_gath[BHA_NSEG];
! 243: /*------------------------------------longword boundary */
! 244: TAILQ_ENTRY(bha_ccb) chain;
! 245: struct bha_ccb *nexthash;
! 246: bus_addr_t hashkey;
! 247:
! 248: struct scsi_xfer *xs; /* the scsipi_xfer for this cmd */
! 249:
! 250: int flags;
! 251: #define CCB_ALLOC 0x01
! 252: #define CCB_ABORT 0x02
! 253: #ifdef BHADIAG
! 254: #define CCB_SENDING 0x04
! 255: #endif
! 256: int timeout;
! 257:
! 258: /*
! 259: * This DMA map maps the buffer involved in the transfer.
! 260: * Its contents are loaded into "scat_gath" above.
! 261: */
! 262: bus_dmamap_t dmamap_xfer;
! 263: };
! 264:
! 265: /*
! 266: * opcode fields
! 267: */
! 268: #define BHA_INITIATOR_CCB 0x00 /* SCSI Initiator CCB */
! 269: #define BHA_TARGET_CCB 0x01 /* SCSI Target CCB */
! 270: #define BHA_INIT_SCAT_GATH_CCB 0x02 /* SCSI Initiator with S/G */
! 271: #define BHA_INIT_RESID_CCB 0x03 /* SCSI Initiator w/ residual */
! 272: #define BHA_INIT_RESID_SG_CCB 0x04 /* SCSI Initiator w/ residual and S/G */
! 273: #define BHA_RESET_CCB 0x81 /* SCSI Bus reset */
! 274:
! 275: /*
! 276: * bha_ccb.host_stat values
! 277: */
! 278: #define BHA_OK 0x00 /* cmd ok */
! 279: #define BHA_LINK_OK 0x0a /* Link cmd ok */
! 280: #define BHA_LINK_IT 0x0b /* Link cmd ok + int */
! 281: #define BHA_DATA_UNDRN 0x0c /* data underrun error */
! 282: #define BHA_SEL_TIMEOUT 0x11 /* Selection time out */
! 283: #define BHA_OVER_UNDER 0x12 /* Data over/under run */
! 284: #define BHA_BUS_FREE 0x13 /* Bus dropped at unexpected time */
! 285: #define BHA_INV_BUS 0x14 /* Invalid bus phase/sequence */
! 286: #define BHA_BAD_MBO 0x15 /* Incorrect MBO cmd */
! 287: #define BHA_BAD_CCB 0x16 /* Incorrect ccb opcode */
! 288: #define BHA_BAD_LINK 0x17 /* Not same values of LUN for links */
! 289: #define BHA_INV_TARGET 0x18 /* Invalid target direction */
! 290: #define BHA_CCB_DUP 0x19 /* Duplicate CCB received */
! 291: #define BHA_INV_CCB 0x1a /* Invalid CCB or segment list */
! 292: #define BHA_AUTOSENSE_FAILED 0x1b /* auto REQUEST SENSE failed */
! 293: #define BHA_TAGGED_MSG_REJ 0x1c /* tagged queueing message rejected */
! 294: #define BHA_UNSUP_MSG_RECVD 0x1d /* unsupported message received */
! 295: #define BHA_HARDWARE_FAILURE 0x20 /* host adapter hardware failure */
! 296: #define BHA_TARG_IGNORED_ATN 0x21 /* target ignored ATN signal */
! 297: #define BHA_HA_SCSI_BUS_RESET 0x22 /* host adapter asserted RST */
! 298: #define BHA_OTHER_SCSI_BUS_RESET 0x23 /* other device asserted RST */
! 299: #define BHA_BAD_RECONNECT 0x24 /* target reconnected improperly */
! 300: #define BHA_HA_BUS_DEVICE_RESET 0x25 /* host adapter performed BDR */
! 301: #define BHA_ABORT_QUEUE 0x26 /* abort queue generated */
! 302: #define BHA_SOFTWARE_FAILURE 0x27 /* host adapter software failure */
! 303: #define BHA_HARDWARE_WATCHDOG 0x30 /* host adapter watchdog timer fired */
! 304: #define BHA_SCSI_PARITY_ERROR 0x34 /* SCSI parity error detected */
! 305:
! 306: struct bha_extended_inquire {
! 307: struct {
! 308: u_char opcode;
! 309: u_char len;
! 310: } cmd;
! 311: struct {
! 312: u_char bus_type; /* Type of bus connected to */
! 313: #define BHA_BUS_TYPE_24BIT 'A' /* ISA bus */
! 314: #define BHA_BUS_TYPE_32BIT 'E' /* EISA/VLB/PCI bus */
! 315: #define BHA_BUS_TYPE_MCA 'M' /* MicroChannel bus */
! 316: u_char bios_address; /* Address of adapter BIOS */
! 317: u_short sg_limit;
! 318: u_char mbox_count;
! 319: u_char mbox_baseaddr[4]; /* packed/unaligned u_int32_t */
! 320: u_char intrflags;
! 321: #define BHA_INTR_FASTEISA 0x04
! 322: #define BHA_INTR_LEVEL 0x40 /* bit 6: level-sensitive interrupt */
! 323: u_char firmware_level[3]; /* last 3 digits of firmware rev */
! 324: u_char scsi_flags; /* supported SCSI features */
! 325: #define BHA_SCSI_WIDE 0x01 /* host adapter is wide */
! 326: #define BHA_SCSI_DIFFERENTIAL 0x02 /* host adapter is differential */
! 327: #define BHA_SCSI_SCAM 0x04 /* host adapter supports SCAM */
! 328: #define BHA_SCSI_ULTRA 0x08 /* host adapter supports Ultra */
! 329: #define BHA_SCSI_TERMINATION 0x10 /* host adapter supports smart
! 330: termination */
! 331: } reply;
! 332: };
! 333:
! 334: struct bha_config {
! 335: struct {
! 336: u_char opcode;
! 337: } cmd;
! 338: struct {
! 339: u_char chan;
! 340: u_char intr;
! 341: #if BYTE_ORDER == LITTLE_ENDIAN
! 342: u_char scsi_dev :3,
! 343: :5;
! 344: #else
! 345: u_char :5,
! 346: scsi_dev :3;
! 347: #endif
! 348: } reply;
! 349: };
! 350:
! 351: struct bha_toggle {
! 352: struct {
! 353: u_char opcode;
! 354: u_char enable;
! 355: } cmd;
! 356: };
! 357:
! 358: struct bha_mailbox {
! 359: struct {
! 360: u_char opcode;
! 361: u_char nmbx;
! 362: physaddr addr;
! 363: } cmd;
! 364: };
! 365:
! 366: struct bha_model {
! 367: struct {
! 368: u_char opcode;
! 369: u_char len;
! 370: } cmd;
! 371: struct {
! 372: u_char id[4]; /* i.e bt742a -> '7','4','2','A' */
! 373: u_char version[2]; /* i.e Board Revision 'H' -> 'H', 0x00 */
! 374: } reply;
! 375: };
! 376:
! 377: struct bha_revision {
! 378: struct {
! 379: u_char opcode;
! 380: } cmd;
! 381: struct {
! 382: u_char board_type;
! 383: u_char custom_feature;
! 384: char firm_revision;
! 385: u_char firm_version;
! 386: } reply;
! 387: };
! 388:
! 389: struct bha_digit {
! 390: struct {
! 391: u_char opcode;
! 392: } cmd;
! 393: struct {
! 394: u_char digit;
! 395: } reply;
! 396: };
! 397:
! 398: struct bha_devices {
! 399: struct {
! 400: u_char opcode;
! 401: } cmd;
! 402: struct {
! 403: u_char lun_map[8];
! 404: } reply;
! 405: };
! 406:
! 407: struct bha_sync {
! 408: #if BYTE_ORDER == LITTLE_ENDIAN
! 409: u_char offset :4,
! 410: period :3,
! 411: valid :1;
! 412: #else
! 413: u_char valid :1,
! 414: period :3,
! 415: offset :4;
! 416: #endif
! 417: };
! 418:
! 419: struct bha_setup_reply {
! 420: #if BYTE_ORDER == LITTLE_ENDIAN
! 421: u_int8_t sync_neg :1,
! 422: parity :1,
! 423: :6;
! 424: #else
! 425: u_int8_t :6,
! 426: parity :1,
! 427: sync_neg :1;
! 428: #endif
! 429: u_int8_t speed;
! 430: u_int8_t bus_on;
! 431: u_int8_t bus_off;
! 432: u_int8_t num_mbx;
! 433: u_int8_t mbx[3]; /*XXX */
! 434: /* doesn't make sense with 32bit addresses */
! 435: struct bha_sync sync[8];
! 436: u_int8_t disc_sts;
! 437: };
! 438:
! 439: /* additional reply data supplied by wide controllers */
! 440: struct bha_setup_reply_wide {
! 441: u_int8_t signature;
! 442: u_int8_t letter_d;
! 443: u_int8_t ha_type;
! 444: u_int8_t low_wide_allowed;
! 445: u_int8_t low_wide_active;
! 446: struct bha_sync sync_high[8];
! 447: u_int8_t high_disc_info;
! 448: u_int8_t reserved;
! 449: u_int8_t high_wide_allowed;
! 450: u_int8_t high_wide_active;
! 451: };
! 452:
! 453: struct bha_setup {
! 454: struct {
! 455: u_char opcode;
! 456: u_char len;
! 457: } cmd;
! 458: struct bha_setup_reply reply;
! 459: struct bha_setup_reply_wide reply_w; /* for wide controllers */
! 460: };
! 461:
! 462: struct bha_period_reply {
! 463: u_char period[8];
! 464: };
! 465:
! 466: struct bha_period {
! 467: struct {
! 468: u_char opcode;
! 469: u_char len;
! 470: } cmd;
! 471: struct bha_period_reply reply;
! 472: struct bha_period_reply reply_w; /* for wide controllers */
! 473: };
! 474:
! 475: struct bha_isadisable {
! 476: struct {
! 477: u_char opcode;
! 478: u_char modifier;
! 479: } cmd;
! 480: };
! 481:
! 482: #pragma pack()
! 483:
! 484: /*
! 485: * bha_isadisable.modifier parameters
! 486: */
! 487: #define BHA_IOMODIFY_330 0x00
! 488: #define BHA_IOMODIFY_334 0x01
! 489: #define BHA_IOMODIFY_DISABLE1 0x06
! 490: #define BHA_IOMODIFY_DISABLE2 0x07
! 491:
! 492: #define INT9 0x01
! 493: #define INT10 0x02
! 494: #define INT11 0x04
! 495: #define INT12 0x08
! 496: #define INT14 0x20
! 497: #define INT15 0x40
! 498:
! 499: #define EISADMA 0x00
! 500: #define CHAN0 0x01
! 501: #define CHAN5 0x20
! 502: #define CHAN6 0x40
! 503: #define CHAN7 0x80
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