Annotation of sys/dev/ic/atwreg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: atwreg.h,v 1.4 2004/07/25 00:16:35 millert Exp $ */
! 2: /* $NetBSD: atwreg.h,v 1.10 2004/07/23 05:01:29 dyoung Exp $ */
! 3:
! 4: /*
! 5: * Copyright (c) 2003 The NetBSD Foundation, Inc. All rights reserved.
! 6: *
! 7: * This code is derived from software contributed to The NetBSD Foundation
! 8: * by David Young.
! 9: *
! 10: * Redistribution and use in source and binary forms, with or without
! 11: * modification, are permitted provided that the following conditions
! 12: * are met:
! 13: * 1. Redistributions of source code must retain the above copyright
! 14: * notice, this list of conditions and the following disclaimer.
! 15: * 2. Redistributions in binary form must reproduce the above copyright
! 16: * notice, this list of conditions and the following disclaimer in the
! 17: * documentation and/or other materials provided with the distribution.
! 18: * 3. All advertising materials mentioning features or use of this software
! 19: * must display the following acknowledgement:
! 20: * This product includes software developed by the NetBSD
! 21: * Foundation, Inc. and its contributors.
! 22: * 4. Neither the name of the author nor the names of any co-contributors
! 23: * may be used to endorse or promote products derived from this software
! 24: * without specific prior written permission.
! 25: *
! 26: * THIS SOFTWARE IS PROVIDED BY David Young AND CONTRIBUTORS ``AS IS'' AND
! 27: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
! 28: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
! 29: * ARE DISCLAIMED. IN NO EVENT SHALL David Young
! 30: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
! 31: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
! 32: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
! 33: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
! 34: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
! 35: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
! 36: * THE POSSIBILITY OF SUCH DAMAGE.
! 37: */
! 38:
! 39: /* glossary */
! 40:
! 41: /* DTIM Delivery Traffic Indication Map, sent by AP
! 42: * ATIM Ad Hoc Traffic Indication Map
! 43: * TU 1024 microseconds
! 44: * TSF time synchronization function
! 45: * TBTT target beacon transmission time
! 46: * DIFS distributed inter-frame space
! 47: * SIFS short inter-frame space
! 48: * EIFS extended inter-frame space
! 49: */
! 50:
! 51: /* Macros for bit twiddling. */
! 52:
! 53: #ifndef _BIT_TWIDDLE
! 54: #define _BIT_TWIDDLE
! 55: /* nth bit, BIT(0) == 0x1. */
! 56: #define BIT(n) (((n) == 32) ? 0 : ((u_int32_t) 1 << (n)))
! 57:
! 58: /* bits m through n, m < n. */
! 59: #define BITS(m, n) ((BIT(MAX((m), (n)) + 1) - 1) ^ (BIT(MIN((m), (n))) - 1))
! 60:
! 61: /* find least significant bit that is set */
! 62: #define LOWEST_SET_BIT(x) ((((x) - 1) & (x)) ^ (x))
! 63:
! 64: /* for x a power of two and p a non-negative integer, is x a greater power than 2**p? */
! 65: #define GTEQ_POWER(x, p) (((u_long)(x) >> (p)) != 0)
! 66:
! 67: #define MASK_TO_SHIFT2(m) (GTEQ_POWER(LOWEST_SET_BIT((m)), 1) ? 1 : 0)
! 68:
! 69: #define MASK_TO_SHIFT4(m) \
! 70: (GTEQ_POWER(LOWEST_SET_BIT((m)), 2) \
! 71: ? 2 + MASK_TO_SHIFT2((m) >> 2) \
! 72: : MASK_TO_SHIFT2((m)))
! 73:
! 74: #define MASK_TO_SHIFT8(m) \
! 75: (GTEQ_POWER(LOWEST_SET_BIT((m)), 4) \
! 76: ? 4 + MASK_TO_SHIFT4((m) >> 4) \
! 77: : MASK_TO_SHIFT4((m)))
! 78:
! 79: #define MASK_TO_SHIFT16(m) \
! 80: (GTEQ_POWER(LOWEST_SET_BIT((m)), 8) \
! 81: ? 8 + MASK_TO_SHIFT8((m) >> 8) \
! 82: : MASK_TO_SHIFT8((m)))
! 83:
! 84: #define MASK_TO_SHIFT(m) \
! 85: (GTEQ_POWER(LOWEST_SET_BIT((m)), 16) \
! 86: ? 16 + MASK_TO_SHIFT16((m) >> 16) \
! 87: : MASK_TO_SHIFT16((m)))
! 88:
! 89: #define MASK_AND_RSHIFT(x, mask) (((x) & (mask)) >> MASK_TO_SHIFT(mask))
! 90: #define LSHIFT(x, mask) ((x) << MASK_TO_SHIFT(mask))
! 91: #define MASK_AND_REPLACE(reg, val, mask) ((reg & ~mask) | LSHIFT(val, mask))
! 92: #define PRESHIFT(m) MASK_AND_RSHIFT((m), (m))
! 93:
! 94: #endif /* _BIT_TWIDDLE */
! 95:
! 96: /* ADM8211 Host Control and Status Registers */
! 97:
! 98: #define ATW_PAR 0x00 /* PCI access */
! 99: #define ATW_FRCTL 0x04 /* Frame control */
! 100: #define ATW_TDR 0x08 /* Transmit demand */
! 101: #define ATW_WTDP 0x0C /* Current transmit descriptor pointer */
! 102: #define ATW_RDR 0x10 /* Receive demand */
! 103: #define ATW_WRDP 0x14 /* Current receive descriptor pointer */
! 104: #define ATW_RDB 0x18 /* Receive descriptor base address */
! 105: #define ATW_CSR3A 0x1C /* Unused (on ADM8211A) */
! 106: #define ATW_C_TDBH 0x1C /* Transmit descriptor base address,
! 107: * high-priority packet
! 108: */
! 109: #define ATW_TDBD 0x20 /* Transmit descriptor base address, DCF */
! 110: #define ATW_TDBP 0x24 /* Transmit descriptor base address, PCF */
! 111: #define ATW_STSR 0x28 /* Status */
! 112: #define ATW_CSR5A 0x2C /* Unused */
! 113: #define ATW_C_TDBB 0x2C /* Transmit descriptor base address, buffered
! 114: * broadcast/multicast packet
! 115: */
! 116: #define ATW_NAR 0x30 /* Network access */
! 117: #define ATW_CSR6A 0x34 /* Unused */
! 118: #define ATW_IER 0x38 /* Interrupt enable */
! 119: #define ATW_CSR7A 0x3C
! 120: #define ATW_LPC 0x40 /* Lost packet counter */
! 121: #define ATW_TEST1 0x44 /* Test register 1 */
! 122: #define ATW_SPR 0x48 /* Serial port */
! 123: #define ATW_TEST0 0x4C /* Test register 0 */
! 124: #define ATW_WCSR 0x50 /* Wake-up control/status */
! 125: #define ATW_WPDR 0x54 /* Wake-up pattern data */
! 126: #define ATW_GPTMR 0x58 /* General purpose timer */
! 127: #define ATW_GPIO 0x5C /* GPIO[5:0] configuration and control */
! 128: #define ATW_BBPCTL 0x60 /* BBP control port */
! 129: #define ATW_SYNCTL 0x64 /* synthesizer control port */
! 130: #define ATW_PLCPHD 0x68 /* PLCP header setting */
! 131: #define ATW_MMIWADDR 0x6C /* MMI write address */
! 132: #define ATW_MMIRADDR1 0x70 /* MMI read address 1 */
! 133: #define ATW_MMIRADDR2 0x74 /* MMI read address 2 */
! 134: #define ATW_TXBR 0x78 /* Transmit burst counter */
! 135: #define ATW_CSR15A 0x7C /* Unused */
! 136: #define ATW_ALCSTAT 0x80 /* ALC statistics */
! 137: #define ATW_TOFS2 0x84 /* Timing offset parameter 2, 16b */
! 138: #define ATW_CMDR 0x88 /* Command */
! 139: #define ATW_PCIC 0x8C /* PCI bus performance counter */
! 140: #define ATW_PMCSR 0x90 /* Power management command and status */
! 141: #define ATW_PAR0 0x94 /* Local MAC address register 0, 32b */
! 142: #define ATW_PAR1 0x98 /* Local MAC address register 1, 16b */
! 143: #define ATW_MAR0 0x9C /* Multicast address hash table register 0 */
! 144: #define ATW_MAR1 0xA0 /* Multicast address hash table register 1 */
! 145: #define ATW_ATIMDA0 0xA4 /* Ad Hoc Traffic Indication Map (ATIM)
! 146: * frame DA, byte[3:0]
! 147: */
! 148: #define ATW_ABDA1 0xA8 /* BSSID address byte[5:4];
! 149: * ATIM frame DA byte[5:4]
! 150: */
! 151: #define ATW_BSSID0 0xAC /* BSSID address byte[3:0] */
! 152: #define ATW_TXLMT 0xB0 /* WLAN retry limit, 8b;
! 153: * Max TX MSDU lifetime, 16b
! 154: */
! 155: #define ATW_MIBCNT 0xB4 /* RTS/ACK/FCS MIB count, 32b */
! 156: #define ATW_BCNT 0xB8 /* Beacon transmission time, 32b */
! 157: #define ATW_TSFTH 0xBC /* TSFT[63:32], 32b */
! 158: #define ATW_TSC 0xC0 /* TSFT[39:32] down count value */
! 159: #define ATW_SYNRF 0xC4 /* SYN RF IF direct control */
! 160: #define ATW_BPLI 0xC8 /* Beacon interval, 16b.
! 161: * STA listen interval, 16b.
! 162: */
! 163: #define ATW_CAP0 0xCC /* Current channel, 4b. RCVDTIM, 1b. */
! 164: #define ATW_CAP1 0xD0 /* Capability information, 16b.
! 165: * ATIM window, 1b.
! 166: */
! 167: #define ATW_RMD 0xD4 /* RX max reception duration, 16b */
! 168: #define ATW_CFPP 0xD8 /* CFP parameter, 32b */
! 169: #define ATW_TOFS0 0xDC /* Timing offset parameter 0, 28b */
! 170: #define ATW_TOFS1 0xE0 /* Timing offset parameter 1, 24b */
! 171: #define ATW_IFST 0xE4 /* IFS timing parameter 1, 32b */
! 172: #define ATW_RSPT 0xE8 /* Response time, 24b */
! 173: #define ATW_TSFTL 0xEC /* TSFT[31:0], 32b */
! 174: #define ATW_WEPCTL 0xF0 /* WEP control */
! 175: #define ATW_WESK 0xF4 /* Write entry for shared/individual key */
! 176: #define ATW_WEPCNT 0xF8 /* WEP count */
! 177: #define ATW_MACTEST 0xFC
! 178:
! 179: #define ATW_FER 0x100 /* Function event */
! 180: #define ATW_FEMR 0x104 /* Function event mask */
! 181: #define ATW_FPSR 0x108 /* Function present state */
! 182: #define ATW_FFER 0x10C /* Function force event */
! 183:
! 184:
! 185: #define ATW_PAR_MWIE BIT(24) /* memory write and invalidate
! 186: * enable
! 187: */
! 188: #define ATW_PAR_MRLE BIT(23) /* memory read line enable */
! 189: #define ATW_PAR_MRME BIT(21) /* memory read multiple
! 190: * enable
! 191: */
! 192: #define ATW_PAR_RAP_MASK BITS(17, 18) /* receive auto-polling in
! 193: * receive suspended state
! 194: */
! 195: #define ATW_PAR_CAL_MASK BITS(14, 15) /* cache alignment */
! 196: #define ATW_PAR_CAL_PBL 0x0
! 197: /* min(8 DW, PBL) */
! 198: #define ATW_PAR_CAL_8DW LSHIFT(0x1, ATW_PAR_CAL_MASK)
! 199: /* min(16 DW, PBL) */
! 200: #define ATW_PAR_CAL_16DW LSHIFT(0x2, ATW_PAR_CAL_MASK)
! 201: /* min(32 DW, PBL) */
! 202: #define ATW_PAR_CAL_32DW LSHIFT(0x3, ATW_PAR_CAL_MASK)
! 203: #define ATW_PAR_PBL_MASK BITS(8, 13) /* programmable burst length */
! 204: #define ATW_PAR_PBL_UNLIMITED 0x0
! 205: #define ATW_PAR_PBL_1DW LSHIFT(0x1, ATW_PAR_PBL_MASK)
! 206: #define ATW_PAR_PBL_2DW LSHIFT(0x2, ATW_PAR_PBL_MASK)
! 207: #define ATW_PAR_PBL_4DW LSHIFT(0x4, ATW_PAR_PBL_MASK)
! 208: #define ATW_PAR_PBL_8DW LSHIFT(0x8, ATW_PAR_PBL_MASK)
! 209: #define ATW_PAR_PBL_16DW LSHIFT(0x16, ATW_PAR_PBL_MASK)
! 210: #define ATW_PAR_PBL_32DW LSHIFT(0x32, ATW_PAR_PBL_MASK)
! 211: #define ATW_PAR_BLE BIT(7) /* big/little endian selection */
! 212: #define ATW_PAR_DSL_MASK BITS(2, 6) /* descriptor skip length */
! 213: #define ATW_PAR_BAR BIT(1) /* bus arbitration */
! 214: #define ATW_PAR_SWR BIT(0) /* software reset */
! 215:
! 216: #define ATW_FRCTL_PWRMGMT BIT(31) /* power management */
! 217: #define ATW_FRCTL_VER_MASK BITS(29, 30) /* protocol version */
! 218: #define ATW_FRCTL_ORDER BIT(28) /* order bit */
! 219: #define ATW_FRCTL_MAXPSP BIT(27) /* maximum power saving */
! 220: #define ATW_C_FRCTL_PRSP BIT(26) /* 1: driver sends probe
! 221: * response
! 222: * 0: ASIC sends prresp
! 223: */
! 224: #define ATW_C_FRCTL_DRVBCON BIT(25) /* 1: driver sends beacons
! 225: * 0: ASIC sends beacons
! 226: */
! 227: #define ATW_C_FRCTL_DRVLINKCTRL BIT(24) /* 1: driver controls link LED
! 228: * 0: ASIC controls link LED
! 229: */
! 230: #define ATW_C_FRCTL_DRVLINKON BIT(23) /* 1: turn on link LED
! 231: * 0: turn off link LED
! 232: */
! 233: #define ATW_C_FRCTL_CTX_DATA BIT(22) /* 0: set by CSR28
! 234: * 1: random
! 235: */
! 236: #define ATW_C_FRCTL_RSVFRM BIT(21) /* 1: receive "reserved"
! 237: * frames, 0: ignore
! 238: * reserved frames
! 239: */
! 240: #define ATW_C_FRCTL_CFEND BIT(19) /* write to send CF_END,
! 241: * ADM8211C/CR clears
! 242: */
! 243: #define ATW_FRCTL_DOZEFRM BIT(18) /* select pre-sleep frame */
! 244: #define ATW_FRCTL_PSAWAKE BIT(17) /* MAC is awake (?) */
! 245: #define ATW_FRCTL_PSMODE BIT(16) /* MAC is power-saving (?) */
! 246: #define ATW_FRCTL_AID_MASK BITS(0, 15) /* STA Association ID */
! 247:
! 248: #define ATW_INTR_PCF BIT(31) /* started/ended CFP */
! 249: #define ATW_INTR_BCNTC BIT(30) /* transmitted IBSS beacon */
! 250: #define ATW_INTR_GPINT BIT(29) /* GPIO interrupt */
! 251: #define ATW_INTR_LINKOFF BIT(28) /* lost ATW_WCSR_BLN beacons */
! 252: #define ATW_INTR_ATIMTC BIT(27) /* transmitted ATIM */
! 253: #define ATW_INTR_TSFTF BIT(26) /* TSFT out of range */
! 254: #define ATW_INTR_TSCZ BIT(25) /* TSC countdown expired */
! 255: #define ATW_INTR_LINKON BIT(24) /* matched SSID, BSSID */
! 256: #define ATW_INTR_SQL BIT(23) /* Marvel signal quality */
! 257: #define ATW_INTR_WEPTD BIT(22) /* switched WEP table */
! 258: #define ATW_INTR_ATIME BIT(21) /* ended ATIM window */
! 259: #define ATW_INTR_TBTT BIT(20) /* (TBTT) Target Beacon TX Time
! 260: * passed
! 261: */
! 262: #define ATW_INTR_NISS BIT(16) /* normal interrupt status
! 263: * summary: any of 31, 30, 27,
! 264: * 24, 14, 12, 6, 2, 0.
! 265: */
! 266: #define ATW_INTR_AISS BIT(15) /* abnormal interrupt status
! 267: * summary: any of 29, 28, 26,
! 268: * 25, 23, 22, 13, 11, 8, 7, 5,
! 269: * 4, 3, 1.
! 270: */
! 271: #define ATW_INTR_TEIS BIT(14) /* transmit early interrupt
! 272: * status: moved TX packet to
! 273: * FIFO
! 274: */
! 275: #define ATW_INTR_FBE BIT(13) /* fatal bus error */
! 276: #define ATW_INTR_REIS BIT(12) /* receive early interrupt
! 277: * status: RX packet filled
! 278: * its first descriptor
! 279: */
! 280: #define ATW_INTR_GPTT BIT(11) /* general purpose timer expired */
! 281: #define ATW_INTR_RPS BIT(8) /* stopped receive process */
! 282: #define ATW_INTR_RDU BIT(7) /* receive descriptor
! 283: * unavailable
! 284: */
! 285: #define ATW_INTR_RCI BIT(6) /* completed packet reception */
! 286: #define ATW_INTR_TUF BIT(5) /* transmit underflow */
! 287: #define ATW_INTR_TRT BIT(4) /* transmit retry count
! 288: * expired
! 289: */
! 290: #define ATW_INTR_TLT BIT(3) /* transmit lifetime exceeded */
! 291: #define ATW_INTR_TDU BIT(2) /* transmit descriptor
! 292: * unavailable
! 293: */
! 294: #define ATW_INTR_TPS BIT(1) /* stopped transmit process */
! 295: #define ATW_INTR_TCI BIT(0) /* completed transmit */
! 296: #define ATW_NAR_TXCF BIT(31) /* stop process on TX failure */
! 297: #define ATW_NAR_HF BIT(30) /* flush TX FIFO to host (?) */
! 298: #define ATW_NAR_UTR BIT(29) /* select retry count source */
! 299: #define ATW_NAR_PCF BIT(28) /* use one/both transmit
! 300: * descriptor base addresses
! 301: */
! 302: #define ATW_NAR_CFP BIT(27) /* indicate more TX data to
! 303: * point coordinator
! 304: */
! 305: #define ATW_C_NAR_APSTA BIT(26) /* 0: STA mode
! 306: * 1: AP mode
! 307: */
! 308: #define ATW_C_NAR_TDBBE BIT(25) /* 0: disable TDBB
! 309: * 1: enable TDBB
! 310: */
! 311: #define ATW_C_NAR_TDBHE BIT(24) /* 0: disable TDBH
! 312: * 1: enable TDBH
! 313: */
! 314: #define ATW_C_NAR_TDBHT BIT(23) /* write 1 to make ASIC
! 315: * poll TDBH once; ASIC clears
! 316: */
! 317: #define ATW_NAR_SF BIT(21) /* store and forward: ignore
! 318: * TX threshold
! 319: */
! 320: #define ATW_NAR_TR_MASK BITS(14, 15) /* TX threshold */
! 321: #define ATW_NAR_TR_L64 LSHIFT(0x0, ATW_NAR_TR_MASK)
! 322: #define ATW_NAR_TR_L160 LSHIFT(0x2, ATW_NAR_TR_MASK)
! 323: #define ATW_NAR_TR_L192 LSHIFT(0x3, ATW_NAR_TR_MASK)
! 324: #define ATW_NAR_TR_H96 LSHIFT(0x0, ATW_NAR_TR_MASK)
! 325: #define ATW_NAR_TR_H288 LSHIFT(0x2, ATW_NAR_TR_MASK)
! 326: #define ATW_NAR_TR_H544 LSHIFT(0x3, ATW_NAR_TR_MASK)
! 327: #define ATW_NAR_ST BIT(13) /* start/stop transmit */
! 328: #define ATW_NAR_OM_MASK BITS(10, 11) /* operating mode */
! 329: #define ATW_NAR_OM_NORMAL 0x0
! 330: #define ATW_NAR_OM_LOOPBACK LSHIFT(0x1, ATW_NAR_OM_MASK)
! 331: #define ATW_NAR_MM BIT(7) /* RX any multicast */
! 332: #define ATW_NAR_PR BIT(6) /* promiscuous mode */
! 333: #define ATW_NAR_EA BIT(5) /* match ad hoc packets (?) */
! 334: #define ATW_NAR_DISPCF BIT(4) /* 1: PCF *not* supported
! 335: * 0: PCF supported
! 336: */
! 337: #define ATW_NAR_PB BIT(3) /* pass bad packets */
! 338: #define ATW_NAR_STPDMA BIT(2) /* stop DMA, abort packet */
! 339: #define ATW_NAR_SR BIT(1) /* start/stop receive */
! 340: #define ATW_NAR_CTX BIT(0) /* continuous TX mode */
! 341:
! 342: /* IER bits are identical to STSR bits. Use ATW_INTR_*. */
! 343: #if 0
! 344: #define ATW_IER_NIE BIT(16) /* normal interrupt enable */
! 345: #define ATW_IER_AIE BIT(15) /* abnormal interrupt enable */
! 346: /* normal interrupts: combine with ATW_IER_NIE */
! 347: #define ATW_IER_PCFIE BIT(31) /* STA entered CFP */
! 348: #define ATW_IER_BCNTCIE BIT(30) /* STA TX'd beacon */
! 349: #define ATW_IER_ATIMTCIE BIT(27) /* transmitted ATIM */
! 350: #define ATW_IER_LINKONIE BIT(24) /* matched beacon */
! 351: #define ATW_IER_ATIMIE BIT(21) /* ended ATIM window */
! 352: #define ATW_IER_TBTTIE BIT(20) /* TBTT */
! 353: #define ATW_IER_TEIE BIT(14) /* moved TX packet to FIFO */
! 354: #define ATW_IER_REIE BIT(12) /* RX packet filled its first
! 355: * descriptor
! 356: */
! 357: #define ATW_IER_RCIE BIT(6) /* completed RX */
! 358: #define ATW_IER_TDUIE BIT(2) /* transmit descriptor
! 359: * unavailable
! 360: */
! 361: #define ATW_IER_TCIE BIT(0) /* completed TX */
! 362: /* abnormal interrupts: combine with ATW_IER_AIE */
! 363: #define ATW_IER_GPIE BIT(29) /* GPIO interrupt */
! 364: #define ATW_IER_LINKOFFIE BIT(28) /* lost beacon */
! 365: #define ATW_IER_TSFTFIE BIT(26) /* TSFT out of range */
! 366: #define ATW_IER_TSCIE BIT(25) /* TSC countdown expired */
! 367: #define ATW_IER_SQLIE BIT(23) /* signal quality */
! 368: #define ATW_IER_WEPIE BIT(22) /* finished WEP table switch */
! 369: #define ATW_IER_FBEIE BIT(13) /* fatal bus error */
! 370: #define ATW_IER_GPTIE BIT(11) /* general purpose timer expired */
! 371: #define ATW_IER_RPSIE BIT(8) /* stopped receive process */
! 372: #define ATW_IER_RUIE BIT(7) /* receive descriptor unavailable */
! 373: #define ATW_IER_TUIE BIT(5) /* transmit underflow */
! 374: #define ATW_IER_TRTIE BIT(4) /* exceeded transmit retry count */
! 375: #define ATW_IER_TLTTIE BIT(3) /* transmit lifetime exceeded */
! 376: #define ATW_IER_TPSIE BIT(1) /* stopped transmit process */
! 377: #endif
! 378:
! 379: #define ATW_LPC_LPCO BIT(16) /* lost packet counter overflow */
! 380: #define ATW_LPC_LPC_MASK BITS(0, 15) /* lost packet counter */
! 381:
! 382: #define ATW_TEST1_CONTROL BIT(31) /* "0: read from dxfer_control,
! 383: * 1: read from dxfer_state"
! 384: */
! 385: #define ATW_TEST1_DBGREAD_MASK BITS(30,28) /* "control of read data,
! 386: * debug only"
! 387: */
! 388: #define ATW_TEST1_TXWP_MASK BITS(27,25) /* select ATW_WTDP content? */
! 389: #define ATW_TEST1_TXWP_TDBD LSHIFT(0x0, ATW_TEST1_TXWP_MASK)
! 390: #define ATW_TEST1_TXWP_TDBH LSHIFT(0x1, ATW_TEST1_TXWP_MASK)
! 391: #define ATW_TEST1_TXWP_TDBB LSHIFT(0x2, ATW_TEST1_TXWP_MASK)
! 392: #define ATW_TEST1_TXWP_TDBP LSHIFT(0x3, ATW_TEST1_TXWP_MASK)
! 393: #define ATW_TEST1_RSVD0_MASK BITS(24,6) /* reserved */
! 394: #define ATW_TEST1_TESTMODE_MASK BITS(5,4)
! 395: /* normal operation */
! 396: #define ATW_TEST1_TESTMODE_NORMAL LSHIFT(0x0, ATW_TEST1_TESTMODE_MASK)
! 397: /* MAC-only mode */
! 398: #define ATW_TEST1_TESTMODE_MACONLY LSHIFT(0x1, ATW_TEST1_TESTMODE_MASK)
! 399: /* normal operation */
! 400: #define ATW_TEST1_TESTMODE_NORMAL2 LSHIFT(0x2, ATW_TEST1_TESTMODE_MASK)
! 401: /* monitor mode */
! 402: #define ATW_TEST1_TESTMODE_MONITOR LSHIFT(0x3, ATW_TEST1_TESTMODE_MASK)
! 403:
! 404: #define ATW_TEST1_DUMP_MASK BITS(3,0) /* select dump signal
! 405: * from dxfer (huh?)
! 406: */
! 407:
! 408: #define ATW_SPR_SRS BIT(11) /* activate SEEPROM access */
! 409: #define ATW_SPR_SDO BIT(3) /* data out of SEEPROM */
! 410: #define ATW_SPR_SDI BIT(2) /* data into SEEPROM */
! 411: #define ATW_SPR_SCLK BIT(1) /* SEEPROM clock */
! 412: #define ATW_SPR_SCS BIT(0) /* SEEPROM chip select */
! 413:
! 414: #define ATW_TEST0_BE_MASK BITS(31, 29) /* Bus error state */
! 415: #define ATW_TEST0_TS_MASK BITS(28, 26) /* Transmit process state */
! 416:
! 417: /* Stopped */
! 418: #define ATW_TEST0_TS_STOPPED LSHIFT(0, ATW_TEST0_TS_MASK)
! 419: /* Running - fetch transmit descriptor */
! 420: #define ATW_TEST0_TS_FETCH LSHIFT(1, ATW_TEST0_TS_MASK)
! 421: /* Running - wait for end of transmission */
! 422: #define ATW_TEST0_TS_WAIT LSHIFT(2, ATW_TEST0_TS_MASK)
! 423: /* Running - read buffer from memory and queue into FIFO */
! 424: #define ATW_TEST0_TS_READING LSHIFT(3, ATW_TEST0_TS_MASK)
! 425: #define ATW_TEST0_TS_RESERVED1 LSHIFT(4, ATW_TEST0_TS_MASK)
! 426: #define ATW_TEST0_TS_RESERVED2 LSHIFT(5, ATW_TEST0_TS_MASK)
! 427: /* Suspended */
! 428: #define ATW_TEST0_TS_SUSPENDED LSHIFT(6, ATW_TEST0_TS_MASK)
! 429: /* Running - close transmit descriptor */
! 430: #define ATW_TEST0_TS_CLOSE LSHIFT(7, ATW_TEST0_TS_MASK)
! 431:
! 432: /* ADM8211C/CR registers */
! 433: /* Suspended */
! 434: #define ATW_C_TEST0_TS_SUSPENDED LSHIFT(4, ATW_TEST0_TS_MASK)
! 435: /* Descriptor write */
! 436: #define ATW_C_TEST0_TS_CLOSE LSHIFT(5, ATW_TEST0_TS_MASK)
! 437: /* Last descriptor write */
! 438: #define ATW_C_TEST0_TS_CLOSELAST LSHIFT(6, ATW_TEST0_TS_MASK)
! 439: /* FIFO full */
! 440: #define ATW_C_TEST0_TS_FIFOFULL LSHIFT(7, ATW_TEST0_TS_MASK)
! 441:
! 442: #define ATW_TEST0_RS_MASK BITS(25, 23) /* Receive process state */
! 443:
! 444: /* Stopped */
! 445: #define ATW_TEST0_RS_STOPPED LSHIFT(0, ATW_TEST0_RS_MASK)
! 446: /* Running - fetch receive descriptor */
! 447: #define ATW_TEST0_RS_FETCH LSHIFT(1, ATW_TEST0_RS_MASK)
! 448: /* Running - check for end of receive */
! 449: #define ATW_TEST0_RS_CHECK LSHIFT(2, ATW_TEST0_RS_MASK)
! 450: /* Running - wait for packet */
! 451: #define ATW_TEST0_RS_WAIT LSHIFT(3, ATW_TEST0_RS_MASK)
! 452: /* Suspended */
! 453: #define ATW_TEST0_RS_SUSPENDED LSHIFT(4, ATW_TEST0_RS_MASK)
! 454: /* Running - close receive descriptor */
! 455: #define ATW_TEST0_RS_CLOSE LSHIFT(5, ATW_TEST0_RS_MASK)
! 456: /* Running - flush current frame from FIFO */
! 457: #define ATW_TEST0_RS_FLUSH LSHIFT(6, ATW_TEST0_RS_MASK)
! 458: /* Running - queue current frame from FIFO into buffer */
! 459: #define ATW_TEST0_RS_QUEUE LSHIFT(7, ATW_TEST0_RS_MASK)
! 460:
! 461: #define ATW_TEST0_EPNE BIT(18) /* SEEPROM not detected */
! 462: #define ATW_TEST0_EPSNM BIT(17) /* SEEPROM bad signature */
! 463: #define ATW_TEST0_EPTYP_MASK BIT(16) /* SEEPROM type
! 464: * 1: 93c66,
! 465: * 0: 93c46
! 466: */
! 467: #define ATW_TEST0_EPTYP_93c66 ATW_TEST0_EPTYP_MASK
! 468: #define ATW_TEST0_EPTYP_93c46 0
! 469: #define ATW_TEST0_EPRLD BIT(15) /* recall SEEPROM (write 1) */
! 470:
! 471: #define ATW_WCSR_CRCT BIT(30) /* CRC-16 type */
! 472: #define ATW_WCSR_WP1E BIT(29) /* match wake-up pattern 1 */
! 473: #define ATW_WCSR_WP2E BIT(28) /* match wake-up pattern 2 */
! 474: #define ATW_WCSR_WP3E BIT(27) /* match wake-up pattern 3 */
! 475: #define ATW_WCSR_WP4E BIT(26) /* match wake-up pattern 4 */
! 476: #define ATW_WCSR_WP5E BIT(25) /* match wake-up pattern 5 */
! 477: #define ATW_WCSR_BLN_MASK BITS(21, 23) /* lose link after BLN lost
! 478: * beacons
! 479: */
! 480: #define ATW_WCSR_TSFTWE BIT(20) /* wake up on TSFT out of
! 481: * range
! 482: */
! 483: #define ATW_WCSR_TIMWE BIT(19) /* wake up on TIM */
! 484: #define ATW_WCSR_ATIMWE BIT(18) /* wake up on ATIM */
! 485: #define ATW_WCSR_KEYWE BIT(17) /* wake up on key update */
! 486: #define ATW_WCSR_WFRE BIT(10) /* wake up on wake-up frame */
! 487: #define ATW_WCSR_MPRE BIT(9) /* wake up on magic packet */
! 488: #define ATW_WCSR_LSOE BIT(8) /* wake up on link loss */
! 489: /* wake-up reasons correspond to enable bits */
! 490: #define ATW_WCSR_KEYUP BIT(6) /* */
! 491: #define ATW_WCSR_TSFTW BIT(5) /* */
! 492: #define ATW_WCSR_TIMW BIT(4) /* */
! 493: #define ATW_WCSR_ATIMW BIT(3) /* */
! 494: #define ATW_WCSR_WFR BIT(2) /* */
! 495: #define ATW_WCSR_MPR BIT(1) /* */
! 496: #define ATW_WCSR_LSO BIT(0) /* */
! 497:
! 498: #define ATW_GPTMR_COM_MASK BIT(16) /* continuous operation mode */
! 499: #define ATW_GPTMR_GTV_MASK BITS(0, 15) /* set countdown in 204us ticks */
! 500:
! 501: #define ATW_GPIO_EC1_MASK BITS(25, 24) /* GPIO1 event configuration */
! 502: #define ATW_GPIO_LAT_MASK BITS(21, 20) /* input latch */
! 503: #define ATW_GPIO_INTEN_MASK BITS(19, 18) /* interrupt enable */
! 504: #define ATW_GPIO_EN_MASK BITS(17, 12) /* output enable */
! 505: #define ATW_GPIO_O_MASK BITS(11, 6) /* output value */
! 506: #define ATW_GPIO_I_MASK BITS(5, 0) /* pin static input */
! 507:
! 508: #define ATW_BBPCTL_TWI BIT(31) /* Intersil 3-wire interface */
! 509: #define ATW_BBPCTL_RF3KADDR_MASK BITS(30, 24) /* Address for RF3000 */
! 510: #define ATW_BBPCTL_RF3KADDR_ADDR LSHIFT(0x20, ATW_BBPCTL_RF3KADDR_MASK)
! 511: #define ATW_BBPCTL_NEGEDGE_DO BIT(23) /* data-out on negative edge */
! 512: #define ATW_BBPCTL_NEGEDGE_DI BIT(22) /* data-in on negative edge */
! 513: #define ATW_BBPCTL_CCA_ACTLO BIT(21) /* CCA low when busy */
! 514: #define ATW_BBPCTL_TYPE_MASK BITS(20, 18) /* BBP type */
! 515: #define ATW_BBPCTL_WR BIT(17) /* start write; reset on
! 516: * completion
! 517: */
! 518: #define ATW_BBPCTL_RD BIT(16) /* start read; reset on
! 519: * completion
! 520: */
! 521: #define ATW_BBPCTL_ADDR_MASK BITS(15, 8) /* BBP address */
! 522: #define ATW_BBPCTL_DATA_MASK BITS(7, 0) /* BBP data */
! 523:
! 524: #define ATW_SYNCTL_WR BIT(31) /* start write; reset on
! 525: * completion
! 526: */
! 527: #define ATW_SYNCTL_RD BIT(30) /* start read; reset on
! 528: * completion
! 529: */
! 530: #define ATW_SYNCTL_CS0 BIT(29) /* chip select */
! 531: #define ATW_SYNCTL_CS1 BIT(28)
! 532: #define ATW_SYNCTL_CAL BIT(27) /* generate RF CAL pulse after
! 533: * Rx
! 534: */
! 535: #define ATW_SYNCTL_SELCAL BIT(26) /* RF CAL source, 0: CAL bit,
! 536: * 1: MAC; needed by Intersil
! 537: * BBP
! 538: */
! 539: #define ATW_C_SYNCTL_MMICE BIT(25) /* ADM8211C/CR define this
! 540: * bit. 0: latch data on
! 541: * negative edge, 1: positive
! 542: * edge.
! 543: */
! 544: #define ATW_SYNCTL_RFTYPE_MASK BITS(24, 22) /* RF type */
! 545: #define ATW_SYNCTL_DATA_MASK BITS(21, 0) /* synthesizer setting */
! 546:
! 547: #define ATW_PLCPHD_SIGNAL_MASK BITS(31, 24) /* signal field in PLCP header,
! 548: * only for beacon, ATIM, and
! 549: * RTS.
! 550: */
! 551: #define ATW_PLCPHD_SERVICE_MASK BITS(23, 16) /* service field in PLCP
! 552: * header; with RFMD BBP,
! 553: * sets Tx power for beacon,
! 554: * RTS, ATIM.
! 555: */
! 556: #define ATW_PLCPHD_PMBL BIT(15) /* 0: long preamble, 1: short */
! 557:
! 558: #define ATW_MMIWADDR_LENLO_MASK BITS(31,24) /* tx: written 4th */
! 559: #define ATW_MMIWADDR_LENHI_MASK BITS(23,16) /* tx: written 3rd */
! 560: #define ATW_MMIWADDR_GAIN_MASK BITS(15,8) /* tx: written 2nd */
! 561: #define ATW_MMIWADDR_RATE_MASK BITS(7,0) /* tx: written 1st */
! 562:
! 563: /* was magic 0x100E0C0A */
! 564: #define ATW_MMIWADDR_INTERSIL \
! 565: (LSHIFT(0x0c, ATW_MMIWADDR_GAIN_MASK) | \
! 566: LSHIFT(0x0a, ATW_MMIWADDR_RATE_MASK) | \
! 567: LSHIFT(0x0e, ATW_MMIWADDR_LENHI_MASK) | \
! 568: LSHIFT(0x10, ATW_MMIWADDR_LENLO_MASK))
! 569:
! 570: /* was magic 0x00009101
! 571: *
! 572: * ADMtek sets the AI bit on the ATW_MMIWADDR_GAIN_MASK address to
! 573: * put the RF3000 into auto-increment mode so that it can write Tx gain,
! 574: * Tx length (high) and Tx length (low) registers back-to-back.
! 575: */
! 576: #define ATW_MMIWADDR_RFMD \
! 577: (LSHIFT(RF3000_TWI_AI|RF3000_GAINCTL, ATW_MMIWADDR_GAIN_MASK) | \
! 578: LSHIFT(RF3000_CTL, ATW_MMIWADDR_RATE_MASK))
! 579:
! 580: #define ATW_MMIRADDR1_RSVD_MASK BITS(31, 24)
! 581: #define ATW_MMIRADDR1_PWRLVL_MASK BITS(23, 16)
! 582: #define ATW_MMIRADDR1_RSSI_MASK BITS(15, 8)
! 583: #define ATW_MMIRADDR1_RXSTAT_MASK BITS(7, 0)
! 584:
! 585: /* was magic 0x00007c7e
! 586: *
! 587: * TBD document registers for Intersil 3861 baseband
! 588: */
! 589: #define ATW_MMIRADDR1_INTERSIL \
! 590: (LSHIFT(0x7c, ATW_MMIRADDR1_RSSI_MASK) | \
! 591: LSHIFT(0x7e, ATW_MMIRADDR1_RXSTAT_MASK))
! 592:
! 593: /* was magic 0x00000301 */
! 594: #define ATW_MMIRADDR1_RFMD \
! 595: (LSHIFT(RF3000_RSSI, ATW_MMIRADDR1_RSSI_MASK) | \
! 596: LSHIFT(RF3000_RXSTAT, ATW_MMIRADDR1_RXSTAT_MASK))
! 597:
! 598: /* was magic 0x00100000 */
! 599: #define ATW_MMIRADDR2_INTERSIL \
! 600: (LSHIFT(0x0, ATW_MMIRADDR2_ID_MASK) | \
! 601: LSHIFT(0x10, ATW_MMIRADDR2_RXPECNT_MASK))
! 602:
! 603: /* was magic 0x7e100000 */
! 604: #define ATW_MMIRADDR2_RFMD \
! 605: (LSHIFT(0x7e, ATW_MMIRADDR2_ID_MASK) | \
! 606: LSHIFT(0x10, ATW_MMIRADDR2_RXPECNT_MASK))
! 607:
! 608: #define ATW_MMIRADDR2_ID_MASK BITS(31, 24) /* 1st element ID in WEP table
! 609: * for Probe Response (huh?)
! 610: */
! 611: /* RXPE is re-asserted after RXPECNT * 22MHz. */
! 612: #define ATW_MMIRADDR2_RXPECNT_MASK BITS(23, 16)
! 613: #define ATW_MMIRADDR2_PROREXT BIT(15) /* Probe Response
! 614: * 11Mb/s length
! 615: * extension.
! 616: */
! 617: #define ATW_MMIRADDR2_PRORLEN_MASK BITS(14, 0) /* Probe Response
! 618: * microsecond length
! 619: */
! 620:
! 621: #define ATW_TXBR_ALCUPDATE_MASK BIT(31) /* auto-update BBP with ALCSET */
! 622: #define ATW_TXBR_TBCNT_MASK BITS(16, 20) /* transmit burst count */
! 623: #define ATW_TXBR_ALCSET_MASK BITS(8, 15) /* TX power level set point */
! 624: #define ATW_TXBR_ALCREF_MASK BITS(0, 7) /* TX power level reference point */
! 625:
! 626: #define ATW_ALCSTAT_MCOV_MASK BIT(27) /* MPDU count overflow */
! 627: #define ATW_ALCSTAT_ESOV_MASK BIT(26) /* error sum overflow */
! 628: #define ATW_ALCSTAT_MCNT_MASK BITS(16, 25) /* MPDU count, unsigned integer */
! 629: #define ATW_ALCSTAT_ERSUM_MASK BITS(0, 15) /* power error sum,
! 630: * 2's complement signed integer
! 631: */
! 632:
! 633: #define ATW_TOFS2_PWR1UP_MASK BITS(31, 28) /* delay of Tx/Rx from PE1,
! 634: * Radio, PHYRST change after
! 635: * power-up, in 2ms units
! 636: */
! 637: #define ATW_TOFS2_PWR0PAPE_MASK BITS(27, 24) /* delay of PAPE going low
! 638: * after internal data
! 639: * transmit end, in us
! 640: */
! 641: #define ATW_TOFS2_PWR1PAPE_MASK BITS(23, 20) /* delay of PAPE going high
! 642: * after TXPE asserted, in us
! 643: */
! 644: #define ATW_TOFS2_PWR0TRSW_MASK BITS(19, 16) /* delay of TRSW going low
! 645: * after internal data transmit
! 646: * end, in us
! 647: */
! 648: #define ATW_TOFS2_PWR1TRSW_MASK BITS(15, 12) /* delay of TRSW going high
! 649: * after TXPE asserted, in us
! 650: */
! 651: #define ATW_TOFS2_PWR0PE2_MASK BITS(11, 8) /* delay of PE2 going low
! 652: * after internal data transmit
! 653: * end, in us
! 654: */
! 655: #define ATW_TOFS2_PWR1PE2_MASK BITS(7, 4) /* delay of PE2 going high
! 656: * after TXPE asserted, in us
! 657: */
! 658: #define ATW_TOFS2_PWR0TXPE_MASK BITS(3, 0) /* delay of TXPE going low
! 659: * after internal data transmit
! 660: * end, in us
! 661: */
! 662:
! 663: #define ATW_CMDR_PM BIT(19) /* enables power mgmt
! 664: * capabilities.
! 665: */
! 666: #define ATW_CMDR_APM BIT(18) /* APM mode, effective when
! 667: * PM = 1.
! 668: */
! 669: #define ATW_CMDR_RTE BIT(4) /* enable Rx FIFO threshold */
! 670: #define ATW_CMDR_DRT_MASK BITS(3, 2) /* drain Rx FIFO threshold */
! 671: /* 32 bytes */
! 672: #define ATW_CMDR_DRT_8DW LSHIFT(0x0, ATW_CMDR_DRT_MASK)
! 673: /* 64 bytes */
! 674: #define ATW_CMDR_DRT_16DW LSHIFT(0x1, ATW_CMDR_DRT_MASK)
! 675: /* Store & Forward */
! 676: #define ATW_CMDR_DRT_SF LSHIFT(0x2, ATW_CMDR_DRT_MASK)
! 677: /* Reserved */
! 678: #define ATW_CMDR_DRT_RSVD LSHIFT(0x3, ATW_CMDR_DRT_MASK)
! 679: #define ATW_CMDR_SINT_MASK BIT(1) /* software interrupt---huh? */
! 680:
! 681: /* TBD PCIC */
! 682:
! 683: /* TBD PMCSR */
! 684:
! 685:
! 686: #define ATW_PAR0_PAB0_MASK BITS(0, 7) /* MAC address byte 0 */
! 687: #define ATW_PAR0_PAB1_MASK BITS(8, 15) /* MAC address byte 1 */
! 688: #define ATW_PAR0_PAB2_MASK BITS(16, 23) /* MAC address byte 2 */
! 689: #define ATW_PAR0_PAB3_MASK BITS(24, 31) /* MAC address byte 3 */
! 690:
! 691: #define ATW_C_PAR1_CTD BITS(16,31) /* Continuous Tx pattern */
! 692: #define ATW_PAR1_PAB5_MASK BITS(8, 15) /* MAC address byte 5 */
! 693: #define ATW_PAR1_PAB4_MASK BITS(0, 7) /* MAC address byte 4 */
! 694:
! 695: #define ATW_MAR0_MAB3_MASK BITS(31, 24) /* multicast table bits 31:24 */
! 696: #define ATW_MAR0_MAB2_MASK BITS(23, 16) /* multicast table bits 23:16 */
! 697: #define ATW_MAR0_MAB1_MASK BITS(15, 8) /* multicast table bits 15:8 */
! 698: #define ATW_MAR0_MAB0_MASK BITS(7, 0) /* multicast table bits 7:0 */
! 699:
! 700: #define ATW_MAR1_MAB7_MASK BITS(31, 24) /* multicast table bits 63:56 */
! 701: #define ATW_MAR1_MAB6_MASK BITS(23, 16) /* multicast table bits 55:48 */
! 702: #define ATW_MAR1_MAB5_MASK BITS(15, 8) /* multicast table bits 47:40 */
! 703: #define ATW_MAR1_MAB4_MASK BITS(7, 0) /* multicast table bits 39:32 */
! 704:
! 705: /* ATIM destination address */
! 706: #define ATW_ATIMDA0_ATIMB3_MASK BITS(31,24)
! 707: #define ATW_ATIMDA0_ATIMB2_MASK BITS(23,16)
! 708: #define ATW_ATIMDA0_ATIMB1_MASK BITS(15,8)
! 709: #define ATW_ATIMDA0_ATIMB0_MASK BITS(7,0)
! 710:
! 711: /* ATIM destination address, BSSID */
! 712: #define ATW_ABDA1_BSSIDB5_MASK BITS(31,24)
! 713: #define ATW_ABDA1_BSSIDB4_MASK BITS(23,16)
! 714: #define ATW_ABDA1_ATIMB5_MASK BITS(15,8)
! 715: #define ATW_ABDA1_ATIMB4_MASK BITS(7,0)
! 716:
! 717: /* BSSID */
! 718: #define ATW_BSSID0_BSSIDB3_MASK BITS(31,24)
! 719: #define ATW_BSSID0_BSSIDB2_MASK BITS(23,16)
! 720: #define ATW_BSSID0_BSSIDB1_MASK BITS(15,8)
! 721: #define ATW_BSSID0_BSSIDB0_MASK BITS(7,0)
! 722:
! 723: #define ATW_TXLMT_MTMLT_MASK BITS(31,16) /* max TX MSDU lifetime in TU */
! 724: #define ATW_TXLMT_SRTYLIM_MASK BITS(7,0) /* short retry limit */
! 725:
! 726: #define ATW_MIBCNT_FFCNT_MASK BITS(31,24) /* FCS failure count */
! 727: #define ATW_MIBCNT_AFCNT_MASK BITS(23,16) /* ACK failure count */
! 728: #define ATW_MIBCNT_RSCNT_MASK BITS(15,8) /* RTS success count */
! 729: #define ATW_MIBCNT_RFCNT_MASK BITS(7,0) /* RTS failure count */
! 730:
! 731: #define ATW_BCNT_PLCPH_MASK BITS(23,16) /* 11M PLCP length (us) */
! 732: #define ATW_BCNT_PLCPL_MASK BITS(15,8) /* 5.5M PLCP length (us) */
! 733: #define ATW_BCNT_BCNT_MASK BITS(7,0) /* byte count of beacon frame */
! 734:
! 735: /* For ADM8211C/CR */
! 736: /* ATW_C_TSC_TIMTABSEL = 1 */
! 737: #define ATW_C_BCNT_EXTEN1 BIT(31) /* 11M beacon len. extension */
! 738: #define ATW_C_BCNT_BEANLEN1 BITS(30,16) /* beacon length in us */
! 739: /* ATW_C_TSC_TIMTABSEL = 0 */
! 740: #define ATW_C_BCNT_EXTEN0 BIT(15) /* 11M beacon len. extension */
! 741: #define ATW_C_BCNT_BEANLEN0 BIT(14,0) /* beacon length in us */
! 742:
! 743: #define ATW_C_TSC_TIMOFS BITS(31,24) /* I think this is the
! 744: * SRAM offset for the TIM
! 745: */
! 746: #define ATW_C_TSC_TIMLEN BITS(21,12) /* length of TIM */
! 747: #define ATW_C_TSC_TIMTABSEL BIT(4) /* select TIM table 0 or 1 */
! 748: #define ATW_TSC_TSC_MASK BITS(3,0) /* TSFT countdown value, 0
! 749: * disables
! 750: */
! 751:
! 752: #define ATW_SYNRF_SELSYN BIT(31) /* 0: MAC controls SYN IF pins,
! 753: * 1: ATW_SYNRF controls SYN IF pins.
! 754: */
! 755: #define ATW_SYNRF_SELRF BIT(30) /* 0: MAC controls RF IF pins,
! 756: * 1: ATW_SYNRF controls RF IF pins.
! 757: */
! 758: #define ATW_SYNRF_LERF BIT(29) /* if SELSYN = 1, direct control of
! 759: * LERF# pin
! 760: */
! 761: #define ATW_SYNRF_LEIF BIT(28) /* if SELSYN = 1, direct control of
! 762: * LEIF# pin
! 763: */
! 764: #define ATW_SYNRF_SYNCLK BIT(27) /* if SELSYN = 1, direct control of
! 765: * SYNCLK pin
! 766: */
! 767: #define ATW_SYNRF_SYNDATA BIT(26) /* if SELSYN = 1, direct control of
! 768: * SYNDATA pin
! 769: */
! 770: #define ATW_SYNRF_PE1 BIT(25) /* if SELRF = 1, direct control of
! 771: * PE1 pin
! 772: */
! 773: #define ATW_SYNRF_PE2 BIT(24) /* if SELRF = 1, direct control of
! 774: * PE2 pin
! 775: */
! 776: #define ATW_SYNRF_PAPE BIT(23) /* if SELRF = 1, direct control of
! 777: * PAPE pin
! 778: */
! 779: #define ATW_C_SYNRF_TRSW BIT(22) /* if SELRF = 1, direct control of
! 780: * TRSW pin
! 781: */
! 782: #define ATW_C_SYNRF_TRSWN BIT(21) /* if SELRF = 1, direct control of
! 783: * TRSWn pin
! 784: */
! 785: #define ATW_SYNRF_INTERSIL_EN BIT(20) /* if SELRF = 1, enables
! 786: * some signal used by the
! 787: * Intersil RF front-end?
! 788: * Undocumented.
! 789: */
! 790: #define ATW_SYNRF_PHYRST BIT(18) /* if SELRF = 1, direct control of
! 791: * PHYRST# pin
! 792: */
! 793: /* 1: force TXPE = RXPE = 1 if ATW_CMDR[27] = 0. */
! 794: #define ATW_C_SYNRF_RF2958PD ATW_SYNRF_PHYRST
! 795:
! 796: #define ATW_BPLI_BP_MASK BITS(31,16) /* beacon interval in TU */
! 797: #define ATW_BPLI_LI_MASK BITS(15,0) /* STA listen interval in
! 798: * beacon intervals
! 799: */
! 800:
! 801: #define ATW_C_CAP0_TIMLEN1 BITS(31,24) /* TIM table 1 len in bytes
! 802: * including TIM ID (XXX huh?)
! 803: */
! 804: #define ATW_C_CAP0_TIMLEN0 BITS(23,16) /* TIM table 0 len in bytes,
! 805: * including TIM ID (XXX huh?)
! 806: */
! 807: #define ATW_C_CAP0_CWMAX BITS(11,8) /* 1 <= CWMAX <= 5 fixes CW?
! 808: * 5 < CWMAX <= 9 sets max?
! 809: * 10?
! 810: * default 0
! 811: */
! 812: #define ATW_CAP0_RCVDTIM BIT(4) /* receive every DTIM */
! 813: #define ATW_CAP0_CHN_MASK BITS(3,0) /* current DSSS channel */
! 814:
! 815: #define ATW_CAP1_CAPI_MASK BITS(31,16) /* capability information */
! 816: #define ATW_CAP1_ATIMW_MASK BITS(15,0) /* ATIM window in TU */
! 817:
! 818: #define ATW_RMD_ATIMST BIT(31) /* ATIM frame TX status */
! 819: #define ATW_RMD_CFP BIT(30) /* CFP indicator */
! 820: #define ATW_RMD_PCNT BITS(27,16) /* idle time between
! 821: * awake/ps mode, in seconds
! 822: */
! 823: #define ATW_RMD_RMRD_MASK BITS(15,0) /* max RX reception duration
! 824: * in us
! 825: */
! 826:
! 827: #define ATW_CFPP_CFPP BITS(31,24) /* CFP unit DTIM */
! 828: #define ATW_CFPP_CFPMD BITS(23,8) /* CFP max duration in TU */
! 829: #define ATW_CFPP_DTIMP BITS(7,0) /* DTIM period in beacon
! 830: * intervals
! 831: */
! 832: #define ATW_TOFS0_USCNT_MASK BITS(29,24) /* number of system clocks
! 833: * in 1 microsecond.
! 834: * Depends PCI bus speed?
! 835: */
! 836: #define ATW_C_TOFS0_TUCNT_MASK BITS(14,10) /* PIFS (microseconds) */
! 837: #define ATW_TOFS0_TUCNT_MASK BITS(9,0) /* TU counter in microseconds */
! 838:
! 839: /* TBD TOFS1 */
! 840: #define ATW_TOFS1_TSFTOFSR_MASK BITS(31,24) /* RX TSFT offset in
! 841: * microseconds: RF+BBP
! 842: * latency
! 843: */
! 844: #define ATW_TOFS1_TBTTPRE_MASK BITS(23,8) /* prediction time, (next
! 845: * Nth TBTT - TBTTOFS) in
! 846: * microseconds (huh?). To
! 847: * match TSFT[25:10] (huh?).
! 848: */
! 849: #define ATW_TBTTPRE_MASK BITS(25, 10)
! 850: #define ATW_TOFS1_TBTTOFS_MASK BITS(7,0) /* wake-up time offset before
! 851: * TBTT in TU
! 852: */
! 853: #define ATW_IFST_SLOT_MASK BITS(27,23) /* SLOT time in us */
! 854: #define ATW_IFST_SIFS_MASK BITS(22,15) /* SIFS time in us */
! 855: #define ATW_IFST_DIFS_MASK BITS(14,9) /* DIFS time in us */
! 856: #define ATW_IFST_EIFS_MASK BITS(8,0) /* EIFS time in us */
! 857:
! 858: #define ATW_RSPT_MART_MASK BITS(31,16) /* max response time in us */
! 859: #define ATW_RSPT_MIRT_MASK BITS(15,8) /* min response time in us */
! 860: #define ATW_RSPT_TSFTOFST_MASK BITS(7,0) /* TX TSFT offset in us */
! 861:
! 862: #define ATW_WEPCTL_WEPENABLE BIT(31) /* enable WEP engine */
! 863: #define ATW_WEPCTL_AUTOSWITCH BIT(30) /* auto-switch enable (huh?) */
! 864: #define ATW_WEPCTL_CURTBL BIT(29) /* current table in use */
! 865: #define ATW_WEPCTL_WR BIT(28) /* */
! 866: #define ATW_WEPCTL_RD BIT(27) /* */
! 867: #define ATW_WEPCTL_WEPRXBYP BIT(25) /* bypass WEP on RX */
! 868: #define ATW_WEPCTL_SHKEY BIT(24) /* 1: pass to host if tbl
! 869: * lookup fails, 0: use
! 870: * shared-key
! 871: */
! 872: #define ATW_WEPCTL_UNKNOWN0 BIT(23) /* has something to do with
! 873: * revision 0x20. Possibly
! 874: * selects a different WEP
! 875: * table.
! 876: */
! 877: #define ATW_WEPCTL_TBLADD_MASK BITS(8,0) /* add to table */
! 878:
! 879: /* set these bits in the second byte of a SRAM shared key record to affect
! 880: * the use and interpretation of the key in the record.
! 881: */
! 882: #define ATW_WEP_ENABLED BIT(7)
! 883: #define ATW_WEP_104BIT BIT(6)
! 884:
! 885: #define ATW_WESK_DATA_MASK BITS(15,0) /* data */
! 886: #define ATW_WEPCNT_WIEC_MASK BITS(15,0) /* WEP ICV error count */
! 887:
! 888: #define ATW_MACTEST_FORCE_IV BIT(23)
! 889: #define ATW_MACTEST_FORCE_KEYID BIT(22)
! 890: #define ATW_MACTEST_KEYID_MASK BITS(21,20)
! 891: #define ATW_MACTEST_MMI_USETXCLK BIT(11)
! 892:
! 893: /* Function Event/Status registers */
! 894:
! 895: #define ATW_FER_INTR BIT(15) /* interrupt: set regardless of mask */
! 896: #define ATW_FER_GWAKE BIT(4) /* general wake-up: set regardless of mask */
! 897:
! 898: #define ATW_FEMR_INTR_EN BIT(15) /* enable INTA# */
! 899: #define ATW_FEMR_WAKEUP_EN BIT(14) /* enable wake-up */
! 900: #define ATW_FEMR_GWAKE_EN BIT(4) /* enable general wake-up */
! 901:
! 902: #define ATW_FPSR_INTR_STATUS BIT(15) /* interrupt status */
! 903: #define ATW_FPSR_WAKEUP_STATUS BIT(4) /* CSTSCHG state */
! 904: #define ATW_FFER_INTA_FORCE BIT(15) /* activate INTA (if not masked) */
! 905: #define ATW_FFER_GWAKE_FORCE BIT(4) /* activate CSTSCHG (if not masked) */
! 906:
! 907: /* Serial EEPROM offsets */
! 908: #define ATW_SR_CLASS_CODE (0x00/2)
! 909: #define ATW_SR_FORMAT_VERSION (0x02/2)
! 910: #define ATW_SR_MAJOR_MASK BITS(7, 0)
! 911: #define ATW_SR_MINOR_MASK BITS(15,8)
! 912: #define ATW_SR_MAC00 (0x08/2) /* CSR21 */
! 913: #define ATW_SR_MAC01 (0x0A/2) /* CSR21/22 */
! 914: #define ATW_SR_MAC10 (0x0C/2) /* CSR22 */
! 915: #define ATW_SR_CSR20 (0x16/2)
! 916: #define ATW_SR_ANT_MASK BITS(12, 10)
! 917: #define ATW_SR_PWRSCALE_MASK BITS(9, 8)
! 918: #define ATW_SR_CLKSAVE_MASK BITS(7, 6)
! 919: #define ATW_SR_RFTYPE_MASK BITS(5, 3)
! 920: #define ATW_SR_BBPTYPE_MASK BITS(2, 0)
! 921: #define ATW_SR_CR28_CR03 (0x18/2)
! 922: #define ATW_SR_CR28_MASK BITS(15,8)
! 923: #define ATW_SR_CR03_MASK BITS(7, 0)
! 924: #define ATW_SR_CTRY_CR29 (0x1A/2)
! 925: #define ATW_SR_CTRY_MASK BITS(15,8) /* country code */
! 926: #define COUNTRY_FCC 0
! 927: #define COUNTRY_IC 1
! 928: #define COUNTRY_ETSI 2
! 929: #define COUNTRY_SPAIN 3
! 930: #define COUNTRY_FRANCE 4
! 931: #define COUNTRY_MMK 5
! 932: #define COUNTRY_MMK2 6
! 933: #define ATW_SR_CR29_MASK BITS(7, 0)
! 934: #define ATW_SR_PCI_DEVICE (0x20/2) /* CR0 */
! 935: #define ATW_SR_PCI_VENDOR (0x22/2) /* CR0 */
! 936: #define ATW_SR_SUB_DEVICE (0x24/2) /* CR11 */
! 937: #define ATW_SR_SUB_VENDOR (0x26/2) /* CR11 */
! 938: #define ATW_SR_CR15 (0x28/2)
! 939: #define ATW_SR_LOCISPTR (0x2A/2) /* CR10 */
! 940: #define ATW_SR_HICISPTR (0x2C/2) /* CR10 */
! 941: #define ATW_SR_CSR18 (0x2E/2)
! 942: #define ATW_SR_D0_D1_PWR (0x40/2) /* CR49 */
! 943: #define ATW_SR_D2_D3_PWR (0x42/2) /* CR49 */
! 944: #define ATW_SR_CIS_WORDS (0x52/2)
! 945: /* CR17 of RFMD RF3000 BBP: returns TWO channels */
! 946: #define ATW_SR_TXPOWER(chnl) (0x54/2 + ((chnl) - 1)/2)
! 947: /* CR20 of RFMD RF3000 BBP: returns TWO channels */
! 948: #define ATW_SR_LPF_CUTOFF(chnl) (0x62/2 + ((chnl) - 1)/2)
! 949: /* CR21 of RFMD RF3000 BBP: returns TWO channels */
! 950: #define ATW_SR_LNA_GS_THRESH(chnl) (0x70/2 + ((chnl) - 1)/2)
! 951: #define ATW_SR_CHECKSUM (0x7e/2) /* for data 0x00-0x7d */
! 952: #define ATW_SR_CIS (0x80/2) /* Cardbus CIS */
! 953:
! 954: /* Tx descriptor */
! 955: struct atw_txdesc {
! 956: u_int32_t at_ctl;
! 957: #define at_stat at_ctl
! 958: u_int32_t at_flags;
! 959: u_int32_t at_buf1;
! 960: u_int32_t at_buf2;
! 961: };
! 962:
! 963: #define ATW_TXCTL_OWN BIT(31) /* 1: ready to transmit */
! 964: #define ATW_TXCTL_DONE BIT(30) /* 0: not processed */
! 965: #define ATW_TXCTL_TXDR_MASK BITS(27,20) /* TX data rate (?) */
! 966: #define ATW_TXCTL_TL_MASK BITS(19,0) /* retry limit, 0 - 255 */
! 967:
! 968: #define ATW_TXSTAT_OWN ATW_TXCTL_OWN /* 0: not for transmission */
! 969: #define ATW_TXSTAT_DONE ATW_TXCTL_DONE /* 1: been processed */
! 970: #define ATW_TXSTAT_ES BIT(29) /* 0: TX successful */
! 971: #define ATW_TXSTAT_TLT BIT(28) /* TX lifetime expired */
! 972: #define ATW_TXSTAT_TRT BIT(27) /* TX retry limit expired */
! 973: #define ATW_TXSTAT_TUF BIT(26) /* TX under-run error */
! 974: #define ATW_TXSTAT_TRO BIT(25) /* TX over-run error */
! 975: #define ATW_TXSTAT_SOFBR BIT(24) /* packet size != buffer size
! 976: * (?)
! 977: */
! 978: #define ATW_TXSTAT_ARC_MASK BITS(11,0) /* accumulated retry count */
! 979:
! 980: #define ATW_TXFLAG_IC BIT(31) /* interrupt on completion */
! 981: #define ATW_TXFLAG_LS BIT(30) /* packet's last descriptor */
! 982: #define ATW_TXFLAG_FS BIT(29) /* packet's first descriptor */
! 983: #define ATW_TXFLAG_TER BIT(25) /* end of ring */
! 984: #define ATW_TXFLAG_TCH BIT(24) /* at_buf2 is 2nd chain */
! 985: #define ATW_TXFLAG_TBS2_MASK BITS(23,12) /* at_buf2 byte count */
! 986: #define ATW_TXFLAG_TBS1_MASK BITS(11,0) /* at_buf1 byte count */
! 987:
! 988: /* Rx descriptor */
! 989: struct atw_rxdesc {
! 990: u_int32_t ar_stat;
! 991: u_int32_t ar_ctl;
! 992: u_int32_t ar_buf1;
! 993: u_int32_t ar_buf2;
! 994: };
! 995:
! 996: #define ar_rssi ar_ctl
! 997:
! 998: #define ATW_RXCTL_RER BIT(25) /* end of ring */
! 999: #define ATW_RXCTL_RCH BIT(24) /* ar_buf2 is 2nd chain */
! 1000: #define ATW_RXCTL_RBS2_MASK BITS(23,12) /* ar_buf2 byte count */
! 1001: #define ATW_RXCTL_RBS1_MASK BITS(11,0) /* ar_buf1 byte count */
! 1002:
! 1003: #define ATW_RXSTAT_OWN BIT(31) /* 1: NIC may fill descriptor */
! 1004: #define ATW_RXSTAT_ES BIT(30) /* error summary, 0 on
! 1005: * success
! 1006: */
! 1007: #define ATW_RXSTAT_SQL BIT(29) /* has signal quality (?) */
! 1008: #define ATW_RXSTAT_DE BIT(28) /* descriptor error---packet is
! 1009: * truncated. last descriptor
! 1010: * only
! 1011: */
! 1012: #define ATW_RXSTAT_FS BIT(27) /* packet's first descriptor */
! 1013: #define ATW_RXSTAT_LS BIT(26) /* packet's last descriptor */
! 1014: #define ATW_RXSTAT_PCF BIT(25) /* received during CFP */
! 1015: #define ATW_RXSTAT_SFDE BIT(24) /* PLCP SFD error */
! 1016: #define ATW_RXSTAT_SIGE BIT(23) /* PLCP signal error */
! 1017: #define ATW_RXSTAT_CRC16E BIT(22) /* PLCP CRC16 error */
! 1018: #define ATW_RXSTAT_RXTOE BIT(21) /* RX time-out, last descriptor
! 1019: * only.
! 1020: */
! 1021: #define ATW_RXSTAT_CRC32E BIT(20) /* CRC32 error */
! 1022: #define ATW_RXSTAT_ICVE BIT(19) /* WEP ICV error */
! 1023: #define ATW_RXSTAT_DA1 BIT(17) /* DA bit 1, admin'd address */
! 1024: #define ATW_RXSTAT_DA0 BIT(16) /* DA bit 0, group address */
! 1025: #define ATW_RXSTAT_RXDR_MASK BITS(15,12) /* RX data rate */
! 1026: #define ATW_RXSTAT_FL_MASK BITS(11,0) /* RX frame length, last
! 1027: * descriptor only
! 1028: */
! 1029:
! 1030: /* Static RAM (contains WEP keys, beacon content). Addresses and size
! 1031: * are in 16-bit words.
! 1032: */
! 1033: #define ATW_SRAM_ADDR_INDIVL_KEY 0x0
! 1034: #define ATW_SRAM_ADDR_SHARED_KEY (0x160 * 2)
! 1035: #define ATW_SRAM_ADDR_SSID (0x180 * 2)
! 1036: #define ATW_SRAM_ADDR_SUPRATES (0x191 * 2)
! 1037: #define ATW_SRAM_MAXSIZE (0x200 * 2)
! 1038: #define ATW_SRAM_A_SIZE ATW_SRAM_MAXSIZE
! 1039: #define ATW_SRAM_B_SIZE (0x1c0 * 2)
! 1040:
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