Annotation of sys/dev/ic/ar5xxx.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: ar5xxx.h,v 1.41 2007/05/09 16:41:14 reyk Exp $ */
2:
3: /*
4: * Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <reyk@openbsd.org>
5: *
6: * Permission to use, copy, modify, and distribute this software for any
7: * purpose with or without fee is hereby granted, provided that the above
8: * copyright notice and this permission notice appear in all copies.
9: *
10: * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11: * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12: * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13: * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14: * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15: * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16: * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17: */
18:
19: /*
20: * HAL interface for Atheros Wireless LAN devices.
21: *
22: * ar5k is a free replacement of the binary-only HAL used by some drivers
23: * for Atheros chipsets. While using a different ABI, it tries to be
24: * source-compatible with the original (non-free) HAL interface.
25: *
26: * Many thanks to various contributors who supported the development of
27: * ar5k with hard work and useful information. And, of course, for all the
28: * people who encouraged me to continue this work which has been based
29: * on my initial approach found on http://team.vantronix.net/ar5k/.
30: */
31:
32: #ifndef _AR5K_H
33: #define _AR5K_H
34:
35: #include <sys/param.h>
36: #include <sys/systm.h>
37: #include <sys/sysctl.h>
38: #include <sys/malloc.h>
39: #include <sys/lock.h>
40: #include <sys/kernel.h>
41: #include <sys/socket.h>
42: #include <sys/sockio.h>
43: #include <sys/errno.h>
44:
45: #include <machine/endian.h>
46: #include <machine/bus.h>
47:
48: #include <net/if.h>
49: #include <net/if_dl.h>
50: #include <net/if_media.h>
51: #include <net/if_arp.h>
52: #include <net/if_llc.h>
53:
54: #ifdef INET
55: #include <netinet/in.h>
56: #include <netinet/if_ether.h>
57: #endif
58:
59: #include <net80211/ieee80211_var.h>
60: #include <net80211/ieee80211_radiotap.h>
61: #include <net80211/ieee80211_regdomain.h>
62:
63: /*
64: * Possible chipsets (could appear in different combinations)
65: */
66:
67: enum ar5k_version {
68: AR5K_AR5210 = 0,
69: AR5K_AR5211 = 1,
70: AR5K_AR5212 = 2,
71: };
72:
73: enum ar5k_radio {
74: AR5K_AR5110 = 0,
75: AR5K_AR5111 = 1,
76: AR5K_AR5112 = 2,
77: };
78:
79: /*
80: * Generic definitions
81: */
82:
83: typedef enum {
84: AH_FALSE = 0,
85: AH_TRUE,
86: } HAL_BOOL;
87:
88: typedef enum {
89: HAL_MODE_11A = 0x001,
90: HAL_MODE_TURBO = 0x002,
91: HAL_MODE_11B = 0x004,
92: HAL_MODE_PUREG = 0x008,
93: HAL_MODE_11G = 0x010,
94: HAL_MODE_108G = 0x020,
95: HAL_MODE_XR = 0x040,
96: HAL_MODE_ALL = 0xfff
97: } HAL_MODE;
98:
99: typedef enum {
100: HAL_ANT_VARIABLE = 0,
101: HAL_ANT_FIXED_A = 1,
102: HAL_ANT_FIXED_B = 2,
103: HAL_ANT_MAX = 3,
104: } HAL_ANT_SETTING;
105:
106: typedef enum {
107: HAL_M_STA = 1,
108: HAL_M_IBSS = 0,
109: HAL_M_HOSTAP = 6,
110: HAL_M_MONITOR = 8,
111: } HAL_OPMODE;
112:
113: typedef int HAL_STATUS;
114:
115: #define HAL_OK 0
116: #define HAL_EINPROGRESS EINPROGRESS
117:
118: #define AR5K_MAX_RSSI 64
119:
120: /*
121: * TX queues
122: */
123:
124: typedef enum {
125: HAL_TX_QUEUE_INACTIVE = 0,
126: HAL_TX_QUEUE_DATA,
127: HAL_TX_QUEUE_BEACON,
128: HAL_TX_QUEUE_CAB,
129: HAL_TX_QUEUE_PSPOLL,
130: } HAL_TX_QUEUE;
131:
132: #define HAL_NUM_TX_QUEUES 10
133:
134: typedef enum {
135: HAL_TX_QUEUE_ID_DATA_MIN = 0,
136: HAL_TX_QUEUE_ID_DATA_MAX = 6,
137: HAL_TX_QUEUE_ID_PSPOLL = 7,
138: HAL_TX_QUEUE_ID_BEACON = 8,
139: HAL_TX_QUEUE_ID_CAB = 9,
140: } HAL_TX_QUEUE_ID;
141:
142: typedef enum {
143: HAL_WME_AC_BK = 0,
144: HAL_WME_AC_BE = 1,
145: HAL_WME_AC_VI = 2,
146: HAL_WME_AC_VO = 3,
147: HAL_WME_UPSD = 4,
148: } HAL_TX_QUEUE_SUBTYPE;
149:
150: #define AR5K_TXQ_FLAG_TXINT_ENABLE 0x0001
151: #define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0002
152: #define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0004
153: #define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x0008
154: #define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0010
155: #define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0020
156: #define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x0040
157:
158: typedef struct {
159: u_int32_t tqi_ver;
160: HAL_TX_QUEUE tqi_type;
161: HAL_TX_QUEUE_SUBTYPE tqi_subtype;
162: u_int16_t tqi_flags;
163: u_int32_t tqi_priority;
164: u_int32_t tqi_aifs;
165: int32_t tqi_cw_min;
166: int32_t tqi_cw_max;
167: u_int32_t tqi_cbr_period;
168: u_int32_t tqi_cbr_overflow_limit;
169: u_int32_t tqi_burst_time;
170: u_int32_t tqi_ready_time;
171: } HAL_TXQ_INFO;
172:
173: typedef enum {
174: HAL_PKT_TYPE_NORMAL = 0,
175: HAL_PKT_TYPE_ATIM = 1,
176: HAL_PKT_TYPE_PSPOLL = 2,
177: HAL_PKT_TYPE_BEACON = 3,
178: HAL_PKT_TYPE_PROBE_RESP = 4,
179: HAL_PKT_TYPE_PIFS = 5,
180: } HAL_PKT_TYPE;
181:
182: /*
183: * Used to compute TX times
184: */
185:
186: #define AR5K_CCK_SIFS_TIME 10
187: #define AR5K_CCK_PREAMBLE_BITS 144
188: #define AR5K_CCK_PLCP_BITS 48
189: #define AR5K_CCK_NUM_BITS(_frmlen) (_frmlen << 3)
190: #define AR5K_CCK_PHY_TIME(_sp) (_sp ? \
191: ((AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS) >> 1) : \
192: (AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS))
193: #define AR5K_CCK_TX_TIME(_kbps, _frmlen, _sp) \
194: AR5K_CCK_PHY_TIME(_sp) + \
195: ((AR5K_CCK_NUM_BITS(_frmlen) * 1000) / _kbps) + \
196: AR5K_CCK_SIFS_TIME
197:
198: #define AR5K_OFDM_SIFS_TIME 16
199: #define AR5K_OFDM_PREAMBLE_TIME 20
200: #define AR5K_OFDM_PLCP_BITS 22
201: #define AR5K_OFDM_SYMBOL_TIME 4
202: #define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3))
203: #define AR5K_OFDM_NUM_BITS_PER_SYM(_kbps) ((_kbps * \
204: AR5K_OFDM_SYMBOL_TIME) / 1000)
205: #define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3))
206: #define AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) \
207: howmany(AR5K_OFDM_NUM_BITS(_frmlen), AR5K_OFDM_NUM_BITS_PER_SYM(_kbps))
208: #define AR5K_OFDM_TX_TIME(_kbps, _frmlen) \
209: AR5K_OFDM_PREAMBLE_TIME + AR5K_OFDM_SIFS_TIME + \
210: (AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_OFDM_SYMBOL_TIME)
211:
212: #define AR5K_TURBO_SIFS_TIME 8
213: #define AR5K_TURBO_PREAMBLE_TIME 14
214: #define AR5K_TURBO_PLCP_BITS 22
215: #define AR5K_TURBO_SYMBOL_TIME 4
216: #define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3))
217: #define AR5K_TURBO_NUM_BITS_PER_SYM(_kbps) (((_kbps << 1) * \
218: AR5K_TURBO_SYMBOL_TIME) / 1000)
219: #define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3))
220: #define AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) \
221: howmany(AR5K_TURBO_NUM_BITS(_frmlen), \
222: AR5K_TURBO_NUM_BITS_PER_SYM(_kbps))
223: #define AR5K_TURBO_TX_TIME(_kbps, _frmlen) \
224: AR5K_TURBO_PREAMBLE_TIME + AR5K_TURBO_SIFS_TIME + \
225: (AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_TURBO_SYMBOL_TIME)
226:
227: #define AR5K_XR_SIFS_TIME 16
228: #define AR5K_XR_PLCP_BITS 22
229: #define AR5K_XR_SYMBOL_TIME 4
230: #define AR5K_XR_PREAMBLE_TIME(_kbps) (((_kbps) < 1000) ? 173 : 76)
231: #define AR5K_XR_NUM_BITS_PER_SYM(_kbps) ((_kbps * \
232: AR5K_XR_SYMBOL_TIME) / 1000)
233: #define AR5K_XR_NUM_BITS(_frmlen) (AR5K_XR_PLCP_BITS + (_frmlen << 3))
234: #define AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) \
235: howmany(AR5K_XR_NUM_BITS(_frmlen), AR5K_XR_NUM_BITS_PER_SYM(_kbps))
236: #define AR5K_XR_TX_TIME(_kbps, _frmlen) \
237: AR5K_XR_PREAMBLE_TIME(_kbps) + AR5K_XR_SIFS_TIME + \
238: (AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_XR_SYMBOL_TIME)
239:
240: /*
241: * RX definitions
242: */
243:
244: #define HAL_RX_FILTER_UCAST 0x00000001
245: #define HAL_RX_FILTER_MCAST 0x00000002
246: #define HAL_RX_FILTER_BCAST 0x00000004
247: #define HAL_RX_FILTER_CONTROL 0x00000008
248: #define HAL_RX_FILTER_BEACON 0x00000010
249: #define HAL_RX_FILTER_PROM 0x00000020
250: #define HAL_RX_FILTER_PROBEREQ 0x00000080
251: #define HAL_RX_FILTER_PHYERR 0x00000100
252: #define HAL_RX_FILTER_PHYRADAR 0x00000200
253:
254: typedef struct {
255: u_int32_t ackrcv_bad;
256: u_int32_t rts_bad;
257: u_int32_t rts_good;
258: u_int32_t fcs_bad;
259: u_int32_t beacons;
260: } HAL_MIB_STATS;
261:
262: /*
263: * Beacon/AP definitions
264: */
265:
266: #define HAL_BEACON_PERIOD 0x0000ffff
267: #define HAL_BEACON_ENA 0x00800000
268: #define HAL_BEACON_RESET_TSF 0x01000000
269:
270: typedef struct {
271: u_int32_t bs_next_beacon;
272: u_int32_t bs_next_dtim;
273: u_int32_t bs_interval;
274: u_int8_t bs_dtim_period;
275: u_int8_t bs_cfp_period;
276: u_int16_t bs_cfp_max_duration;
277: u_int16_t bs_cfp_du_remain;
278: u_int16_t bs_tim_offset;
279: u_int16_t bs_sleep_duration;
280: u_int16_t bs_bmiss_threshold;
281:
282: #define bs_nexttbtt bs_next_beacon
283: #define bs_intval bs_interval
284: #define bs_nextdtim bs_next_dtim
285: #define bs_bmissthreshold bs_bmiss_threshold
286: #define bs_sleepduration bs_sleep_duration
287: #define bs_dtimperiod bs_dtim_period
288:
289: } HAL_BEACON_STATE;
290:
291: /*
292: * Power management
293: */
294:
295: typedef enum {
296: HAL_PM_UNDEFINED = 0,
297: HAL_PM_AUTO,
298: HAL_PM_AWAKE,
299: HAL_PM_FULL_SLEEP,
300: HAL_PM_NETWORK_SLEEP,
301: } HAL_POWER_MODE;
302:
303: /*
304: * Weak wireless crypto definitions (use IPsec/WLSec/...)
305: */
306:
307: typedef enum {
308: HAL_CIPHER_WEP = 0,
309: HAL_CIPHER_AES_CCM,
310: HAL_CIPHER_CKIP,
311: } HAL_CIPHER;
312:
313: #define AR5K_KEYVAL_LENGTH_40 5
314: #define AR5K_KEYVAL_LENGTH_104 13
315: #define AR5K_KEYVAL_LENGTH_128 16
316: #define AR5K_KEYVAL_LENGTH_MAX AR5K_KEYVAL_LENGTH_128
317:
318: typedef struct {
319: int wk_len;
320: u_int8_t wk_key[AR5K_KEYVAL_LENGTH_MAX];
321: } HAL_KEYVAL;
322:
323: #define AR5K_ASSERT_ENTRY(_e, _s) do { \
324: if (_e >= _s) \
325: return (AH_FALSE); \
326: } while (0)
327:
328: /*
329: * PHY
330: */
331:
332: #define AR5K_MAX_RATES 32
333:
334: typedef struct {
335: u_int8_t valid;
336: u_int8_t phy;
337: u_int16_t rateKbps;
338: u_int8_t rateCode;
339: u_int8_t shortPreamble;
340: u_int8_t dot11Rate;
341: u_int8_t controlRate;
342:
343: #define r_valid valid
344: #define r_phy phy
345: #define r_rate_kbps rateKbps
346: #define r_rate_code rateCode
347: #define r_short_preamble shortPreamble
348: #define r_dot11_rate dot11Rate
349: #define r_control_rate controlRate
350:
351: } HAL_RATE;
352:
353: typedef struct {
354: u_int16_t rateCount;
355: u_int8_t rateCodeToIndex[AR5K_MAX_RATES];
356: HAL_RATE info[AR5K_MAX_RATES];
357:
358: #define rt_rate_count rateCount
359: #define rt_rate_code_index rateCodeToIndex
360: #define rt_info info
361:
362: } HAL_RATE_TABLE;
363:
364: #define AR5K_RATES_11A { 8, { \
365: 255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0, \
366: 7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255, \
367: 255, 255, 255, 255, 255, 255, 255, 255 }, { \
368: { 1, IEEE80211_T_OFDM, 6000, 11, 0, 140, 0 }, \
369: { 1, IEEE80211_T_OFDM, 9000, 15, 0, 18, 0 }, \
370: { 1, IEEE80211_T_OFDM, 12000, 10, 0, 152, 2 }, \
371: { 1, IEEE80211_T_OFDM, 18000, 14, 0, 36, 2 }, \
372: { 1, IEEE80211_T_OFDM, 24000, 9, 0, 176, 4 }, \
373: { 1, IEEE80211_T_OFDM, 36000, 13, 0, 72, 4 }, \
374: { 1, IEEE80211_T_OFDM, 48000, 8, 0, 96, 4 }, \
375: { 1, IEEE80211_T_OFDM, 54000, 12, 0, 108, 4 } } \
376: }
377:
378: #define AR5K_RATES_11B { 4, { \
379: 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \
380: 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \
381: 3, 2, 1, 0, 255, 255, 255, 255 }, { \
382: { 1, IEEE80211_T_CCK, 1000, 27, 0x00, 130, 0 }, \
383: { 1, IEEE80211_T_CCK, 2000, 26, 0x04, 132, 1 }, \
384: { 1, IEEE80211_T_CCK, 5500, 25, 0x04, 139, 1 }, \
385: { 1, IEEE80211_T_CCK, 11000, 24, 0x04, 150, 1 } } \
386: }
387:
388: #define AR5K_RATES_11G { 12, { \
389: 255, 255, 255, 255, 255, 255, 255, 255, 10, 8, 6, 4, \
390: 11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255, \
391: 3, 2, 1, 0, 255, 255, 255, 255 }, { \
392: { 1, IEEE80211_T_CCK, 1000, 27, 0x00, 2, 0 }, \
393: { 1, IEEE80211_T_CCK, 2000, 26, 0x04, 4, 1 }, \
394: { 1, IEEE80211_T_CCK, 5500, 25, 0x04, 11, 1 }, \
395: { 1, IEEE80211_T_CCK, 11000, 24, 0x04, 22, 1 }, \
396: { 0, IEEE80211_T_OFDM, 6000, 11, 0, 12, 4 }, \
397: { 0, IEEE80211_T_OFDM, 9000, 15, 0, 18, 4 }, \
398: { 1, IEEE80211_T_OFDM, 12000, 10, 0, 24, 6 }, \
399: { 1, IEEE80211_T_OFDM, 18000, 14, 0, 36, 6 }, \
400: { 1, IEEE80211_T_OFDM, 24000, 9, 0, 48, 8 }, \
401: { 1, IEEE80211_T_OFDM, 36000, 13, 0, 72, 8 }, \
402: { 1, IEEE80211_T_OFDM, 48000, 8, 0, 96, 8 }, \
403: { 1, IEEE80211_T_OFDM, 54000, 12, 0, 108, 8 } } \
404: }
405:
406: #define AR5K_RATES_TURBO { 8, { \
407: 255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0, \
408: 7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255, \
409: 255, 255, 255, 255, 255, 255, 255, 255 }, { \
410: { 1, IEEE80211_T_TURBO, 6000, 11, 0, 140, 0 }, \
411: { 1, IEEE80211_T_TURBO, 9000, 15, 0, 18, 0 }, \
412: { 1, IEEE80211_T_TURBO, 12000, 10, 0, 152, 2 }, \
413: { 1, IEEE80211_T_TURBO, 18000, 14, 0, 36, 2 }, \
414: { 1, IEEE80211_T_TURBO, 24000, 9, 0, 176, 4 }, \
415: { 1, IEEE80211_T_TURBO, 36000, 13, 0, 72, 4 }, \
416: { 1, IEEE80211_T_TURBO, 48000, 8, 0, 96, 4 }, \
417: { 1, IEEE80211_T_TURBO, 54000, 12, 0, 108, 4 } } \
418: }
419:
420: #define AR5K_RATES_XR { 12, { \
421: 255, 3, 1, 255, 255, 255, 2, 0, 10, 8, 6, 4, \
422: 11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255, \
423: 255, 255, 255, 255, 255, 255, 255, 255 }, { \
424: { 1, IEEE80211_T_XR, 500, 7, 0, 129, 0 }, \
425: { 1, IEEE80211_T_XR, 1000, 2, 0, 139, 1 }, \
426: { 1, IEEE80211_T_XR, 2000, 6, 0, 150, 2 }, \
427: { 1, IEEE80211_T_XR, 3000, 1, 0, 150, 3 }, \
428: { 1, IEEE80211_T_OFDM, 6000, 11, 0, 140, 4 }, \
429: { 1, IEEE80211_T_OFDM, 9000, 15, 0, 18, 4 }, \
430: { 1, IEEE80211_T_OFDM, 12000, 10, 0, 152, 6 }, \
431: { 1, IEEE80211_T_OFDM, 18000, 14, 0, 36, 6 }, \
432: { 1, IEEE80211_T_OFDM, 24000, 9, 0, 176, 8 }, \
433: { 1, IEEE80211_T_OFDM, 36000, 13, 0, 72, 8 }, \
434: { 1, IEEE80211_T_OFDM, 48000, 8, 0, 96, 8 }, \
435: { 1, IEEE80211_T_OFDM, 54000, 12, 0, 108, 8 } } \
436: }
437:
438: typedef enum {
439: HAL_RFGAIN_INACTIVE = 0,
440: HAL_RFGAIN_READ_REQUESTED,
441: HAL_RFGAIN_NEED_CHANGE,
442: } HAL_RFGAIN;
443:
444: typedef struct {
445: u_int16_t channel; /* MHz */
446: u_int16_t channelFlags;
447:
448: #define c_channel channel
449: #define c_channel_flags channelFlags
450:
451: } HAL_CHANNEL;
452:
453: #define HAL_SLOT_TIME_9 396
454: #define HAL_SLOT_TIME_20 880
455: #define HAL_SLOT_TIME_MAX 0xffff
456:
457: #define CHANNEL_A (IEEE80211_CHAN_5GHZ | IEEE80211_CHAN_OFDM)
458: #define CHANNEL_B (IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_CCK)
459: #define CHANNEL_G (IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_DYN)
460: #define CHANNEL_PUREG (IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_OFDM)
461: #define CHANNEL_T (CHANNEL_A | IEEE80211_CHAN_TURBO)
462: #define CHANNEL_TG (CHANNEL_PUREG | IEEE80211_CHAN_TURBO)
463: #define CHANNEL_XR (CHANNEL_A | IEEE80211_CHAN_XR)
464: #define CHANNEL_MODES \
465: (CHANNEL_A | CHANNEL_B | CHANNEL_G | CHANNEL_PUREG | \
466: CHANNEL_T | CHANNEL_TG | CHANNEL_XR)
467:
468: typedef enum {
469: HAL_CHIP_5GHZ = IEEE80211_CHAN_5GHZ,
470: HAL_CHIP_2GHZ = IEEE80211_CHAN_2GHZ
471: } HAL_CHIP;
472:
473: /*
474: * The following structure will be used to map 2GHz channels to
475: * 5GHz Atheros channels.
476: */
477:
478: struct ar5k_athchan_2ghz {
479: u_int32_t a2_flags;
480: u_int16_t a2_athchan;
481: };
482:
483: /*
484: * Regulation stuff
485: */
486:
487: typedef enum ieee80211_countrycode HAL_CTRY_CODE;
488:
489: /*
490: * HAL interrupt abstraction
491: */
492:
493: #define HAL_INT_RX 0x00000001
494: #define HAL_INT_RXDESC 0x00000002
495: #define HAL_INT_RXNOFRM 0x00000008
496: #define HAL_INT_RXEOL 0x00000010
497: #define HAL_INT_RXORN 0x00000020
498: #define HAL_INT_TX 0x00000040
499: #define HAL_INT_TXDESC 0x00000080
500: #define HAL_INT_TXURN 0x00000800
501: #define HAL_INT_MIB 0x00001000
502: #define HAL_INT_RXPHY 0x00004000
503: #define HAL_INT_RXKCM 0x00008000
504: #define HAL_INT_SWBA 0x00010000
505: #define HAL_INT_BMISS 0x00040000
506: #define HAL_INT_BNR 0x00100000
507: #define HAL_INT_GPIO 0x01000000
508: #define HAL_INT_FATAL 0x40000000
509: #define HAL_INT_GLOBAL 0x80000000
510: #define HAL_INT_NOCARD 0xffffffff
511: #define HAL_INT_COMMON ( \
512: HAL_INT_RXNOFRM | HAL_INT_RXDESC | HAL_INT_RXEOL | \
513: HAL_INT_RXORN | HAL_INT_TXURN | HAL_INT_TXDESC | \
514: HAL_INT_MIB | HAL_INT_RXPHY | HAL_INT_RXKCM | \
515: HAL_INT_SWBA | HAL_INT_BMISS | HAL_INT_GPIO \
516: )
517:
518: typedef u_int32_t HAL_INT;
519:
520: /*
521: * LED states
522: */
523:
524: typedef enum ieee80211_state HAL_LED_STATE;
525:
526: #define HAL_LED_INIT IEEE80211_S_INIT
527: #define HAL_LED_SCAN IEEE80211_S_SCAN
528: #define HAL_LED_AUTH IEEE80211_S_AUTH
529: #define HAL_LED_ASSOC IEEE80211_S_ASSOC
530: #define HAL_LED_RUN IEEE80211_S_RUN
531:
532: /* GPIO-controlled software LED */
533: #define AR5K_SOFTLED_PIN 0
534: #define AR5K_SOFTLED_ON 0
535: #define AR5K_SOFTLED_OFF 1
536:
537: /*
538: * Gain settings
539: */
540:
541: #define AR5K_GAIN_CRN_FIX_BITS_5111 4
542: #define AR5K_GAIN_CRN_FIX_BITS_5112 7
543: #define AR5K_GAIN_CRN_MAX_FIX_BITS AR5K_GAIN_CRN_FIX_BITS_5112
544: #define AR5K_GAIN_DYN_ADJUST_HI_MARGIN 15
545: #define AR5K_GAIN_DYN_ADJUST_LO_MARGIN 20
546: #define AR5K_GAIN_CCK_PROBE_CORR 5
547: #define AR5K_GAIN_CCK_OFDM_GAIN_DELTA 15
548: #define AR5K_GAIN_STEP_COUNT 10
549: #define AR5K_GAIN_PARAM_TX_CLIP 0
550: #define AR5K_GAIN_PARAM_PD_90 1
551: #define AR5K_GAIN_PARAM_PD_84 2
552: #define AR5K_GAIN_PARAM_GAIN_SEL 3
553: #define AR5K_GAIN_PARAM_MIX_ORN 0
554: #define AR5K_GAIN_PARAM_PD_138 1
555: #define AR5K_GAIN_PARAM_PD_137 2
556: #define AR5K_GAIN_PARAM_PD_136 3
557: #define AR5K_GAIN_PARAM_PD_132 4
558: #define AR5K_GAIN_PARAM_PD_131 5
559: #define AR5K_GAIN_PARAM_PD_130 6
560: #define AR5K_GAIN_CHECK_ADJUST(_g) \
561: ((_g)->g_current <= (_g)->g_low || (_g)->g_current >= (_g)->g_high)
562:
563: struct ar5k_gain_opt_step {
564: int16_t gos_param[AR5K_GAIN_CRN_MAX_FIX_BITS];
565: int32_t gos_gain;
566: };
567:
568: struct ar5k_gain_opt {
569: u_int32_t go_default;
570: u_int32_t go_steps_count;
571: const struct ar5k_gain_opt_step go_step[AR5K_GAIN_STEP_COUNT];
572: };
573:
574: struct ar5k_gain {
575: u_int32_t g_step_idx;
576: u_int32_t g_current;
577: u_int32_t g_target;
578: u_int32_t g_low;
579: u_int32_t g_high;
580: u_int32_t g_f_corr;
581: u_int32_t g_active;
582: const struct ar5k_gain_opt_step *g_step;
583: };
584:
585: #define AR5K_AR5111_GAIN_OPT { \
586: 4, \
587: 9, \
588: { \
589: { { 4, 1, 1, 1 }, 6 }, \
590: { { 4, 0, 1, 1 }, 4 }, \
591: { { 3, 1, 1, 1 }, 3 }, \
592: { { 4, 0, 0, 1 }, 1 }, \
593: { { 4, 1, 1, 0 }, 0 }, \
594: { { 4, 0, 1, 0 }, -2 }, \
595: { { 3, 1, 1, 0 }, -3 }, \
596: { { 4, 0, 0, 0 }, -4 }, \
597: { { 2, 1, 1, 0 }, -6 } \
598: } \
599: }
600:
601: #define AR5K_AR5112_GAIN_OPT { \
602: 1, \
603: 8, \
604: { \
605: { { 3, 0, 0, 0, 0, 0, 0 }, 6 }, \
606: { { 2, 0, 0, 0, 0, 0, 0 }, 0 }, \
607: { { 1, 0, 0, 0, 0, 0, 0 }, -3 }, \
608: { { 0, 0, 0, 0, 0, 0, 0 }, -6 }, \
609: { { 0, 1, 1, 0, 0, 0, 0 }, -8 }, \
610: { { 0, 1, 1, 0, 1, 1, 0 }, -10 }, \
611: { { 0, 1, 0, 1, 1, 1, 0 }, -13 }, \
612: { { 0, 1, 0, 1, 1, 0, 1 }, -16 }, \
613: } \
614: }
615:
616: /*
617: * Common ar5xxx EEPROM data registers
618: */
619:
620: #define AR5K_EEPROM_MAGIC 0x003d
621: #define AR5K_EEPROM_MAGIC_VALUE 0x5aa5
622: #define AR5K_EEPROM_PROTECT 0x003f
623: #define AR5K_EEPROM_PROTECT_RD_0_31 0x0001
624: #define AR5K_EEPROM_PROTECT_WR_0_31 0x0002
625: #define AR5K_EEPROM_PROTECT_RD_32_63 0x0004
626: #define AR5K_EEPROM_PROTECT_WR_32_63 0x0008
627: #define AR5K_EEPROM_PROTECT_RD_64_127 0x0010
628: #define AR5K_EEPROM_PROTECT_WR_64_127 0x0020
629: #define AR5K_EEPROM_PROTECT_RD_128_191 0x0040
630: #define AR5K_EEPROM_PROTECT_WR_128_191 0x0080
631: #define AR5K_EEPROM_PROTECT_RD_192_207 0x0100
632: #define AR5K_EEPROM_PROTECT_WR_192_207 0x0200
633: #define AR5K_EEPROM_PROTECT_RD_208_223 0x0400
634: #define AR5K_EEPROM_PROTECT_WR_208_223 0x0800
635: #define AR5K_EEPROM_PROTECT_RD_224_239 0x1000
636: #define AR5K_EEPROM_PROTECT_WR_224_239 0x2000
637: #define AR5K_EEPROM_PROTECT_RD_240_255 0x4000
638: #define AR5K_EEPROM_PROTECT_WR_240_255 0x8000
639: #define AR5K_EEPROM_REG_DOMAIN 0x00bf
640: #define AR5K_EEPROM_INFO_BASE 0x00c0
641: #define AR5K_EEPROM_INFO_MAX \
642: (0x400 - AR5K_EEPROM_INFO_BASE)
643: #define AR5K_EEPROM_INFO_CKSUM 0xffff
644: #define AR5K_EEPROM_INFO(_n) (AR5K_EEPROM_INFO_BASE + (_n))
645:
646: #define AR5K_EEPROM_VERSION AR5K_EEPROM_INFO(1)
647: #define AR5K_EEPROM_VERSION_3_0 0x3000
648: #define AR5K_EEPROM_VERSION_3_1 0x3001
649: #define AR5K_EEPROM_VERSION_3_2 0x3002
650: #define AR5K_EEPROM_VERSION_3_3 0x3003
651: #define AR5K_EEPROM_VERSION_3_4 0x3004
652: #define AR5K_EEPROM_VERSION_4_0 0x4000
653: #define AR5K_EEPROM_VERSION_4_1 0x4001
654: #define AR5K_EEPROM_VERSION_4_2 0x4002
655: #define AR5K_EEPROM_VERSION_4_3 0x4003
656: #define AR5K_EEPROM_VERSION_4_6 0x4006
657: #define AR5K_EEPROM_VERSION_4_7 0x3007
658:
659: #define AR5K_EEPROM_MODE_11A 0
660: #define AR5K_EEPROM_MODE_11B 1
661: #define AR5K_EEPROM_MODE_11G 2
662:
663: #define AR5K_EEPROM_HDR AR5K_EEPROM_INFO(2)
664: #define AR5K_EEPROM_HDR_11A(_v) (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1)
665: #define AR5K_EEPROM_HDR_11B(_v) (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1)
666: #define AR5K_EEPROM_HDR_11G(_v) (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1)
667: #define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v) (((_v) >> 3) & 0x1)
668: #define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v) (((_v) >> 4) & 0x7f)
669: #define AR5K_EEPROM_HDR_DEVICE(_v) (((_v) >> 11) & 0x7)
670: #define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) (((_v) >> 15) & 0x1)
671: #define AR5K_EEPROM_HDR_RFKILL(_v) (((_v) >> 14) & 0x1)
672:
673: #define AR5K_EEPROM_RFKILL_GPIO_SEL 0x0000001c
674: #define AR5K_EEPROM_RFKILL_GPIO_SEL_S 2
675: #define AR5K_EEPROM_RFKILL_POLARITY 0x00000002
676: #define AR5K_EEPROM_RFKILL_POLARITY_S 1
677:
678: /* Newer EEPROMs are using a different offset */
679: #define AR5K_EEPROM_OFF(_v, _v3_0, _v3_3) \
680: (((_v) >= AR5K_EEPROM_VERSION_3_3) ? _v3_3 : _v3_0)
681:
682: #define AR5K_EEPROM_ANT_GAIN(_v) AR5K_EEPROM_OFF(_v, 0x00c4, 0x00c3)
683: #define AR5K_EEPROM_ANT_GAIN_5GHZ(_v) ((int8_t)(((_v) >> 8) & 0xff))
684: #define AR5K_EEPROM_ANT_GAIN_2GHZ(_v) ((int8_t)((_v) & 0xff))
685:
686: #define AR5K_EEPROM_MODES_11A(_v) AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4)
687: #define AR5K_EEPROM_MODES_11B(_v) AR5K_EEPROM_OFF(_v, 0x00d0, 0x00f2)
688: #define AR5K_EEPROM_MODES_11G(_v) AR5K_EEPROM_OFF(_v, 0x00da, 0x010d)
689: #define AR5K_EEPROM_CTL(_v) AR5K_EEPROM_OFF(_v, 0x00e4, 0x0128)
690:
691: /* Since 3.1 */
692: #define AR5K_EEPROM_OBDB0_2GHZ 0x00ec
693: #define AR5K_EEPROM_OBDB1_2GHZ 0x00ed
694:
695: /* Misc values available since EEPROM 4.0 */
696: #define AR5K_EEPROM_MISC0 0x00c4
697: #define AR5K_EEPROM_EARSTART(_v) ((_v) & 0xfff)
698: #define AR5K_EEPROM_EEMAP(_v) (((_v) >> 14) & 0x3)
699: #define AR5K_EEPROM_MISC1 0x00c5
700: #define AR5K_EEPROM_TARGET_PWRSTART(_v) ((_v) & 0xfff)
701: #define AR5K_EEPROM_HAS32KHZCRYSTAL(_v) (((_v) >> 14) & 0x1)
702:
703: /* Some EEPROM defines */
704: #define AR5K_EEPROM_EEP_SCALE 100
705: #define AR5K_EEPROM_EEP_DELTA 10
706: #define AR5K_EEPROM_N_MODES 3
707: #define AR5K_EEPROM_N_5GHZ_CHAN 10
708: #define AR5K_EEPROM_N_2GHZ_CHAN 3
709: #define AR5K_EEPROM_MAX_CHAN 10
710: #define AR5K_EEPROM_N_PCDAC 11
711: #define AR5K_EEPROM_N_TEST_FREQ 8
712: #define AR5K_EEPROM_N_EDGES 8
713: #define AR5K_EEPROM_N_INTERCEPTS 11
714: #define AR5K_EEPROM_FREQ_M(_v) AR5K_EEPROM_OFF(_v, 0x7f, 0xff)
715: #define AR5K_EEPROM_PCDAC_M 0x3f
716: #define AR5K_EEPROM_PCDAC_START 1
717: #define AR5K_EEPROM_PCDAC_STOP 63
718: #define AR5K_EEPROM_PCDAC_STEP 1
719: #define AR5K_EEPROM_NON_EDGE_M 0x40
720: #define AR5K_EEPROM_CHANNEL_POWER 8
721: #define AR5K_EEPROM_N_OBDB 4
722: #define AR5K_EEPROM_OBDB_DIS 0xffff
723: #define AR5K_EEPROM_CHANNEL_DIS 0xff
724: #define AR5K_EEPROM_SCALE_OC_DELTA(_x) (((_x) * 2) / 10)
725: #define AR5K_EEPROM_N_CTLS(_v) AR5K_EEPROM_OFF(_v, 16, 32)
726: #define AR5K_EEPROM_MAX_CTLS 32
727: #define AR5K_EEPROM_N_XPD_PER_CHANNEL 4
728: #define AR5K_EEPROM_N_XPD0_POINTS 4
729: #define AR5K_EEPROM_N_XPD3_POINTS 3
730: #define AR5K_EEPROM_N_INTERCEPT_10_2GHZ 35
731: #define AR5K_EEPROM_N_INTERCEPT_10_5GHZ 55
732: #define AR5K_EEPROM_POWER_M 0x3f
733: #define AR5K_EEPROM_POWER_MIN 0
734: #define AR5K_EEPROM_POWER_MAX 3150
735: #define AR5K_EEPROM_POWER_STEP 50
736: #define AR5K_EEPROM_POWER_TABLE_SIZE 64
737: #define AR5K_EEPROM_N_POWER_LOC_11B 4
738: #define AR5K_EEPROM_N_POWER_LOC_11G 6
739: #define AR5K_EEPROM_I_GAIN 10
740: #define AR5K_EEPROM_CCK_OFDM_DELTA 15
741: #define AR5K_EEPROM_N_IQ_CAL 2
742:
743: struct ar5k_eeprom_info {
744: u_int16_t ee_magic;
745: u_int16_t ee_protect;
746: u_int16_t ee_regdomain;
747: u_int16_t ee_version;
748: u_int16_t ee_header;
749: u_int16_t ee_ant_gain;
750: u_int16_t ee_misc0;
751: u_int16_t ee_misc1;
752: u_int16_t ee_cck_ofdm_gain_delta;
753: u_int16_t ee_cck_ofdm_power_delta;
754: u_int16_t ee_scaled_cck_delta;
755: u_int16_t ee_tx_clip;
756: u_int16_t ee_pwd_84;
757: u_int16_t ee_pwd_90;
758: u_int16_t ee_gain_select;
759:
760: u_int16_t ee_i_cal[AR5K_EEPROM_N_MODES];
761: u_int16_t ee_q_cal[AR5K_EEPROM_N_MODES];
762: u_int16_t ee_fixed_bias[AR5K_EEPROM_N_MODES];
763: u_int16_t ee_turbo_max_power[AR5K_EEPROM_N_MODES];
764: u_int16_t ee_xr_power[AR5K_EEPROM_N_MODES];
765: u_int16_t ee_switch_settling[AR5K_EEPROM_N_MODES];
766: u_int16_t ee_ant_tx_rx[AR5K_EEPROM_N_MODES];
767: u_int16_t ee_ant_control[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PCDAC];
768: u_int16_t ee_ob[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
769: u_int16_t ee_db[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
770: u_int16_t ee_tx_end2xlna_enable[AR5K_EEPROM_N_MODES];
771: u_int16_t ee_tx_end2xpa_disable[AR5K_EEPROM_N_MODES];
772: u_int16_t ee_tx_frm2xpa_enable[AR5K_EEPROM_N_MODES];
773: u_int16_t ee_thr_62[AR5K_EEPROM_N_MODES];
774: u_int16_t ee_xlna_gain[AR5K_EEPROM_N_MODES];
775: u_int16_t ee_xpd[AR5K_EEPROM_N_MODES];
776: u_int16_t ee_x_gain[AR5K_EEPROM_N_MODES];
777: u_int16_t ee_i_gain[AR5K_EEPROM_N_MODES];
778: u_int16_t ee_margin_tx_rx[AR5K_EEPROM_N_MODES];
779: u_int16_t ee_false_detect[AR5K_EEPROM_N_MODES];
780: u_int16_t ee_cal_pier[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_2GHZ_CHAN];
781: u_int16_t ee_channel[AR5K_EEPROM_N_MODES][AR5K_EEPROM_MAX_CHAN];
782:
783: u_int16_t ee_ctls;
784: u_int16_t ee_ctl[AR5K_EEPROM_MAX_CTLS];
785:
786: int16_t ee_noise_floor_thr[AR5K_EEPROM_N_MODES];
787: int8_t ee_adc_desired_size[AR5K_EEPROM_N_MODES];
788: int8_t ee_pga_desired_size[AR5K_EEPROM_N_MODES];
789: };
790:
791: /*
792: * Chipset capabilities
793: */
794:
795: typedef struct {
796: /*
797: * Supported PHY modes
798: * (ie. IEEE80211_CHAN_A, IEEE80211_CHAN_B, ...)
799: */
800: u_int16_t cap_mode;
801:
802: /*
803: * Frequency range (without regulation restrictions)
804: */
805: struct {
806: u_int16_t range_2ghz_min;
807: u_int16_t range_2ghz_max;
808: u_int16_t range_5ghz_min;
809: u_int16_t range_5ghz_max;
810: } cap_range;
811:
812: /*
813: * Active regulation domain settings
814: */
815: struct {
816: ieee80211_regdomain_t reg_current;
817: ieee80211_regdomain_t reg_hw;
818: } cap_regdomain;
819:
820: /*
821: * Values stored in the EEPROM (some of them...)
822: */
823: struct ar5k_eeprom_info cap_eeprom;
824:
825: /*
826: * Queue information
827: */
828: struct {
829: u_int8_t q_tx_num;
830: } cap_queues;
831: } ar5k_capabilities_t;
832:
833: /*
834: * TX power and TPC settings
835: */
836:
837: #define AR5K_TXPOWER_OFDM(_r, _v) ( \
838: ((0 & 1) << ((_v) + 6)) | \
839: (((hal->ah_txpower.txp_rates[(_r)]) & 0x3f) << (_v)) \
840: )
841:
842: #define AR5K_TXPOWER_CCK(_r, _v) ( \
843: (hal->ah_txpower.txp_rates[(_r)] & 0x3f) << (_v) \
844: )
845:
846: /*
847: * Atheros descriptor definitions
848: */
849:
850: struct ath_tx_status {
851: u_int16_t ts_seqnum;
852: u_int16_t ts_tstamp;
853: u_int8_t ts_status;
854: u_int8_t ts_rate;
855: int8_t ts_rssi;
856: u_int8_t ts_shortretry;
857: u_int8_t ts_longretry;
858: u_int8_t ts_virtcol;
859: u_int8_t ts_antenna;
860: };
861:
862: #define HAL_TXSTAT_ALTRATE 0x80
863: #define HAL_TXERR_XRETRY 0x01
864: #define HAL_TXERR_FILT 0x02
865: #define HAL_TXERR_FIFO 0x04
866:
867: struct ath_rx_status {
868: u_int16_t rs_datalen;
869: u_int16_t rs_tstamp;
870: u_int8_t rs_status;
871: u_int8_t rs_phyerr;
872: int8_t rs_rssi;
873: u_int8_t rs_keyix;
874: u_int8_t rs_rate;
875: u_int8_t rs_antenna;
876: u_int8_t rs_more;
877: };
878:
879: #define HAL_RXERR_CRC 0x01
880: #define HAL_RXERR_PHY 0x02
881: #define HAL_RXERR_FIFO 0x04
882: #define HAL_RXERR_DECRYPT 0x08
883: #define HAL_RXERR_MIC 0x10
884: #define HAL_RXKEYIX_INVALID ((u_int8_t) - 1)
885: #define HAL_TXKEYIX_INVALID ((u_int32_t) - 1)
886:
887: #define HAL_PHYERR_UNDERRUN 0x00
888: #define HAL_PHYERR_TIMING 0x01
889: #define HAL_PHYERR_PARITY 0x02
890: #define HAL_PHYERR_RATE 0x03
891: #define HAL_PHYERR_LENGTH 0x04
892: #define HAL_PHYERR_RADAR 0x05
893: #define HAL_PHYERR_SERVICE 0x06
894: #define HAL_PHYERR_TOR 0x07
895: #define HAL_PHYERR_OFDM_TIMING 0x11
896: #define HAL_PHYERR_OFDM_SIGNAL_PARITY 0x12
897: #define HAL_PHYERR_OFDM_RATE_ILLEGAL 0x13
898: #define HAL_PHYERR_OFDM_LENGTH_ILLEGAL 0x14
899: #define HAL_PHYERR_OFDM_POWER_DROP 0x15
900: #define HAL_PHYERR_OFDM_SERVICE 0x16
901: #define HAL_PHYERR_OFDM_RESTART 0x17
902: #define HAL_PHYERR_CCK_TIMING 0x19
903: #define HAL_PHYERR_CCK_HEADER_CRC 0x1a
904: #define HAL_PHYERR_CCK_RATE_ILLEGAL 0x1b
905: #define HAL_PHYERR_CCK_SERVICE 0x1e
906: #define HAL_PHYERR_CCK_RESTART 0x1f
907:
908: struct ath_desc {
909: u_int32_t ds_link;
910: u_int32_t ds_data;
911: u_int32_t ds_ctl0;
912: u_int32_t ds_ctl1;
913: u_int32_t ds_hw[4];
914:
915: union {
916: struct ath_rx_status rx;
917: struct ath_tx_status tx;
918: } ds_us;
919:
920: #define ds_rxstat ds_us.rx
921: #define ds_txstat ds_us.tx
922:
923: } __packed;
924:
925: #define HAL_RXDESC_INTREQ 0x0020
926:
927: #define HAL_TXDESC_CLRDMASK 0x0001
928: #define HAL_TXDESC_NOACK 0x0002
929: #define HAL_TXDESC_RTSENA 0x0004
930: #define HAL_TXDESC_CTSENA 0x0008
931: #define HAL_TXDESC_INTREQ 0x0010
932: #define HAL_TXDESC_VEOL 0x0020
933:
934: /*
935: * Hardware abstraction layer structure
936: */
937:
938: #define AR5K_HAL_FUNCTION(_hal, _n, _f) (_hal)->ah_##_f = ar5k_##_n##_##_f
939: #define AR5K_HAL_FUNCTIONS(_t, _n, _a) \
940: _t const HAL_RATE_TABLE *(_a _n##_get_rate_table)(struct ath_hal *, \
941: u_int mode); \
942: _t void (_a _n##_detach)(struct ath_hal *); \
943: /* Reset functions */ \
944: _t HAL_BOOL (_a _n##_reset)(struct ath_hal *, HAL_OPMODE, \
945: HAL_CHANNEL *, HAL_BOOL change_channel, HAL_STATUS *status); \
946: _t void (_a _n##_set_opmode)(struct ath_hal *); \
947: _t HAL_BOOL (_a _n##_calibrate)(struct ath_hal*, \
948: HAL_CHANNEL *); \
949: /* Transmit functions */ \
950: _t HAL_BOOL (_a _n##_update_tx_triglevel)(struct ath_hal*, \
951: HAL_BOOL level); \
952: _t int (_a _n##_setup_tx_queue)(struct ath_hal *, HAL_TX_QUEUE, \
953: const HAL_TXQ_INFO *); \
954: _t HAL_BOOL (_a _n##_setup_tx_queueprops)(struct ath_hal *, int queue, \
955: const HAL_TXQ_INFO *); \
956: _t HAL_BOOL (_a _n##_release_tx_queue)(struct ath_hal *, u_int queue); \
957: _t HAL_BOOL (_a _n##_reset_tx_queue)(struct ath_hal *, u_int queue); \
958: _t u_int32_t (_a _n##_get_tx_buf)(struct ath_hal *, u_int queue); \
959: _t HAL_BOOL (_a _n##_put_tx_buf)(struct ath_hal *, u_int, \
960: u_int32_t phys_addr); \
961: _t HAL_BOOL (_a _n##_tx_start)(struct ath_hal *, u_int queue); \
962: _t HAL_BOOL (_a _n##_stop_tx_dma)(struct ath_hal *, u_int queue); \
963: _t HAL_BOOL (_a _n##_setup_tx_desc)(struct ath_hal *, \
964: struct ath_desc *, \
965: u_int packet_length, u_int header_length, HAL_PKT_TYPE type, \
966: u_int txPower, u_int tx_rate0, u_int tx_tries0, u_int key_index, \
967: u_int antenna_mode, u_int flags, u_int rtscts_rate, \
968: u_int rtscts_duration); \
969: _t HAL_BOOL (_a _n##_setup_xtx_desc)(struct ath_hal *, \
970: struct ath_desc *, \
971: u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, \
972: u_int tx_rate3, u_int tx_tries3); \
973: _t HAL_BOOL (_a _n##_fill_tx_desc)(struct ath_hal *, \
974: struct ath_desc *, \
975: u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg); \
976: _t HAL_STATUS (_a _n##_proc_tx_desc)(struct ath_hal *, \
977: struct ath_desc *); \
978: _t HAL_BOOL (_a _n##_has_veol)(struct ath_hal *); \
979: /* Receive Functions */ \
980: _t u_int32_t (_a _n##_get_rx_buf)(struct ath_hal*); \
981: _t void (_a _n##_put_rx_buf)(struct ath_hal*, u_int32_t rxdp); \
982: _t void (_a _n##_start_rx)(struct ath_hal*); \
983: _t HAL_BOOL (_a _n##_stop_rx_dma)(struct ath_hal*); \
984: _t void (_a _n##_start_rx_pcu)(struct ath_hal*); \
985: _t void (_a _n##_stop_pcu_recv)(struct ath_hal*); \
986: _t void (_a _n##_set_mcast_filter)(struct ath_hal*, \
987: u_int32_t filter0, u_int32_t filter1); \
988: _t HAL_BOOL (_a _n##_set_mcast_filterindex)(struct ath_hal*, \
989: u_int32_t index); \
990: _t HAL_BOOL (_a _n##_clear_mcast_filter_idx)(struct ath_hal*, \
991: u_int32_t index); \
992: _t u_int32_t (_a _n##_get_rx_filter)(struct ath_hal*); \
993: _t void (_a _n##_set_rx_filter)(struct ath_hal*, u_int32_t); \
994: _t HAL_BOOL (_a _n##_setup_rx_desc)(struct ath_hal *, \
995: struct ath_desc *, u_int32_t size, u_int flags); \
996: _t HAL_STATUS (_a _n##_proc_rx_desc)(struct ath_hal *, \
997: struct ath_desc *, u_int32_t phyAddr, struct ath_desc *next); \
998: _t void (_a _n##_set_rx_signal)(struct ath_hal *); \
999: /* Misc Functions */ \
1000: _t void (_a _n##_dump_state)(struct ath_hal *); \
1001: _t HAL_BOOL (_a _n##_get_diag_state)(struct ath_hal *, int, void **, \
1002: u_int *); \
1003: _t void (_a _n##_get_lladdr)(struct ath_hal *, u_int8_t *); \
1004: _t HAL_BOOL (_a _n##_set_lladdr)(struct ath_hal *, \
1005: const u_int8_t*); \
1006: _t HAL_BOOL (_a _n##_set_regdomain)(struct ath_hal*, \
1007: u_int16_t, HAL_STATUS *); \
1008: _t void (_a _n##_set_ledstate)(struct ath_hal*, HAL_LED_STATE); \
1009: _t void (_a _n##_set_associd)(struct ath_hal*, \
1010: const u_int8_t *bssid, u_int16_t assocId, u_int16_t timOffset); \
1011: _t HAL_BOOL (_a _n##_set_gpio_output)(struct ath_hal *, \
1012: u_int32_t gpio); \
1013: _t HAL_BOOL (_a _n##_set_gpio_input)(struct ath_hal *, \
1014: u_int32_t gpio); \
1015: _t u_int32_t (_a _n##_get_gpio)(struct ath_hal *, u_int32_t gpio); \
1016: _t HAL_BOOL (_a _n##_set_gpio)(struct ath_hal *, u_int32_t gpio, \
1017: u_int32_t val); \
1018: _t void (_a _n##_set_gpio_intr)(struct ath_hal*, u_int, u_int32_t); \
1019: _t u_int32_t (_a _n##_get_tsf32)(struct ath_hal*); \
1020: _t u_int64_t (_a _n##_get_tsf64)(struct ath_hal*); \
1021: _t void (_a _n##_reset_tsf)(struct ath_hal*); \
1022: _t u_int16_t (_a _n##_get_regdomain)(struct ath_hal*); \
1023: _t HAL_BOOL (_a _n##_detect_card_present)(struct ath_hal*); \
1024: _t void (_a _n##_update_mib_counters)(struct ath_hal*, \
1025: HAL_MIB_STATS*); \
1026: _t HAL_BOOL (_a _n##_is_cipher_supported)(struct ath_hal*, \
1027: HAL_CIPHER); \
1028: _t HAL_RFGAIN (_a _n##_get_rf_gain)(struct ath_hal*); \
1029: _t HAL_BOOL (_a _n##_set_slot_time)(struct ath_hal*, u_int); \
1030: _t u_int (_a _n##_get_slot_time)(struct ath_hal*); \
1031: _t HAL_BOOL (_a _n##_set_ack_timeout)(struct ath_hal *, u_int); \
1032: _t u_int (_a _n##_get_ack_timeout)(struct ath_hal*); \
1033: _t HAL_BOOL (_a _n##_set_cts_timeout)(struct ath_hal*, u_int); \
1034: _t u_int (_a _n##_get_cts_timeout)(struct ath_hal*); \
1035: /* Key Cache Functions */ \
1036: _t u_int32_t (_a _n##_get_keycache_size)(struct ath_hal*); \
1037: _t HAL_BOOL (_a _n##_reset_key)(struct ath_hal*, \
1038: u_int16_t); \
1039: _t HAL_BOOL (_a _n##_is_key_valid)(struct ath_hal *, \
1040: u_int16_t); \
1041: _t HAL_BOOL (_a _n##_set_key)(struct ath_hal*, u_int16_t, \
1042: const HAL_KEYVAL *, const u_int8_t *, int); \
1043: _t HAL_BOOL (_a _n##_set_key_lladdr)(struct ath_hal*, \
1044: u_int16_t, const u_int8_t *); \
1045: /* Power Management Functions */ \
1046: _t HAL_BOOL (_a _n##_set_power)(struct ath_hal*, \
1047: HAL_POWER_MODE mode, \
1048: HAL_BOOL set_chip, u_int16_t sleep_duration); \
1049: _t HAL_POWER_MODE (_a _n##_get_power_mode)(struct ath_hal*); \
1050: _t HAL_BOOL (_a _n##_query_pspoll_support)(struct ath_hal*); \
1051: _t HAL_BOOL (_a _n##_init_pspoll)(struct ath_hal*); \
1052: _t HAL_BOOL (_a _n##_enable_pspoll)(struct ath_hal *, u_int8_t *, \
1053: u_int16_t); \
1054: _t HAL_BOOL (_a _n##_disable_pspoll)(struct ath_hal *); \
1055: /* Beacon Management Functions */ \
1056: _t void (_a _n##_init_beacon)(struct ath_hal *, u_int32_t nexttbtt, \
1057: u_int32_t intval); \
1058: _t void (_a _n##_set_beacon_timers)(struct ath_hal *, \
1059: const HAL_BEACON_STATE *, u_int32_t tsf, u_int32_t dtimCount, \
1060: u_int32_t cfpCcount); \
1061: _t void (_a _n##_reset_beacon)(struct ath_hal *); \
1062: _t HAL_BOOL (_a _n##_wait_for_beacon)(struct ath_hal *, \
1063: bus_addr_t); \
1064: /* Interrupt functions */ \
1065: _t HAL_BOOL (_a _n##_is_intr_pending)(struct ath_hal *); \
1066: _t HAL_BOOL (_a _n##_get_isr)(struct ath_hal *, \
1067: u_int32_t *); \
1068: _t u_int32_t (_a _n##_get_intr)(struct ath_hal *); \
1069: _t HAL_INT (_a _n##_set_intr)(struct ath_hal *, HAL_INT); \
1070: /* Chipset functions (ar5k-specific, non-HAL) */ \
1071: _t HAL_BOOL (_a _n##_get_capabilities)(struct ath_hal *); \
1072: _t void (_a _n##_radar_alert)(struct ath_hal *, HAL_BOOL enable); \
1073: _t HAL_BOOL (_a _n##_eeprom_is_busy)(struct ath_hal *); \
1074: _t int (_a _n##_eeprom_read)(struct ath_hal *, u_int32_t offset, \
1075: u_int16_t *data); \
1076: _t int (_a _n##_eeprom_write)(struct ath_hal *, u_int32_t offset, \
1077: u_int16_t data); \
1078: /* Unused functions */ \
1079: _t HAL_BOOL (_a _n##_get_tx_queueprops)(struct ath_hal *, int, \
1080: HAL_TXQ_INFO *); \
1081: _t u_int32_t (_a _n##_num_tx_pending)(struct ath_hal *, u_int); \
1082: _t HAL_BOOL (_a _n##_phy_disable)(struct ath_hal *); \
1083: _t HAL_BOOL (_a _n##_set_txpower_limit)(struct ath_hal *, u_int); \
1084: _t void (_a _n##_set_def_antenna)(struct ath_hal *, u_int); \
1085: _t u_int (_a _n ##_get_def_antenna)(struct ath_hal *); \
1086: _t HAL_BOOL (_a _n##_set_bssid_mask)(struct ath_hal *, \
1087: const u_int8_t*);
1088:
1089: #define AR5K_MAX_GPIO 10
1090: #define AR5K_MAX_RF_BANKS 8
1091:
1092: struct ath_hal {
1093: u_int32_t ah_magic;
1094: u_int32_t ah_abi;
1095: u_int16_t ah_device;
1096: u_int16_t ah_sub_vendor;
1097:
1098: void *ah_sc;
1099: bus_space_tag_t ah_st;
1100: bus_space_handle_t ah_sh;
1101:
1102: HAL_INT ah_imr;
1103:
1104: HAL_OPMODE ah_op_mode;
1105: HAL_POWER_MODE ah_power_mode;
1106: HAL_CHANNEL ah_current_channel;
1107: HAL_BOOL ah_turbo;
1108: HAL_BOOL ah_calibration;
1109: HAL_BOOL ah_running;
1110: HAL_BOOL ah_single_chip;
1111: HAL_RFGAIN ah_rf_gain;
1112:
1113: HAL_RATE_TABLE ah_rt_11a;
1114: HAL_RATE_TABLE ah_rt_11b;
1115: HAL_RATE_TABLE ah_rt_11g;
1116: HAL_RATE_TABLE ah_rt_turbo;
1117: HAL_RATE_TABLE ah_rt_xr;
1118:
1119: u_int32_t ah_mac_srev;
1120: u_int16_t ah_mac_version;
1121: u_int16_t ah_mac_revision;
1122: u_int16_t ah_phy_revision;
1123: u_int16_t ah_radio_5ghz_revision;
1124: u_int16_t ah_radio_2ghz_revision;
1125:
1126: enum ar5k_version ah_version;
1127: enum ar5k_radio ah_radio;
1128: u_int32_t ah_phy;
1129:
1130: HAL_BOOL ah_5ghz;
1131: HAL_BOOL ah_2ghz;
1132:
1133: #define ah_regdomain ah_capabilities.cap_regdomain.reg_current
1134: #define ah_regdomain_hw ah_capabilities.cap_regdomain.reg_hw
1135: #define ah_modes ah_capabilities.cap_mode
1136: #define ah_ee_version ah_capabilities.cap_eeprom.ee_version
1137:
1138: u_int32_t ah_atim_window;
1139: u_int32_t ah_aifs;
1140: u_int32_t ah_cw_min;
1141: u_int32_t ah_cw_max;
1142: HAL_BOOL ah_software_retry;
1143: u_int32_t ah_limit_tx_retries;
1144:
1145: u_int32_t ah_antenna[AR5K_EEPROM_N_MODES][HAL_ANT_MAX];
1146: HAL_BOOL ah_ant_diversity;
1147:
1148: u_int8_t ah_sta_id[IEEE80211_ADDR_LEN];
1149: u_int8_t ah_bssid[IEEE80211_ADDR_LEN];
1150:
1151: u_int32_t ah_gpio[AR5K_MAX_GPIO];
1152: int ah_gpio_npins;
1153:
1154: ar5k_capabilities_t ah_capabilities;
1155:
1156: HAL_TXQ_INFO ah_txq[HAL_NUM_TX_QUEUES];
1157: u_int32_t ah_txq_interrupts;
1158:
1159: u_int32_t *ah_rf_banks;
1160: size_t ah_rf_banks_size;
1161: struct ar5k_gain ah_gain;
1162: u_int32_t ah_offset[AR5K_MAX_RF_BANKS];
1163:
1164: struct {
1165: u_int16_t txp_pcdac[AR5K_EEPROM_POWER_TABLE_SIZE];
1166: u_int16_t txp_rates[AR5K_MAX_RATES];
1167: int16_t txp_min, txp_max;
1168: HAL_BOOL txp_tpc;
1169: int16_t txp_ofdm;
1170: } ah_txpower;
1171:
1172: struct {
1173: HAL_BOOL r_enabled;
1174: int r_last_alert;
1175: HAL_CHANNEL r_last_channel;
1176: } ah_radar;
1177:
1178: /*
1179: * Function pointers
1180: */
1181: AR5K_HAL_FUNCTIONS(, ah, *);
1182: };
1183:
1184: /*
1185: * Common silicon revision/version values
1186: */
1187: enum ar5k_srev_type {
1188: AR5K_VERSION_VER,
1189: AR5K_VERSION_REV,
1190: AR5K_VERSION_RAD,
1191: AR5K_VERSION_DEV,
1192: };
1193:
1194: struct ar5k_srev_name {
1195: const char *sr_name;
1196: enum ar5k_srev_type sr_type;
1197: u_int sr_val;
1198: };
1199:
1200: #define AR5K_SREV_NAME { \
1201: { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 }, \
1202: { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 }, \
1203: { "5311a", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },\
1204: { "5311b", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },\
1205: { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 }, \
1206: { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 }, \
1207: { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 }, \
1208: { "xxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN }, \
1209: { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 }, \
1210: { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, \
1211: { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, \
1212: { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, \
1213: { "5112a", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, \
1214: { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, \
1215: { "2112a", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, \
1216: { "xxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, \
1217: { "2413", AR5K_VERSION_DEV, AR5K_DEVID_AR2413 }, \
1218: { "5413", AR5K_VERSION_DEV, AR5K_DEVID_AR5413 }, \
1219: { "5424", AR5K_VERSION_DEV, AR5K_DEVID_AR5424 }, \
1220: { "xxxx", AR5K_VERSION_DEV, AR5K_SREV_UNKNOWN } \
1221: }
1222:
1223: #define AR5K_SREV_UNKNOWN 0xffff
1224:
1225: #define AR5K_SREV_VER_AR5210 0x00
1226: #define AR5K_SREV_VER_AR5311 0x10
1227: #define AR5K_SREV_VER_AR5311A 0x20
1228: #define AR5K_SREV_VER_AR5311B 0x30
1229: #define AR5K_SREV_VER_AR5211 0x40
1230: #define AR5K_SREV_VER_AR5212 0x50
1231: #define AR5K_SREV_VER_AR5213 0x55
1232: #define AR5K_SREV_VER_UNSUPP 0x60
1233:
1234: #define AR5K_SREV_RAD_5110 0x00
1235: #define AR5K_SREV_RAD_5111 0x10
1236: #define AR5K_SREV_RAD_5111A 0x15
1237: #define AR5K_SREV_RAD_2111 0x20
1238: #define AR5K_SREV_RAD_5112 0x30
1239: #define AR5K_SREV_RAD_5112A 0x35
1240: #define AR5K_SREV_RAD_2112 0x40
1241: #define AR5K_SREV_RAD_2112A 0x45
1242: #define AR5K_SREV_RAD_UNSUPP 0x50
1243:
1244: #define AR5K_DEVID_AR2413 0x001a
1245: #define AR5K_DEVID_AR5413 0x001b
1246: #define AR5K_DEVID_AR5424 0x001c
1247:
1248: /*
1249: * Misc defines
1250: */
1251:
1252: #define HAL_ABI_VERSION 0x04090901 /* YYMMDDnn */
1253:
1254: #define AR5K_PRINTF(fmt, ...) printf("%s: " fmt, __func__, ##__VA_ARGS__)
1255: #define AR5K_PRINT(fmt) printf("%s: " fmt, __func__)
1256: #ifdef AR5K_DEBUG
1257: #define AR5K_TRACE printf("%s:%d\n", __func__, __LINE__)
1258: #else
1259: #define AR5K_TRACE
1260: #endif
1261: #define AR5K_DELAY(_n) delay(_n)
1262: #define AR5K_ELEMENTS(_array) (sizeof(_array) / sizeof(_array[0]))
1263:
1264: typedef struct ath_hal * (ar5k_attach_t)
1265: (u_int16_t, void *, bus_space_tag_t, bus_space_handle_t, HAL_STATUS *);
1266: typedef HAL_BOOL (ar5k_rfgain_t)
1267: (struct ath_hal *, HAL_CHANNEL *, u_int);
1268:
1269: /*
1270: * Some tuneable values (these should be changeable by the user)
1271: */
1272:
1273: #define AR5K_TUNE_DMA_BEACON_RESP 2
1274: #define AR5K_TUNE_SW_BEACON_RESP 10
1275: #define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0
1276: #define AR5K_TUNE_RADAR_ALERT AH_FALSE
1277: #define AR5K_TUNE_MIN_TX_FIFO_THRES 1
1278: #define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_LEN / 64) + 1)
1279: #define AR5K_TUNE_RSSI_THRES 1792
1280: #define AR5K_TUNE_REGISTER_TIMEOUT 20000
1281: #define AR5K_TUNE_REGISTER_DWELL_TIME 20000
1282: #define AR5K_TUNE_BEACON_INTERVAL 100
1283: #define AR5K_TUNE_AIFS 2
1284: #define AR5K_TUNE_AIFS_11B 2
1285: #define AR5K_TUNE_AIFS_XR 0
1286: #define AR5K_TUNE_CWMIN 15
1287: #define AR5K_TUNE_CWMIN_11B 31
1288: #define AR5K_TUNE_CWMIN_XR 3
1289: #define AR5K_TUNE_CWMAX 1023
1290: #define AR5K_TUNE_CWMAX_11B 1023
1291: #define AR5K_TUNE_CWMAX_XR 7
1292: #define AR5K_TUNE_NOISE_FLOOR -72
1293: #define AR5K_TUNE_MAX_TXPOWER 60
1294: #define AR5K_TUNE_DEFAULT_TXPOWER 30
1295: #define AR5K_TUNE_TPC_TXPOWER AH_TRUE
1296: #define AR5K_TUNE_ANT_DIVERSITY AH_TRUE
1297: #define AR5K_TUNE_HWTXTRIES 4
1298:
1299: /* Default regulation domain if stored value EEPROM value is invalid */
1300: #define AR5K_TUNE_REGDOMAIN DMN_FCC2_FCCA /* Canada */
1301:
1302: /*
1303: * Common initial register values
1304: */
1305:
1306: #define AR5K_INIT_MODE ( \
1307: IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_DYN \
1308: )
1309: #define AR5K_INIT_TX_LATENCY 502
1310: #define AR5K_INIT_USEC 39
1311: #define AR5K_INIT_USEC_TURBO 79
1312: #define AR5K_INIT_USEC_32 31
1313: #define AR5K_INIT_CARR_SENSE_EN 1
1314: #define AR5K_INIT_PROG_IFS 920
1315: #define AR5K_INIT_PROG_IFS_TURBO 960
1316: #define AR5K_INIT_EIFS 3440
1317: #define AR5K_INIT_EIFS_TURBO 6880
1318: #define AR5K_INIT_SLOT_TIME 396
1319: #define AR5K_INIT_SLOT_TIME_TURBO 480
1320: #define AR5K_INIT_ACK_CTS_TIMEOUT 1024
1321: #define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800
1322: #define AR5K_INIT_SIFS 560
1323: #define AR5K_INIT_SIFS_TURBO 480
1324: #define AR5K_INIT_SH_RETRY 10
1325: #define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY
1326: #define AR5K_INIT_SSH_RETRY 32
1327: #define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY
1328: #define AR5K_INIT_TX_RETRY 10
1329: #define AR5K_INIT_TOPS 8
1330: #define AR5K_INIT_RXNOFRM 8
1331: #define AR5K_INIT_RPGTO 0
1332: #define AR5K_INIT_TXNOFRM 0
1333: #define AR5K_INIT_BEACON_PERIOD 65535
1334: #define AR5K_INIT_TIM_OFFSET 0
1335: #define AR5K_INIT_BEACON_EN 0
1336: #define AR5K_INIT_RESET_TSF 0
1337: #define AR5K_INIT_TRANSMIT_LATENCY ( \
1338: (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
1339: (AR5K_INIT_USEC) \
1340: )
1341: #define AR5K_INIT_TRANSMIT_LATENCY_TURBO ( \
1342: (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
1343: (AR5K_INIT_USEC_TURBO) \
1344: )
1345: #define AR5K_INIT_PROTO_TIME_CNTRL ( \
1346: (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \
1347: (AR5K_INIT_PROG_IFS) \
1348: )
1349: #define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \
1350: (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) |\
1351: (AR5K_INIT_PROG_IFS_TURBO) \
1352: )
1353: #define AR5K_INIT_BEACON_CONTROL ( \
1354: (AR5K_INIT_RESET_TSF << 24) | (AR5K_INIT_BEACON_EN << 23) | \
1355: (AR5K_INIT_TIM_OFFSET << 16) | (AR5K_INIT_BEACON_PERIOD) \
1356: )
1357:
1358: /*
1359: * AR5k register access
1360: */
1361:
1362: #define AR5K_REG_WRITE(_reg, _val) \
1363: bus_space_write_4(hal->ah_st, hal->ah_sh, (_reg), (_val))
1364: #define AR5K_REG_READ(_reg) \
1365: bus_space_read_4(hal->ah_st, hal->ah_sh, (_reg))
1366:
1367: #define AR5K_REG_SM(_val, _flags) \
1368: (((_val) << _flags##_S) & (_flags))
1369: #define AR5K_REG_MS(_val, _flags) \
1370: (((_val) & (_flags)) >> _flags##_S)
1371: #define AR5K_REG_WRITE_BITS(_reg, _flags, _val) \
1372: AR5K_REG_WRITE(_reg, (AR5K_REG_READ(_reg) &~ (_flags)) | \
1373: (((_val) << _flags##_S) & (_flags)))
1374: #define AR5K_REG_MASKED_BITS(_reg, _flags, _mask) \
1375: AR5K_REG_WRITE(_reg, (AR5K_REG_READ(_reg) & (_mask)) | (_flags))
1376: #define AR5K_REG_ENABLE_BITS(_reg, _flags) \
1377: AR5K_REG_WRITE(_reg, AR5K_REG_READ(_reg) | (_flags))
1378: #define AR5K_REG_DISABLE_BITS(_reg, _flags) \
1379: AR5K_REG_WRITE(_reg, AR5K_REG_READ(_reg) &~ (_flags))
1380:
1381: #define AR5K_PHY_WRITE(_reg, _val) \
1382: AR5K_REG_WRITE(hal->ah_phy + ((_reg) << 2), _val)
1383: #define AR5K_PHY_READ(_reg) \
1384: AR5K_REG_READ(hal->ah_phy + ((_reg) << 2))
1385:
1386: #define AR5K_REG_WAIT(_i) \
1387: if (_i % 64) \
1388: AR5K_DELAY(1);
1389:
1390: #define AR5K_EEPROM_READ(_o, _v) { \
1391: if ((ret = hal->ah_eeprom_read(hal, (_o), \
1392: &(_v))) != 0) \
1393: return (ret); \
1394: }
1395: #define AR5K_EEPROM_READ_HDR(_o, _v) \
1396: AR5K_EEPROM_READ(_o, hal->ah_capabilities.cap_eeprom._v); \
1397:
1398: /* Read status of selected queue */
1399: #define AR5K_REG_READ_Q(_reg, _queue) \
1400: (AR5K_REG_READ(_reg) & (1 << _queue)) \
1401:
1402: #define AR5K_REG_WRITE_Q(_reg, _queue) \
1403: AR5K_REG_WRITE(_reg, (1 << _queue))
1404:
1405: #define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \
1406: _reg |= 1 << _queue; \
1407: } while (0)
1408:
1409: #define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \
1410: _reg &= ~(1 << _queue); \
1411: } while (0)
1412:
1413: #define AR5K_LOW_ID(_a) ( \
1414: (_a)[0] | (_a)[1] << 8 | (_a)[2] << 16 | (_a)[3] << 24 \
1415: )
1416: #define AR5K_HIGH_ID(_a) ((_a)[4] | (_a)[5] << 8)
1417:
1418: /*
1419: * Unaligned little endian access
1420: */
1421:
1422: #define AR5K_LE_READ_2(_p) \
1423: (((const u_int8_t *)(_p))[0] | (((const u_int8_t *)(_p))[1] << 8))
1424: #define AR5K_LE_READ_4(_p) \
1425: (((const u_int8_t *)(_p))[0] | \
1426: (((const u_int8_t *)(_p))[1] << 8) | \
1427: (((const u_int8_t *)(_p))[2] << 16) | \
1428: (((const u_int8_t *)(_p))[3] << 24))
1429: #define AR5K_LE_WRITE_2(_p, _val) \
1430: ((((u_int8_t *)(_p))[0] = ((u_int32_t)(_val) & 0xff)), \
1431: (((u_int8_t *)(_p))[1] = (((u_int32_t)(_val) >> 8) & 0xff)))
1432: #define AR5K_LE_WRITE_4(_p, _val) \
1433: ((((u_int8_t *)(_p))[0] = ((u_int32_t)(_val) & 0xff)), \
1434: (((u_int8_t *)(_p))[1] = (((u_int32_t)(_val) >> 8) & 0xff)), \
1435: (((u_int8_t *)(_p))[2] = (((u_int32_t)(_val) >> 16) & 0xff)), \
1436: (((u_int8_t *)(_p))[3] = (((u_int32_t)(_val) >> 24) & 0xff)))
1437:
1438: /*
1439: * Initial register values
1440: */
1441:
1442: struct ar5k_ini {
1443: u_int16_t ini_register;
1444: u_int32_t ini_value;
1445:
1446: enum {
1447: AR5K_INI_WRITE = 0,
1448: AR5K_INI_READ = 1,
1449: } ini_mode;
1450: };
1451:
1452: #define AR5K_INI_VAL_11A 0
1453: #define AR5K_INI_VAL_11A_TURBO 1
1454: #define AR5K_INI_VAL_11B 2
1455: #define AR5K_INI_VAL_11G 3
1456: #define AR5K_INI_VAL_11G_TURBO 4
1457: #define AR5K_INI_VAL_XR 0
1458: #define AR5K_INI_VAL_MAX 5
1459:
1460: #define AR5K_INI_PHY_5111 0
1461: #define AR5K_INI_PHY_5112 1
1462: #define AR5K_INI_PHY_511X 1
1463:
1464: #define AR5K_AR5111_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS
1465: #define AR5K_AR5112_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS
1466:
1467: struct ar5k_ini_rf {
1468: u_int8_t rf_bank;
1469: u_int16_t rf_register;
1470: u_int32_t rf_value[5];
1471: };
1472:
1473: #define AR5K_AR5111_INI_RF { \
1474: { 0, 0x989c, \
1475: { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1476: { 0, 0x989c, \
1477: { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1478: { 0, 0x989c, \
1479: { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1480: { 0, 0x989c, \
1481: { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1482: { 0, 0x989c, \
1483: { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1484: { 0, 0x989c, \
1485: { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1486: { 0, 0x989c, \
1487: { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1488: { 0, 0x989c, \
1489: { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1490: { 0, 0x989c, \
1491: { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1492: { 0, 0x989c, \
1493: { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1494: { 0, 0x989c, \
1495: { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1496: { 0, 0x989c, \
1497: { 0x00380000, 0x00380000, 0x00380000, 0x00380000, 0x00380000 } }, \
1498: { 0, 0x989c, \
1499: { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1500: { 0, 0x989c, \
1501: { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1502: { 0, 0x989c, \
1503: { 0x00000000, 0x00000000, 0x000000c0, 0x00000080, 0x00000080 } }, \
1504: { 0, 0x989c, \
1505: { 0x000400f9, 0x000400f9, 0x000400ff, 0x000400fd, 0x000400fd } }, \
1506: { 0, 0x98d4, \
1507: { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } }, \
1508: { 1, 0x98d4, \
1509: { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \
1510: { 2, 0x98d4, \
1511: { 0x00000010, 0x00000014, 0x00000010, 0x00000010, 0x00000014 } }, \
1512: { 3, 0x98d8, \
1513: { 0x00601068, 0x00601068, 0x00601068, 0x00601068, 0x00601068 } }, \
1514: { 6, 0x989c, \
1515: { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1516: { 6, 0x989c, \
1517: { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1518: { 6, 0x989c, \
1519: { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1520: { 6, 0x989c, \
1521: { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1522: { 6, 0x989c, \
1523: { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1524: { 6, 0x989c, \
1525: { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } }, \
1526: { 6, 0x989c, \
1527: { 0x04000000, 0x04000000, 0x04000000, 0x04000000, 0x04000000 } }, \
1528: { 6, 0x989c, \
1529: { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1530: { 6, 0x989c, \
1531: { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1532: { 6, 0x989c, \
1533: { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1534: { 6, 0x989c, \
1535: { 0x00000000, 0x00000000, 0x0a000000, 0x00000000, 0x00000000 } }, \
1536: { 6, 0x989c, \
1537: { 0x003800c0, 0x00380080, 0x023800c0, 0x003800c0, 0x003800c0 } }, \
1538: { 6, 0x989c, \
1539: { 0x00020006, 0x00020006, 0x00000006, 0x00020006, 0x00020006 } }, \
1540: { 6, 0x989c, \
1541: { 0x00000089, 0x00000089, 0x00000089, 0x00000089, 0x00000089 } }, \
1542: { 6, 0x989c, \
1543: { 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0 } }, \
1544: { 6, 0x989c, \
1545: { 0x00040007, 0x00040007, 0x00040007, 0x00040007, 0x00040007 } }, \
1546: { 6, 0x98d4, \
1547: { 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a } }, \
1548: { 7, 0x989c, \
1549: { 0x00000040, 0x00000048, 0x00000040, 0x00000040, 0x00000040 } }, \
1550: { 7, 0x989c, \
1551: { 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 } }, \
1552: { 7, 0x989c, \
1553: { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } }, \
1554: { 7, 0x989c, \
1555: { 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f } }, \
1556: { 7, 0x989c, \
1557: { 0x000000f1, 0x000000f1, 0x00000061, 0x000000f1, 0x000000f1 } }, \
1558: { 7, 0x989c, \
1559: { 0x0000904f, 0x0000904f, 0x0000904c, 0x0000904f, 0x0000904f } }, \
1560: { 7, 0x989c, \
1561: { 0x0000125a, 0x0000125a, 0x0000129a, 0x0000125a, 0x0000125a } }, \
1562: { 7, 0x98cc, \
1563: { 0x0000000e, 0x0000000e, 0x0000000f, 0x0000000e, 0x0000000e } }, \
1564: }
1565:
1566: #define AR5K_AR5112_INI_RF { \
1567: { 1, 0x98d4, \
1568: { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \
1569: { 2, 0x98d0, \
1570: { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } }, \
1571: { 3, 0x98dc, \
1572: { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } }, \
1573: { 6, 0x989c, \
1574: { 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000 } }, \
1575: { 6, 0x989c, \
1576: { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } }, \
1577: { 6, 0x989c, \
1578: { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1579: { 6, 0x989c, \
1580: { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1581: { 6, 0x989c, \
1582: { 0x00660000, 0x00660000, 0x00660000, 0x00660000, 0x00660000 } }, \
1583: { 6, 0x989c, \
1584: { 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000 } }, \
1585: { 6, 0x989c, \
1586: { 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000 } }, \
1587: { 6, 0x989c, \
1588: { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, \
1589: { 6, 0x989c, \
1590: { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, \
1591: { 6, 0x989c, \
1592: { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } }, \
1593: { 6, 0x989c, \
1594: { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1595: { 6, 0x989c, \
1596: { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, \
1597: { 6, 0x989c, \
1598: { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \
1599: { 6, 0x989c, \
1600: { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \
1601: { 6, 0x989c, \
1602: { 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000 } }, \
1603: { 6, 0x989c, \
1604: { 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000 } }, \
1605: { 6, 0x989c, \
1606: { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, \
1607: { 6, 0x989c, \
1608: { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } }, \
1609: { 6, 0x989c, \
1610: { 0x00640000, 0x00640000, 0x00640000, 0x00640000, 0x00640000 } }, \
1611: { 6, 0x989c, \
1612: { 0x00200000, 0x00200000, 0x00200000, 0x00200000, 0x00200000 } }, \
1613: { 6, 0x989c, \
1614: { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } }, \
1615: { 6, 0x989c, \
1616: { 0x00250000, 0x00250000, 0x00250000, 0x00250000, 0x00250000 } }, \
1617: { 6, 0x989c, \
1618: { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, \
1619: { 6, 0x989c, \
1620: { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, \
1621: { 6, 0x989c, \
1622: { 0x00510000, 0x00510000, 0x00510000, 0x00510000, 0x00510000 } }, \
1623: { 6, 0x989c, \
1624: { 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000 } }, \
1625: { 6, 0x989c, \
1626: { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } }, \
1627: { 6, 0x989c, \
1628: { 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000 } }, \
1629: { 6, 0x989c, \
1630: { 0x00400000, 0x00400000, 0x00400000, 0x00400000, 0x00400000 } }, \
1631: { 6, 0x989c, \
1632: { 0x03090000, 0x03090000, 0x03090000, 0x03090000, 0x03090000 } }, \
1633: { 6, 0x989c, \
1634: { 0x06000000, 0x06000000, 0x06000000, 0x06000000, 0x06000000 } }, \
1635: { 6, 0x989c, \
1636: { 0x000000b0, 0x000000b0, 0x000000a8, 0x000000a8, 0x000000a8 } }, \
1637: { 6, 0x989c, \
1638: { 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e } }, \
1639: { 6, 0x989c, \
1640: { 0x006c4a41, 0x006c4a41, 0x006c4af1, 0x006c4a61, 0x006c4a61 } }, \
1641: { 6, 0x989c, \
1642: { 0x0050892a, 0x0050892a, 0x0050892b, 0x0050892b, 0x0050892b } }, \
1643: { 6, 0x989c, \
1644: { 0x00842400, 0x00842400, 0x00842400, 0x00842400, 0x00842400 } }, \
1645: { 6, 0x989c, \
1646: { 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200 } }, \
1647: { 6, 0x98d0, \
1648: { 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c } }, \
1649: { 7, 0x989c, \
1650: { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } }, \
1651: { 7, 0x989c, \
1652: { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } }, \
1653: { 7, 0x989c, \
1654: { 0x0000000a, 0x0000000a, 0x00000012, 0x00000012, 0x00000012 } }, \
1655: { 7, 0x989c, \
1656: { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } }, \
1657: { 7, 0x989c, \
1658: { 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1 } }, \
1659: { 7, 0x989c, \
1660: { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } }, \
1661: { 7, 0x989c, \
1662: { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } }, \
1663: { 7, 0x989c, \
1664: { 0x00000022, 0x00000022, 0x00000022, 0x00000022, 0x00000022 } }, \
1665: { 7, 0x989c, \
1666: { 0x00000092, 0x00000092, 0x00000092, 0x00000092, 0x00000092 } }, \
1667: { 7, 0x989c, \
1668: { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } }, \
1669: { 7, 0x989c, \
1670: { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } }, \
1671: { 7, 0x989c, \
1672: { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } }, \
1673: { 7, 0x98c4, \
1674: { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \
1675: }
1676:
1677: #define AR5K_AR5112A_INI_RF { \
1678: { 1, 0x98d4, \
1679: { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \
1680: { 2, 0x98d0, \
1681: { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } }, \
1682: { 3, 0x98dc, \
1683: { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } }, \
1684: { 6, 0x989c, \
1685: { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } }, \
1686: { 6, 0x989c, \
1687: { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1688: { 6, 0x989c, \
1689: { 0x00800000, 0x00800000, 0x00800000, 0x00800000, 0x00800000 } }, \
1690: { 6, 0x989c, \
1691: { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } }, \
1692: { 6, 0x989c, \
1693: { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } }, \
1694: { 6, 0x989c, \
1695: { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1696: { 6, 0x989c, \
1697: { 0x00180000, 0x00180000, 0x00180000, 0x00180000, 0x00180000 } }, \
1698: { 6, 0x989c, \
1699: { 0x00600000, 0x00600000, 0x006e0000, 0x006e0000, 0x006e0000 } }, \
1700: { 6, 0x989c, \
1701: { 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000 } }, \
1702: { 6, 0x989c, \
1703: { 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000 } }, \
1704: { 6, 0x989c, \
1705: { 0x04480000, 0x04480000, 0x04480000, 0x04480000, 0x04480000 } }, \
1706: { 6, 0x989c, \
1707: { 0x00220000, 0x00220000, 0x00220000, 0x00220000, 0x00220000 } }, \
1708: { 6, 0x989c, \
1709: { 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000 } }, \
1710: { 6, 0x989c, \
1711: { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1712: { 6, 0x989c, \
1713: { 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000 } }, \
1714: { 6, 0x989c, \
1715: { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \
1716: { 6, 0x989c, \
1717: { 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000 } }, \
1718: { 6, 0x989c, \
1719: { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, \
1720: { 6, 0x989c, \
1721: { 0x00190000, 0x00190000, 0x00190000, 0x00190000, 0x00190000 } }, \
1722: { 6, 0x989c, \
1723: { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } }, \
1724: { 6, 0x989c, \
1725: { 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000 } }, \
1726: { 6, 0x989c, \
1727: { 0x00990000, 0x00990000, 0x00990000, 0x00990000, 0x00990000 } }, \
1728: { 6, 0x989c, \
1729: { 0x00500000, 0x00500000, 0x00500000, 0x00500000, 0x00500000 } }, \
1730: { 6, 0x989c, \
1731: { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } }, \
1732: { 6, 0x989c, \
1733: { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, \
1734: { 6, 0x989c, \
1735: { 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000 } }, \
1736: { 6, 0x989c, \
1737: { 0x01740000, 0x01740000, 0x01740000, 0x01740000, 0x01740000 } }, \
1738: { 6, 0x989c, \
1739: { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, \
1740: { 6, 0x989c, \
1741: { 0x86280000, 0x86280000, 0x86280000, 0x86280000, 0x86280000 } }, \
1742: { 6, 0x989c, \
1743: { 0x31840000, 0x31840000, 0x31840000, 0x31840000, 0x31840000 } }, \
1744: { 6, 0x989c, \
1745: { 0x00020080, 0x00020080, 0x00020080, 0x00020080, 0x00020080 } }, \
1746: { 6, 0x989c, \
1747: { 0x00080009, 0x00080009, 0x00080009, 0x00080009, 0x00080009 } }, \
1748: { 6, 0x989c, \
1749: { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \
1750: { 6, 0x989c, \
1751: { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1752: { 6, 0x989c, \
1753: { 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2 } }, \
1754: { 6, 0x989c, \
1755: { 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084 } }, \
1756: { 6, 0x989c, \
1757: { 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4 } }, \
1758: { 6, 0x989c, \
1759: { 0x00119220, 0x00119220, 0x00119220, 0x00119220, 0x00119220 } }, \
1760: { 6, 0x989c, \
1761: { 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800 } }, \
1762: { 6, 0x98d8, \
1763: { 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230 } }, \
1764: { 7, 0x989c, \
1765: { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } }, \
1766: { 7, 0x989c, \
1767: { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } }, \
1768: { 7, 0x989c, \
1769: { 0x00000012, 0x00000012, 0x00000012, 0x00000012, 0x00000012 } }, \
1770: { 7, 0x989c, \
1771: { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } }, \
1772: { 7, 0x989c, \
1773: { 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9 } }, \
1774: { 7, 0x989c, \
1775: { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } }, \
1776: { 7, 0x989c, \
1777: { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } }, \
1778: { 7, 0x989c, \
1779: { 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2 } }, \
1780: { 7, 0x989c, \
1781: { 0x00000052, 0x00000052, 0x00000052, 0x00000052, 0x00000052 } }, \
1782: { 7, 0x989c, \
1783: { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } }, \
1784: { 7, 0x989c, \
1785: { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } }, \
1786: { 7, 0x989c, \
1787: { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } }, \
1788: { 7, 0x98c4, \
1789: { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \
1790: }
1791:
1792: struct ar5k_ini_rfgain {
1793: u_int16_t rfg_register;
1794: u_int32_t rfg_value[2][2];
1795:
1796: #define AR5K_INI_RFGAIN_5GHZ 0
1797: #define AR5K_INI_RFGAIN_2GHZ 1
1798: };
1799:
1800: #define AR5K_INI_RFGAIN { \
1801: { 0x9a00, { \
1802: { 0x000001a9, 0x00000000 }, { 0x00000007, 0x00000007 } } }, \
1803: { 0x9a04, { \
1804: { 0x000001e9, 0x00000040 }, { 0x00000047, 0x00000047 } } }, \
1805: { 0x9a08, { \
1806: { 0x00000029, 0x00000080 }, { 0x00000087, 0x00000087 } } }, \
1807: { 0x9a0c, { \
1808: { 0x00000069, 0x00000150 }, { 0x000001a0, 0x000001a0 } } }, \
1809: { 0x9a10, { \
1810: { 0x00000199, 0x00000190 }, { 0x000001e0, 0x000001e0 } } }, \
1811: { 0x9a14, { \
1812: { 0x000001d9, 0x000001d0 }, { 0x00000020, 0x00000020 } } }, \
1813: { 0x9a18, { \
1814: { 0x00000019, 0x00000010 }, { 0x00000060, 0x00000060 } } }, \
1815: { 0x9a1c, { \
1816: { 0x00000059, 0x00000044 }, { 0x000001a1, 0x000001a1 } } }, \
1817: { 0x9a20, { \
1818: { 0x00000099, 0x00000084 }, { 0x000001e1, 0x000001e1 } } }, \
1819: { 0x9a24, { \
1820: { 0x000001a5, 0x00000148 }, { 0x00000021, 0x00000021 } } }, \
1821: { 0x9a28, { \
1822: { 0x000001e5, 0x00000188 }, { 0x00000061, 0x00000061 } } }, \
1823: { 0x9a2c, { \
1824: { 0x00000025, 0x000001c8 }, { 0x00000162, 0x00000162 } } }, \
1825: { 0x9a30, { \
1826: { 0x000001c8, 0x00000014 }, { 0x000001a2, 0x000001a2 } } }, \
1827: { 0x9a34, { \
1828: { 0x00000008, 0x00000042 }, { 0x000001e2, 0x000001e2 } } }, \
1829: { 0x9a38, { \
1830: { 0x00000048, 0x00000082 }, { 0x00000022, 0x00000022 } } }, \
1831: { 0x9a3c, { \
1832: { 0x00000088, 0x00000178 }, { 0x00000062, 0x00000062 } } }, \
1833: { 0x9a40, { \
1834: { 0x00000198, 0x000001b8 }, { 0x00000163, 0x00000163 } } }, \
1835: { 0x9a44, { \
1836: { 0x000001d8, 0x000001f8 }, { 0x000001a3, 0x000001a3 } } }, \
1837: { 0x9a48, { \
1838: { 0x00000018, 0x00000012 }, { 0x000001e3, 0x000001e3 } } }, \
1839: { 0x9a4c, { \
1840: { 0x00000058, 0x00000052 }, { 0x00000023, 0x00000023 } } }, \
1841: { 0x9a50, { \
1842: { 0x00000098, 0x00000092 }, { 0x00000063, 0x00000063 } } }, \
1843: { 0x9a54, { \
1844: { 0x000001a4, 0x0000017c }, { 0x00000184, 0x00000184 } } }, \
1845: { 0x9a58, { \
1846: { 0x000001e4, 0x000001bc }, { 0x000001c4, 0x000001c4 } } }, \
1847: { 0x9a5c, { \
1848: { 0x00000024, 0x000001fc }, { 0x00000004, 0x00000004 } } }, \
1849: { 0x9a60, { \
1850: { 0x00000064, 0x0000000a }, { 0x000001ea, 0x0000000b } } }, \
1851: { 0x9a64, { \
1852: { 0x000000a4, 0x0000004a }, { 0x0000002a, 0x0000004b } } }, \
1853: { 0x9a68, { \
1854: { 0x000000e4, 0x0000008a }, { 0x0000006a, 0x0000008b } } }, \
1855: { 0x9a6c, { \
1856: { 0x0000010a, 0x0000015a }, { 0x000000aa, 0x000001ac } } }, \
1857: { 0x9a70, { \
1858: { 0x0000014a, 0x0000019a }, { 0x000001ab, 0x000001ec } } }, \
1859: { 0x9a74, { \
1860: { 0x0000018a, 0x000001da }, { 0x000001eb, 0x0000002c } } }, \
1861: { 0x9a78, { \
1862: { 0x000001ca, 0x0000000e }, { 0x0000002b, 0x00000012 } } }, \
1863: { 0x9a7c, { \
1864: { 0x0000000a, 0x0000004e }, { 0x0000006b, 0x00000052 } } }, \
1865: { 0x9a80, { \
1866: { 0x0000004a, 0x0000008e }, { 0x000000ab, 0x00000092 } } }, \
1867: { 0x9a84, { \
1868: { 0x0000008a, 0x0000015e }, { 0x000001ac, 0x00000193 } } }, \
1869: { 0x9a88, { \
1870: { 0x000001ba, 0x0000019e }, { 0x000001ec, 0x000001d3 } } }, \
1871: { 0x9a8c, { \
1872: { 0x000001fa, 0x000001de }, { 0x0000002c, 0x00000013 } } }, \
1873: { 0x9a90, { \
1874: { 0x0000003a, 0x00000009 }, { 0x0000003a, 0x00000053 } } }, \
1875: { 0x9a94, { \
1876: { 0x0000007a, 0x00000049 }, { 0x0000007a, 0x00000093 } } }, \
1877: { 0x9a98, { \
1878: { 0x00000186, 0x00000089 }, { 0x000000ba, 0x00000194 } } }, \
1879: { 0x9a9c, { \
1880: { 0x000001c6, 0x00000179 }, { 0x000001bb, 0x000001d4 } } }, \
1881: { 0x9aa0, { \
1882: { 0x00000006, 0x000001b9 }, { 0x000001fb, 0x00000014 } } }, \
1883: { 0x9aa4, { \
1884: { 0x00000046, 0x000001f9 }, { 0x0000003b, 0x0000003a } } }, \
1885: { 0x9aa8, { \
1886: { 0x00000086, 0x00000039 }, { 0x0000007b, 0x0000007a } } }, \
1887: { 0x9aac, { \
1888: { 0x000000c6, 0x00000079 }, { 0x000000bb, 0x000000ba } } }, \
1889: { 0x9ab0, { \
1890: { 0x000000c6, 0x000000b9 }, { 0x000001bc, 0x000001bb } } }, \
1891: { 0x9ab4, { \
1892: { 0x000000c6, 0x000001bd }, { 0x000001fc, 0x000001fb } } }, \
1893: { 0x9ab8, { \
1894: { 0x000000c6, 0x000001fd }, { 0x0000003c, 0x0000003b } } }, \
1895: { 0x9abc, { \
1896: { 0x000000c6, 0x0000003d }, { 0x0000007c, 0x0000007b } } }, \
1897: { 0x9ac0, { \
1898: { 0x000000c6, 0x0000007d }, { 0x000000bc, 0x000000bb } } }, \
1899: { 0x9ac4, { \
1900: { 0x000000c6, 0x000000bd }, { 0x000000fc, 0x000001bc } } }, \
1901: { 0x9ac8, { \
1902: { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000001fc } } }, \
1903: { 0x9acc, { \
1904: { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x0000003c } } }, \
1905: { 0x9ad0, { \
1906: { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x0000007c } } }, \
1907: { 0x9ad4, { \
1908: { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000bc } } }, \
1909: { 0x9ad8, { \
1910: { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \
1911: { 0x9adc, { \
1912: { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \
1913: { 0x9ae0, { \
1914: { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \
1915: { 0x9ae4, { \
1916: { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \
1917: { 0x9ae8, { \
1918: { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \
1919: { 0x9aec, { \
1920: { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \
1921: { 0x9af0, { \
1922: { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \
1923: { 0x9af4, { \
1924: { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \
1925: { 0x9af8, { \
1926: { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \
1927: { 0x9afc, { \
1928: { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \
1929: }
1930:
1931: /*
1932: * Prototypes
1933: */
1934:
1935: __BEGIN_DECLS
1936:
1937: const char *ath_hal_probe(u_int16_t, u_int16_t);
1938:
1939: struct ath_hal *ath_hal_attach(u_int16_t, void *, bus_space_tag_t,
1940: bus_space_handle_t, u_int, HAL_STATUS *);
1941:
1942: u_int16_t ath_hal_computetxtime(struct ath_hal *,
1943: const HAL_RATE_TABLE *, u_int32_t, u_int16_t, HAL_BOOL);
1944:
1945: HAL_BOOL ath_hal_init_channels(struct ath_hal *, HAL_CHANNEL *,
1946: u_int, u_int *, u_int16_t, HAL_BOOL, HAL_BOOL);
1947:
1948: const char *ar5k_printver(enum ar5k_srev_type, u_int32_t);
1949: void ar5k_radar_alert(struct ath_hal *);
1950: ieee80211_regdomain_t ar5k_regdomain_to_ieee(u_int16_t);
1951: u_int16_t ar5k_regdomain_from_ieee(ieee80211_regdomain_t);
1952: u_int16_t ar5k_get_regdomain(struct ath_hal *);
1953:
1954: u_int32_t ar5k_bitswap(u_int32_t, u_int);
1955: u_int ar5k_clocktoh(u_int, HAL_BOOL);
1956: u_int ar5k_htoclock(u_int, HAL_BOOL);
1957: void ar5k_rt_copy(HAL_RATE_TABLE *, const HAL_RATE_TABLE *);
1958:
1959: HAL_BOOL ar5k_register_timeout(struct ath_hal *, u_int32_t,
1960: u_int32_t, u_int32_t, HAL_BOOL);
1961:
1962: int ar5k_eeprom_init(struct ath_hal *);
1963: int ar5k_eeprom_read_mac(struct ath_hal *, u_int8_t *);
1964: HAL_BOOL ar5k_eeprom_regulation_domain(struct ath_hal *,
1965: HAL_BOOL, ieee80211_regdomain_t *);
1966:
1967: HAL_BOOL ar5k_channel(struct ath_hal *, HAL_CHANNEL *);
1968: HAL_BOOL ar5k_rfregs(struct ath_hal *, HAL_CHANNEL *, u_int);
1969: u_int32_t ar5k_rfregs_gainf_corr(struct ath_hal *);
1970: HAL_BOOL ar5k_rfregs_gain_readback(struct ath_hal *);
1971: int32_t ar5k_rfregs_gain_adjust(struct ath_hal *);
1972: HAL_BOOL ar5k_rfgain(struct ath_hal *, u_int, u_int);
1973:
1974: void ar5k_txpower_table(struct ath_hal *, HAL_CHANNEL *,
1975: int16_t);
1976:
1977: __END_DECLS
1978:
1979: #endif /* _AR5K_H */
CVSweb
![[BACK]](/icons/back.gif){kind=icon}
Return to ar5xxx.h CVS log ![[TXT]](/icons/text.gif){kind=icon}
![[DIR]](/icons/dir.gif){kind=icon}
Up to [local] / sys / dev / ic