Annotation of sys/dev/ic/ar5211reg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: ar5211reg.h,v 1.11 2007/03/12 01:04:52 reyk Exp $ */
2:
3: /*
4: * Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <reyk@openbsd.org>
5: *
6: * Permission to use, copy, modify, and distribute this software for any
7: * purpose with or without fee is hereby granted, provided that the above
8: * copyright notice and this permission notice appear in all copies.
9: *
10: * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11: * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12: * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13: * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14: * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15: * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16: * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17: */
18:
19: /*
20: * Known registers of the Atheros AR5001 Wireless LAN chipsets
21: * (AR5211/AR5311).
22: */
23:
24: #ifndef _AR5K_AR5211_REG_H
25: #define _AR5K_AR5211_REG_H
26:
27: /*
28: * Command register
29: */
30: #define AR5K_AR5211_CR 0x0008
31: #define AR5K_AR5211_CR_RXE 0x00000004
32: #define AR5K_AR5211_CR_RXD 0x00000020
33: #define AR5K_AR5211_CR_SWI 0x00000040
34:
35: /*
36: * Receive queue descriptor pointer register
37: */
38: #define AR5K_AR5211_RXDP 0x000c
39:
40: /*
41: * Configuration and status register
42: */
43: #define AR5K_AR5211_CFG 0x0014
44: #define AR5K_AR5211_CFG_SWTD 0x00000001
45: #define AR5K_AR5211_CFG_SWTB 0x00000002
46: #define AR5K_AR5211_CFG_SWRD 0x00000004
47: #define AR5K_AR5211_CFG_SWRB 0x00000008
48: #define AR5K_AR5211_CFG_SWRG 0x00000010
49: #define AR5K_AR5211_CFG_ADHOC 0x00000020
50: #define AR5K_AR5211_CFG_PHY_OK 0x00000100
51: #define AR5K_AR5211_CFG_EEBS 0x00000200
52: #define AR5K_AR5211_CFG_CLKGD 0x00000400
53: #define AR5K_AR5211_CFG_PCI_THRES 0x00060000
54: #define AR5K_AR5211_CFG_PCI_THRES_S 17
55:
56: /*
57: * Interrupt enable register
58: */
59: #define AR5K_AR5211_IER 0x0024
60: #define AR5K_AR5211_IER_DISABLE 0x00000000
61: #define AR5K_AR5211_IER_ENABLE 0x00000001
62:
63: /*
64: * First RTS duration register
65: */
66: #define AR5K_AR5211_RTSD0 0x0028
67: #define AR5K_AR5211_RTSD0_6 0x000000ff
68: #define AR5K_AR5211_RTSD0_6_S 0
69: #define AR5K_AR5211_RTSD0_9 0x0000ff00
70: #define AR5K_AR5211_RTSD0_9_S 8
71: #define AR5K_AR5211_RTSD0_12 0x00ff0000
72: #define AR5K_AR5211_RTSD0_12_S 16
73: #define AR5K_AR5211_RTSD0_18 0xff000000
74: #define AR5K_AR5211_RTSD0_18_S 24
75:
76: /*
77: * Second RTS duration register
78: */
79: #define AR5K_AR5211_RTSD1 0x002c
80: #define AR5K_AR5211_RTSD1_24 0x000000ff
81: #define AR5K_AR5211_RTSD1_24_S 0
82: #define AR5K_AR5211_RTSD1_36 0x0000ff00
83: #define AR5K_AR5211_RTSD1_36_S 8
84: #define AR5K_AR5211_RTSD1_48 0x00ff0000
85: #define AR5K_AR5211_RTSD1_48_S 16
86: #define AR5K_AR5211_RTSD1_54 0xff000000
87: #define AR5K_AR5211_RTSD1_54_S 24
88:
89: /*
90: * Transmit configuration register
91: */
92: #define AR5K_AR5211_TXCFG 0x0030
93: #define AR5K_AR5211_TXCFG_SDMAMR 0x00000007
94: #define AR5K_AR5211_TXCFG_SDMAMR_S 0
95: #define AR5K_AR5211_TXCFG_B_MODE 0x00000008
96: #define AR5K_AR5211_TXCFG_TXFULL 0x000003f0
97: #define AR5K_AR5211_TXCFG_TXFULL_S 4
98: #define AR5K_AR5211_TXCFG_TXFULL_0B 0x00000000
99: #define AR5K_AR5211_TXCFG_TXFULL_64B 0x00000010
100: #define AR5K_AR5211_TXCFG_TXFULL_128B 0x00000020
101: #define AR5K_AR5211_TXCFG_TXFULL_192B 0x00000030
102: #define AR5K_AR5211_TXCFG_TXFULL_256B 0x00000040
103: #define AR5K_AR5211_TXCFG_TXCONT_ENABLE 0x00000080
104: #define AR5K_AR5211_TXCFG_DMASIZE 0x00000100
105: #define AR5K_AR5211_TXCFG_JUMBO_TXE 0x00000400
106: #define AR5K_AR5211_TXCFG_RTSRND 0x00001000
107: #define AR5K_AR5211_TXCFG_FRMPAD_DIS 0x00002000
108: #define AR5K_AR5211_TXCFG_RDY_DIS 0x00004000
109:
110: /*
111: * Receive configuration register
112: */
113: #define AR5K_AR5211_RXCFG 0x0034
114: #define AR5K_AR5211_RXCFG_SDMAMW 0x00000007
115: #define AR5K_AR5211_RXCFG_SDMAMW_S 0
116: #define AR5K_AR5311_RXCFG_DEFAULT_ANTENNA 0x00000008
117: #define AR5K_AR5211_RXCFG_ZLFDMA 0x00000010
118: #define AR5K_AR5211_RXCFG_JUMBO_RXE 0x00000020
119: #define AR5K_AR5211_RXCFG_JUMBO_WRAP 0x00000040
120:
121: /*
122: * Receive jumbo descriptor last address register
123: */
124: #define AR5K_AR5211_RXJLA 0x0038
125:
126: /*
127: * MIB control register
128: */
129: #define AR5K_AR5211_MIBC 0x0040
130: #define AR5K_AR5211_MIBC_COW 0x00000001
131: #define AR5K_AR5211_MIBC_FMC 0x00000002
132: #define AR5K_AR5211_MIBC_CMC 0x00000004
133: #define AR5K_AR5211_MIBC_MCS 0x00000008
134:
135: /*
136: * Timeout prescale register
137: */
138: #define AR5K_AR5211_TOPS 0x0044
139: #define AR5K_AR5211_TOPS_M 0x0000ffff
140:
141: /*
142: * Receive timeout register (no frame received)
143: */
144: #define AR5K_AR5211_RXNOFRM 0x0048
145: #define AR5K_AR5211_RXNOFRM_M 0x000003ff
146:
147: /*
148: * Transmit timeout register (no frame sent)
149: */
150: #define AR5K_AR5211_TXNOFRM 0x004c
151: #define AR5K_AR5211_TXNOFRM_M 0x000003ff
152: #define AR5K_AR5211_TXNOFRM_QCU 0x000ffc00
153:
154: /*
155: * Receive frame gap timeout register
156: */
157: #define AR5K_AR5211_RPGTO 0x0050
158: #define AR5K_AR5211_RPGTO_M 0x000003ff
159:
160: /*
161: * Receive frame count limit register
162: */
163: #define AR5K_AR5211_RFCNT 0x0054
164: #define AR5K_AR5211_RFCNT_M 0x0000001f
165:
166: /*
167: * Misc settings register
168: */
169: #define AR5K_AR5211_MISC 0x0058
170: #define AR5K_AR5211_MISC_DMA_OBS_M 0x000001e0
171: #define AR5K_AR5211_MISC_DMA_OBS_S 5
172: #define AR5K_AR5211_MISC_MISC_OBS_M 0x00000e00
173: #define AR5K_AR5211_MISC_MISC_OBS_S 9
174: #define AR5K_AR5211_MISC_MAC_OBS_LSB_M 0x00007000
175: #define AR5K_AR5211_MISC_MAC_OBS_LSB_S 12
176: #define AR5K_AR5211_MISC_MAC_OBS_MSB_M 0x00038000
177: #define AR5K_AR5211_MISC_MAC_OBS_MSB_S 15
178:
179: /*
180: * QCU/DCU clock gating register
181: */
182: #define AR5K_AR5311_QCUDCU_CLKGT
183: #define AR5K_AR5311_QCUDCU_CLKGT_QCU 0x0000ffff
184: #define AR5K_AR5311_QCUDCU_CLKGT_DCU 0x07ff0000
185:
186: /*
187: * Primary interrupt status register
188: */
189: #define AR5K_AR5211_PISR 0x0080
190: #define AR5K_AR5211_PISR_RXOK 0x00000001
191: #define AR5K_AR5211_PISR_RXDESC 0x00000002
192: #define AR5K_AR5211_PISR_RXERR 0x00000004
193: #define AR5K_AR5211_PISR_RXNOFRM 0x00000008
194: #define AR5K_AR5211_PISR_RXEOL 0x00000010
195: #define AR5K_AR5211_PISR_RXORN 0x00000020
196: #define AR5K_AR5211_PISR_TXOK 0x00000040
197: #define AR5K_AR5211_PISR_TXDESC 0x00000080
198: #define AR5K_AR5211_PISR_TXERR 0x00000100
199: #define AR5K_AR5211_PISR_TXNOFRM 0x00000200
200: #define AR5K_AR5211_PISR_TXEOL 0x00000400
201: #define AR5K_AR5211_PISR_TXURN 0x00000800
202: #define AR5K_AR5211_PISR_MIB 0x00001000
203: #define AR5K_AR5211_PISR_SWI 0x00002000
204: #define AR5K_AR5211_PISR_RXPHY 0x00004000
205: #define AR5K_AR5211_PISR_RXKCM 0x00008000
206: #define AR5K_AR5211_PISR_SWBA 0x00010000
207: #define AR5K_AR5211_PISR_BRSSI 0x00020000
208: #define AR5K_AR5211_PISR_BMISS 0x00040000
209: #define AR5K_AR5211_PISR_HIUERR 0x00080000
210: #define AR5K_AR5211_PISR_BNR 0x00100000
211: #define AR5K_AR5211_PISR_TIM 0x00800000
212: #define AR5K_AR5211_PISR_GPIO 0x01000000
213: #define AR5K_AR5211_PISR_QCBRORN 0x02000000
214: #define AR5K_AR5211_PISR_QCBRURN 0x04000000
215: #define AR5K_AR5211_PISR_QTRIG 0x08000000
216:
217: /*
218: * Secondary interrupt status registers (0 - 4)
219: */
220: #define AR5K_AR5211_SISR0 0x0084
221: #define AR5K_AR5211_SISR0_QCU_TXOK 0x000003ff
222: #define AR5K_AR5211_SISR0_QCU_TXDESC 0x03ff0000
223:
224: #define AR5K_AR5211_SISR1 0x0088
225: #define AR5K_AR5211_SISR1_QCU_TXERR 0x000003ff
226: #define AR5K_AR5211_SISR1_QCU_TXEOL 0x03ff0000
227:
228: #define AR5K_AR5211_SISR2 0x008c
229: #define AR5K_AR5211_SISR2_QCU_TXURN 0x000003ff
230: #define AR5K_AR5211_SISR2_MCABT 0x00100000
231: #define AR5K_AR5211_SISR2_SSERR 0x00200000
232: #define AR5K_AR5211_SISR2_DPERR 0x00400000
233:
234: #define AR5K_AR5211_SISR3 0x0090
235: #define AR5K_AR5211_SISR3_QCBRORN 0x000003ff
236: #define AR5K_AR5211_SISR3_QCBRURN 0x03ff0000
237:
238: #define AR5K_AR5211_SISR4 0x0094
239: #define AR5K_AR5211_SISR4_QTRIG 0x000003ff
240:
241: /*
242: * Shadow read-and-clear interrupt status registers
243: */
244: #define AR5K_AR5211_RAC_PISR 0x00c0
245: #define AR5K_AR5211_RAC_SISR0 0x00c4
246: #define AR5K_AR5211_RAC_SISR1 0x00c8
247: #define AR5K_AR5211_RAC_SISR2 0x00cc
248: #define AR5K_AR5211_RAC_SISR3 0c00d0
249: #define AR5K_AR5211_RAC_SISR4 0c00d4
250:
251: /*
252: * Primary interrupt mask register
253: */
254: #define AR5K_AR5211_PIMR 0x00a0
255: #define AR5K_AR5211_PIMR_RXOK 0x00000001
256: #define AR5K_AR5211_PIMR_RXDESC 0x00000002
257: #define AR5K_AR5211_PIMR_RXERR 0x00000004
258: #define AR5K_AR5211_PIMR_RXNOFRM 0x00000008
259: #define AR5K_AR5211_PIMR_RXEOL 0x00000010
260: #define AR5K_AR5211_PIMR_RXORN 0x00000020
261: #define AR5K_AR5211_PIMR_TXOK 0x00000040
262: #define AR5K_AR5211_PIMR_TXDESC 0x00000080
263: #define AR5K_AR5211_PIMR_TXERR 0x00000100
264: #define AR5K_AR5211_PIMR_TXNOFRM 0x00000200
265: #define AR5K_AR5211_PIMR_TXEOL 0x00000400
266: #define AR5K_AR5211_PIMR_TXURN 0x00000800
267: #define AR5K_AR5211_PIMR_MIB 0x00001000
268: #define AR5K_AR5211_PIMR_SWI 0x00002000
269: #define AR5K_AR5211_PIMR_RXPHY 0x00004000
270: #define AR5K_AR5211_PIMR_RXKCM 0x00008000
271: #define AR5K_AR5211_PIMR_SWBA 0x00010000
272: #define AR5K_AR5211_PIMR_BRSSI 0x00020000
273: #define AR5K_AR5211_PIMR_BMISS 0x00040000
274: #define AR5K_AR5211_PIMR_HIUERR 0x00080000
275: #define AR5K_AR5211_PIMR_BNR 0x00100000
276: #define AR5K_AR5211_PIMR_TIM 0x00800000
277: #define AR5K_AR5211_PIMR_GPIO 0x01000000
278: #define AR5K_AR5211_PIMR_QCBRORN 0x02000000
279: #define AR5K_AR5211_PIMR_QCBRURN 0x04000000
280: #define AR5K_AR5211_PIMR_QTRIG 0x08000000
281:
282: /*
283: * Secondary interrupt mask registers (0 - 4)
284: */
285: #define AR5K_AR5211_SIMR0 0x00a4
286: #define AR5K_AR5211_SIMR0_QCU_TXOK 0x000003ff
287: #define AR5K_AR5211_SIMR0_QCU_TXOK_S 0
288: #define AR5K_AR5211_SIMR0_QCU_TXDESC 0x03ff0000
289: #define AR5K_AR5211_SIMR0_QCU_TXDESC_S 16
290:
291: #define AR5K_AR5211_SIMR1 0x00a8
292: #define AR5K_AR5211_SIMR1_QCU_TXERR 0x000003ff
293: #define AR5K_AR5211_SIMR1_QCU_TXERR_S 0
294: #define AR5K_AR5211_SIMR1_QCU_TXEOL 0x03ff0000
295: #define AR5K_AR5211_SIMR1_QCU_TXEOL_S 16
296:
297: #define AR5K_AR5211_SIMR2 0x00ac
298: #define AR5K_AR5211_SIMR2_QCU_TXURN 0x000003ff
299: #define AR5K_AR5211_SIMR2_QCU_TXURN_S 0
300: #define AR5K_AR5211_SIMR2_MCABT 0x00100000
301: #define AR5K_AR5211_SIMR2_SSERR 0x00200000
302: #define AR5K_AR5211_SIMR2_DPERR 0x00400000
303:
304: #define AR5K_AR5211_SIMR3 0x00b0
305: #define AR5K_AR5211_SIMR3_QCBRORN 0x000003ff
306: #define AR5K_AR5211_SIMR3_QCBRORN_S 0
307: #define AR5K_AR5211_SIMR3_QCBRURN 0x03ff0000
308: #define AR5K_AR5211_SIMR3_QCBRURN_S 16
309:
310: #define AR5K_AR5211_SIMR4 0x00b4
311: #define AR5K_AR5211_SIMR4_QTRIG 0x000003ff
312: #define AR5K_AR5211_SIMR4_QTRIG_S 0
313:
314: /*
315: * Queue control unit (QCU) registers (0 - 9)
316: */
317: #define AR5K_AR5211_QCU(_n, _a) (((_n) << 2) + _a)
318:
319: /*
320: * QCU Transmit descriptor pointer registers
321: */
322: #define AR5K_AR5211_QCU_TXDP(_n) AR5K_AR5211_QCU(_n, 0x0800)
323:
324: /*
325: * QCU Transmit enable register
326: */
327: #define AR5K_AR5211_QCU_TXE 0x0840
328:
329: /*
330: * QCU Transmit disable register
331: */
332: #define AR5K_AR5211_QCU_TXD 0x0880
333:
334: /*
335: * QCU CBR configuration registers
336: */
337: #define AR5K_AR5211_QCU_CBRCFG(_n) AR5K_AR5211_QCU(_n, 0x08c0)
338: #define AR5K_AR5211_QCU_CBRCFG_INTVAL 0x00ffffff
339: #define AR5K_AR5211_QCU_CBRCFG_INTVAL_S 0
340: #define AR5K_AR5211_QCU_CBRCFG_ORN_THRES 0xff000000
341: #define AR5K_AR5211_QCU_CBRCFG_ORN_THRES_S 24
342:
343: /*
344: * QCU Ready time configuration registers
345: */
346: #define AR5K_AR5211_QCU_RDYTIMECFG(_n) AR5K_AR5211_QCU(_n, 0x0900)
347: #define AR5K_AR5211_QCU_RDYTIMECFG_INTVAL 0x00ffffff
348: #define AR5K_AR5211_QCU_RDYTIMECFG_INTVAL_S 0
349: #define AR5K_AR5211_QCU_RDYTIMECFG_DURATION 0x00ffffff
350: #define AR5K_AR5211_QCU_RDYTIMECFG_ENABLE 0x01000000
351:
352: /*
353: * QCU one shot arm set registers
354: */
355: #define AR5K_AR5211_QCU_ONESHOTARMS(_n) AR5K_AR5211_QCU(_n, 0x0940)
356: #define AR5K_AR5211_QCU_ONESHOTARMS_M 0x0000ffff
357:
358: /*
359: * QCU one shot arm clear registers
360: */
361: #define AR5K_AR5211_QCU_ONESHOTARMC(_n) AR5K_AR5211_QCU(_n, 0x0980)
362: #define AR5K_AR5211_QCU_ONESHOTARMC_M 0x0000ffff
363:
364: /*
365: * QCU misc registers
366: */
367: #define AR5K_AR5211_QCU_MISC(_n) AR5K_AR5211_QCU(_n, 0x09c0)
368: #define AR5K_AR5211_QCU_MISC_FRSHED_M 0x0000000f
369: #define AR5K_AR5211_QCU_MISC_FRSHED_ASAP 0
370: #define AR5K_AR5211_QCU_MISC_FRSHED_CBR 1
371: #define AR5K_AR5211_QCU_MISC_FRSHED_DBA_GT 2
372: #define AR5K_AR5211_QCU_MISC_FRSHED_TIM_GT 3
373: #define AR5K_AR5211_QCU_MISC_FRSHED_BCN_SENT_GT 4
374: #define AR5K_AR5211_QCU_MISC_ONESHOT_ENABLE 0x00000010
375: #define AR5K_AR5211_QCU_MISC_CBREXP 0x00000020
376: #define AR5K_AR5211_QCU_MISC_CBREXP_BCN 0x00000040
377: #define AR5K_AR5211_QCU_MISC_BCN_ENABLE 0x00000080
378: #define AR5K_AR5211_QCU_MISC_CBR_THRES_ENABLE 0x00000100
379: #define AR5K_AR5211_QCU_MISC_TXE 0x00000200
380: #define AR5K_AR5211_QCU_MISC_CBR 0x00000400
381: #define AR5K_AR5211_QCU_MISC_DCU_EARLY 0x00000800
382:
383: /*
384: * QCU status registers
385: */
386: #define AR5K_AR5211_QCU_STS(_n) AR5K_AR5211_QCU(_n, 0x0a00)
387: #define AR5K_AR5211_QCU_STS_FRMPENDCNT 0x00000003
388: #define AR5K_AR5211_QCU_STS_CBREXPCNT 0x0000ff00
389:
390: /*
391: * QCU ready time shutdown register
392: */
393: #define AR5K_AR5211_QCU_RDYTIMESHDN 0x0a40
394: #define AR5K_AR5211_QCU_RDYTIMESHDN_M 0x000003ff
395:
396: /*
397: * DCF control unit (DCU) registers (0 - 9)
398: */
399: #define AR5K_AR5211_DCU(_n, _a) AR5K_AR5211_QCU(_n, _a)
400:
401: /*
402: * DCU QCU mask registers
403: */
404: #define AR5K_AR5211_DCU_QCUMASK(_n) AR5K_AR5211_DCU(_n, 0x1000)
405: #define AR5K_AR5211_DCU_QCUMASK_M 0x000003ff
406:
407: /*
408: * DCU local IFS settings register
409: */
410: #define AR5K_AR5211_DCU_LCL_IFS(_n) AR5K_AR5211_DCU(_n, 0x1040)
411: #define AR5K_AR5211_DCU_LCL_IFS_CW_MIN 0x000003ff
412: #define AR5K_AR5211_DCU_LCL_IFS_CW_MIN_S 0
413: #define AR5K_AR5211_DCU_LCL_IFS_CW_MAX 0x000ffc00
414: #define AR5K_AR5211_DCU_LCL_IFS_CW_MAX_S 10
415: #define AR5K_AR5211_DCU_LCL_IFS_AIFS 0x0ff00000
416: #define AR5K_AR5211_DCU_LCL_IFS_AIFS_S 20
417:
418: /*
419: * DCU retry limit registers
420: */
421: #define AR5K_AR5211_DCU_RETRY_LMT(_n) AR5K_AR5211_DCU(_n, 0x1080)
422: #define AR5K_AR5211_DCU_RETRY_LMT_SH_RETRY 0x0000000f
423: #define AR5K_AR5211_DCU_RETRY_LMT_SH_RETRY_S 0
424: #define AR5K_AR5211_DCU_RETRY_LMT_LG_RETRY 0x000000f0
425: #define AR5K_AR5211_DCU_RETRY_LMT_LG_RETRY_S 4
426: #define AR5K_AR5211_DCU_RETRY_LMT_SSH_RETRY 0x00003f00
427: #define AR5K_AR5211_DCU_RETRY_LMT_SSH_RETRY_S 8
428: #define AR5K_AR5211_DCU_RETRY_LMT_SLG_RETRY 0x000fc000
429: #define AR5K_AR5211_DCU_RETRY_LMT_SLG_RETRY_S 14
430:
431: /*
432: * DCU channel time registers
433: */
434: #define AR5K_AR5211_DCU_CHAN_TIME(_n) AR5K_AR5211_DCU(_n, 0x10c0)
435: #define AR5K_AR5211_DCU_CHAN_TIME_ENABLE 0x00100000
436: #define AR5K_AR5211_DCU_CHAN_TIME_DUR 0x000fffff
437: #define AR5K_AR5211_DCU_CHAN_TIME_DUR_S 0
438:
439: /*
440: * DCU misc registers
441: */
442: #define AR5K_AR5211_DCU_MISC(_n) AR5K_AR5211_DCU(_n, 0x1100)
443: #define AR5K_AR5211_DCU_MISC_BACKOFF 0x000007ff
444: #define AR5K_AR5211_DCU_MISC_BACKOFF_FRAG 0x00000200
445: #define AR5K_AR5211_DCU_MISC_HCFPOLL_ENABLE 0x00000800
446: #define AR5K_AR5211_DCU_MISC_BACKOFF_PERSIST 0x00001000
447: #define AR5K_AR5211_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000
448: #define AR5K_AR5211_DCU_MISC_VIRTCOL 0x0000c000
449: #define AR5K_AR5211_DCU_MISC_VIRTCOL_NORMAL 0
450: #define AR5K_AR5211_DCU_MISC_VIRTCOL_MODIFIED 1
451: #define AR5K_AR5211_DCU_MISC_VIRTCOL_IGNORE 2
452: #define AR5K_AR5211_DCU_MISC_BCN_ENABLE 0x00010000
453: #define AR5K_AR5211_DCU_MISC_ARBLOCK_CTL 0x00060000
454: #define AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_S 17
455: #define AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_NONE 0
456: #define AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_INTFRM 1
457: #define AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_GLOBAL 2
458: #define AR5K_AR5211_DCU_MISC_ARBLOCK_IGNORE 0x00080000
459: #define AR5K_AR5211_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000
460: #define AR5K_AR5211_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000
461: #define AR5K_AR5211_DCU_MISC_VIRT_COLL_POLICY 0x00400000
462: #define AR5K_AR5211_DCU_MISC_BLOWN_IFS_POLICY 0x00800000
463: #define AR5K_AR5211_DCU_MISC_SEQNUM_CTL 0x01000000
464:
465: /*
466: * DCU frame sequence number registers
467: */
468: #define AR5K_AR5211_DCU_SEQNUM(_n) AR5K_AR5211_DCU(_n, 0x1140)
469: #define AR5K_AR5211_DCU_SEQNUM_M 0x00000fff
470: /*
471: * DCU global IFS SIFS registers
472: */
473: #define AR5K_AR5211_DCU_GBL_IFS_SIFS 0x1030
474: #define AR5K_AR5211_DCU_GBL_IFS_SIFS_M 0x0000ffff
475:
476: /*
477: * DCU global IFS slot interval registers
478: */
479: #define AR5K_AR5211_DCU_GBL_IFS_SLOT 0x1070
480: #define AR5K_AR5211_DCU_GBL_IFS_SLOT_M 0x0000ffff
481:
482: /*
483: * DCU global IFS EIFS registers
484: */
485: #define AR5K_AR5211_DCU_GBL_IFS_EIFS 0x10b0
486: #define AR5K_AR5211_DCU_GBL_IFS_EIFS_M 0x0000ffff
487:
488: /*
489: * DCU global IFS misc registers
490: */
491: #define AR5K_AR5211_DCU_GBL_IFS_MISC 0x10f0
492: #define AR5K_AR5211_DCU_GBL_IFS_MISC_LFSR_SLICE 0x00000007
493: #define AR5K_AR5211_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008
494: #define AR5K_AR5211_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0
495: #define AR5K_AR5211_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00
496: #define AR5K_AR5211_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000
497:
498: /*
499: * DCU frame prefetch control register
500: */
501: #define AR5K_AR5211_DCU_FP 0x1230
502:
503: /*
504: * DCU transmit pause control/status register
505: */
506: #define AR5K_AR5211_DCU_TXP 0x1270
507: #define AR5K_AR5211_DCU_TXP_M 0x000003ff
508: #define AR5K_AR5211_DCU_TXP_STATUS 0x00010000
509:
510: /*
511: * DCU transmit filter register
512: */
513: #define AR5K_AR5211_DCU_TX_FILTER 0x1038
514:
515: /*
516: * DCU clear transmit filter register
517: */
518: #define AR5K_AR5211_DCU_TX_FILTER_CLR 0x143c
519:
520: /*
521: * DCU set transmit filter register
522: */
523: #define AR5K_AR5211_DCU_TX_FILTER_SET 0x147c
524:
525: /*
526: * DMA size definitions
527: */
528: typedef enum {
529: AR5K_AR5211_DMASIZE_4B = 0,
530: AR5K_AR5211_DMASIZE_8B = 1,
531: AR5K_AR5211_DMASIZE_16B = 2,
532: AR5K_AR5211_DMASIZE_32B = 3,
533: AR5K_AR5211_DMASIZE_64B = 4,
534: AR5K_AR5211_DMASIZE_128B = 5,
535: AR5K_AR5211_DMASIZE_256B = 6,
536: AR5K_AR5211_DMASIZE_512B = 7
537: } ar5k_ar5211_dmasize_t;
538:
539: /*
540: * Reset control register
541: */
542: #define AR5K_AR5211_RC 0x4000
543: #define AR5K_AR5211_RC_PCU 0x00000001
544: #define AR5K_AR5211_RC_BB 0x00000002
545: #define AR5K_AR5211_RC_PCI 0x00000010
546: #define AR5K_AR5211_RC_CHIP ( \
547: AR5K_AR5211_RC_PCU | AR5K_AR5211_RC_BB | AR5K_AR5211_RC_PCI \
548: )
549:
550: /*
551: * Sleep control register
552: */
553: #define AR5K_AR5211_SCR 0x4004
554: #define AR5K_AR5211_SCR_SLDUR 0x0000ffff
555: #define AR5K_AR5211_SCR_SLDUR_S 0
556: #define AR5K_AR5211_SCR_SLE 0x00030000
557: #define AR5K_AR5211_SCR_SLE_S 16
558: #define AR5K_AR5211_SCR_SLE_WAKE 0x00000000
559: #define AR5K_AR5211_SCR_SLE_SLP 0x00010000
560: #define AR5K_AR5211_SCR_SLE_ALLOW 0x00020000
561: #define AR5K_AR5211_SCR_SLE_UNITS 0x00000008
562:
563: /*
564: * Interrupt pending register
565: */
566: #define AR5K_AR5211_INTPEND 0x4008
567: #define AR5K_AR5211_INTPEND_M 0x00000001
568:
569: /*
570: * Sleep force register
571: */
572: #define AR5K_AR5211_SFR 0x400c
573: #define AR5K_AR5211_SFR_M 0x00000001
574:
575: /*
576: * PCI configuration register
577: */
578: #define AR5K_AR5211_PCICFG 0x4010
579: #define AR5K_AR5211_PCICFG_CLKRUNEN 0x00000004
580: #define AR5K_AR5211_PCICFG_EESIZE 0x00000018
581: #define AR5K_AR5211_PCICFG_EESIZE_S 3
582: #define AR5K_AR5211_PCICFG_EESIZE_4K 0
583: #define AR5K_AR5211_PCICFG_EESIZE_8K 1
584: #define AR5K_AR5211_PCICFG_EESIZE_16K 2
585: #define AR5K_AR5211_PCICFG_EESIZE_FAIL 3
586: #define AR5K_AR5211_PCICFG_LED 0x00000060
587: #define AR5K_AR5211_PCICFG_LED_NONE 0x00000000
588: #define AR5K_AR5211_PCICFG_LED_PEND 0x00000020
589: #define AR5K_AR5211_PCICFG_LED_ASSOC 0x00000040
590: #define AR5K_AR5211_PCICFG_BUS_SEL 0x00000380
591: #define AR5K_AR5211_PCICFG_CBEFIX_DIS 0x00000400
592: #define AR5K_AR5211_PCICFG_SL_INTEN 0x00000800
593: #define AR5K_AR5211_PCICFG_SL_INPEN 0x00002800
594: #define AR5K_AR5211_PCICFG_SPWR_DN 0x00010000
595: #define AR5K_AR5211_PCICFG_LEDMODE 0x000e0000
596: #define AR5K_AR5211_PCICFG_LEDMODE_PROP 0x00000000
597: #define AR5K_AR5211_PCICFG_LEDMODE_PROM 0x00020000
598: #define AR5K_AR5211_PCICFG_LEDMODE_PWR 0x00040000
599: #define AR5K_AR5211_PCICFG_LEDMODE_RAND 0x00060000
600: #define AR5K_AR5211_PCICFG_LEDBLINK 0x00700000
601: #define AR5K_AR5211_PCICFG_LEDBLINK_S 20
602: #define AR5K_AR5211_PCICFG_LEDSLOW 0x00800000
603: #define AR5K_AR5211_PCICFG_LEDSTATE \
604: (AR5K_AR5211_PCICFG_LED | AR5K_AR5211_PCICFG_LEDMODE | \
605: AR5K_AR5211_PCICFG_LEDBLINK | AR5K_AR5211_PCICFG_LEDSLOW)
606:
607: /*
608: * "General Purpose Input/Output" (GPIO) control register
609: */
610: #define AR5K_AR5211_GPIOCR 0x4014
611: #define AR5K_AR5211_GPIOCR_INT_ENA 0x00008000
612: #define AR5K_AR5211_GPIOCR_INT_SELL 0x00000000
613: #define AR5K_AR5211_GPIOCR_INT_SELH 0x00010000
614: #define AR5K_AR5211_GPIOCR_NONE(n) (0 << ((n) * 2))
615: #define AR5K_AR5211_GPIOCR_OUT0(n) (1 << ((n) * 2))
616: #define AR5K_AR5211_GPIOCR_OUT1(n) (2 << ((n) * 2))
617: #define AR5K_AR5211_GPIOCR_ALL(n) (3 << ((n) * 2))
618: #define AR5K_AR5211_GPIOCR_INT_SEL(n) ((n) << 12)
619:
620: #define AR5K_AR5211_NUM_GPIO 6
621:
622: /*
623: * "General Purpose Input/Output" (GPIO) data output register
624: */
625: #define AR5K_AR5211_GPIODO 0x4018
626:
627: /*
628: * "General Purpose Input/Output" (GPIO) data input register
629: */
630: #define AR5K_AR5211_GPIODI 0x401c
631: #define AR5K_AR5211_GPIODI_M 0x0000002f
632:
633: /*
634: * Silicon revision register
635: */
636: #define AR5K_AR5211_SREV 0x4020
637: #define AR5K_AR5211_SREV_REV 0x0000000f
638: #define AR5K_AR5211_SREV_REV_S 0
639: #define AR5K_AR5211_SREV_VER 0x000000ff
640: #define AR5K_AR5211_SREV_VER_S 4
641:
642: /*
643: * EEPROM access registers
644: */
645: #define AR5K_AR5211_EEPROM_BASE 0x6000
646: #define AR5K_AR5211_EEPROM_DATA 0x6004
647: #define AR5K_AR5211_EEPROM_CMD 0x6008
648: #define AR5K_AR5211_EEPROM_CMD_READ 0x00000001
649: #define AR5K_AR5211_EEPROM_CMD_WRITE 0x00000002
650: #define AR5K_AR5211_EEPROM_CMD_RESET 0x00000004
651: #define AR5K_AR5211_EEPROM_STATUS 0x600c
652: #define AR5K_AR5211_EEPROM_STAT_RDERR 0x00000001
653: #define AR5K_AR5211_EEPROM_STAT_RDDONE 0x00000002
654: #define AR5K_AR5211_EEPROM_STAT_WRERR 0x00000004
655: #define AR5K_AR5211_EEPROM_STAT_WRDONE 0x00000008
656: #define AR5K_AR5211_EEPROM_CFG 0x6010
657:
658: /*
659: * AR5211 EEPROM data registers
660: */
661: #define AR5K_AR5211_EEPROM_MAGIC 0x3d
662: #define AR5K_AR5211_EEPROM_MAGIC_VALUE 0x5aa5
663: #define AR5K_AR5211_EEPROM_PROTECT 0x3f
664: #define AR5K_AR5211_EEPROM_PROTECT_128_191 0x80
665: #define AR5K_AR5211_EEPROM_REG_DOMAIN 0xbf
666: #define AR5K_AR5211_EEPROM_INFO_BASE 0xc0
667: #define AR5K_AR5211_EEPROM_INFO_VERSION \
668: (AR5K_AR5211_EEPROM_INFO_BASE + 1)
669: #define AR5K_AR5211_EEPROM_INFO_MAX \
670: (0x400 - AR5K_AR5211_EEPROM_INFO_BASE)
671:
672: /*
673: * PCU registers
674: */
675:
676: #define AR5K_AR5211_PCU_MIN 0x8000
677: #define AR5K_AR5211_PCU_MAX 0x8fff
678:
679: /*
680: * First station id register (MAC address in lower 32 bits)
681: */
682: #define AR5K_AR5211_STA_ID0 0x8000
683:
684: /*
685: * Second station id register (MAC address in upper 16 bits)
686: */
687: #define AR5K_AR5211_STA_ID1 0x8004
688: #define AR5K_AR5211_STA_ID1_AP 0x00010000
689: #define AR5K_AR5211_STA_ID1_ADHOC 0x00020000
690: #define AR5K_AR5211_STA_ID1_PWR_SV 0x00040000
691: #define AR5K_AR5211_STA_ID1_NO_KEYSRCH 0x00080000
692: #define AR5K_AR5211_STA_ID1_PCF 0x00100000
693: #define AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA 0x00200000
694: #define AR5K_AR5211_STA_ID1_DESC_ANTENNA 0x00400000
695: #define AR5K_AR5211_STA_ID1_RTS_DEFAULT_ANTENNA 0x00800000
696: #define AR5K_AR5211_STA_ID1_ACKCTS_6MB 0x01000000
697: #define AR5K_AR5211_STA_ID1_BASE_RATE_11B 0x02000000
698:
699: /*
700: * First BSSID register (MAC address, lower 32bits)
701: */
702: #define AR5K_AR5211_BSS_ID0 0x8008
703:
704: /*
705: * Second BSSID register (MAC address in upper 16 bits)
706: *
707: * AID: Association ID
708: */
709: #define AR5K_AR5211_BSS_ID1 0x800c
710: #define AR5K_AR5211_BSS_ID1_AID 0xffff0000
711: #define AR5K_AR5211_BSS_ID1_AID_S 16
712:
713: /*
714: * Backoff slot time register
715: */
716: #define AR5K_AR5211_SLOT_TIME 0x8010
717:
718: /*
719: * ACK/CTS timeout register
720: */
721: #define AR5K_AR5211_TIME_OUT 0x8014
722: #define AR5K_AR5211_TIME_OUT_ACK 0x00001fff
723: #define AR5K_AR5211_TIME_OUT_ACK_S 0
724: #define AR5K_AR5211_TIME_OUT_CTS 0x1fff0000
725: #define AR5K_AR5211_TIME_OUT_CTS_S 16
726:
727: /*
728: * RSSI threshold register
729: */
730: #define AR5K_AR5211_RSSI_THR 0x8018
731: #define AR5K_AR5211_RSSI_THR_M 0x000000ff
732: #define AR5K_AR5211_RSSI_THR_BMISS 0x0000ff00
733: #define AR5K_AR5211_RSSI_THR_BMISS_S 8
734:
735: /*
736: * Transmit latency register
737: */
738: #define AR5K_AR5211_USEC 0x801c
739: #define AR5K_AR5211_USEC_1 0x0000007f
740: #define AR5K_AR5211_USEC_1_S 0
741: #define AR5K_AR5211_USEC_32 0x00003f80
742: #define AR5K_AR5211_USEC_32_S 7
743: #define AR5K_AR5211_USEC_TX_LATENCY 0x007fc000
744: #define AR5K_AR5211_USEC_TX_LATENCY_S 14
745: #define AR5K_AR5211_USEC_RX_LATENCY 0x1f800000
746: #define AR5K_AR5211_USEC_RX_LATENCY_S 23
747: #define AR5K_AR5311_USEC_TX_LATENCY 0x000fc000
748: #define AR5K_AR5311_USEC_TX_LATENCY_S 14
749: #define AR5K_AR5311_USEC_RX_LATENCY 0x03f00000
750: #define AR5K_AR5311_USEC_RX_LATENCY_S 20
751:
752: /*
753: * PCU beacon control register
754: */
755: #define AR5K_AR5211_BEACON 0x8020
756: #define AR5K_AR5211_BEACON_PERIOD 0x0000ffff
757: #define AR5K_AR5211_BEACON_PERIOD_S 0
758: #define AR5K_AR5211_BEACON_TIM 0x007f0000
759: #define AR5K_AR5211_BEACON_TIM_S 16
760: #define AR5K_AR5211_BEACON_ENABLE 0x00800000
761: #define AR5K_AR5211_BEACON_RESET_TSF 0x01000000
762:
763: /*
764: * CFP period register
765: */
766: #define AR5K_AR5211_CFP_PERIOD 0x8024
767:
768: /*
769: * Next beacon time register
770: */
771: #define AR5K_AR5211_TIMER0 0x8028
772:
773: /*
774: * Next DMA beacon alert register
775: */
776: #define AR5K_AR5211_TIMER1 0x802c
777:
778: /*
779: * Next software beacon alert register
780: */
781: #define AR5K_AR5211_TIMER2 0x8030
782:
783: /*
784: * Next ATIM window time register
785: */
786: #define AR5K_AR5211_TIMER3 0x8034
787:
788: /*
789: * CFP duration register
790: */
791: #define AR5K_AR5211_CFP_DUR 0x8038
792:
793: /*
794: * Receive filter register
795: */
796: #define AR5K_AR5211_RX_FILTER 0x803c
797: #define AR5K_AR5211_RX_FILTER_UNICAST 0x00000001
798: #define AR5K_AR5211_RX_FILTER_MULTICAST 0x00000002
799: #define AR5K_AR5211_RX_FILTER_BROADCAST 0x00000004
800: #define AR5K_AR5211_RX_FILTER_CONTROL 0x00000008
801: #define AR5K_AR5211_RX_FILTER_BEACON 0x00000010
802: #define AR5K_AR5211_RX_FILTER_PROMISC 0x00000020
803: #define AR5K_AR5211_RX_FILTER_PHYERR 0x00000040
804: #define AR5K_AR5211_RX_FILTER_RADARERR 0x00000080
805:
806: /*
807: * Multicast filter register (lower 32 bits)
808: */
809: #define AR5K_AR5211_MCAST_FIL0 0x8040
810:
811: /*
812: * Multicast filter register (higher 16 bits)
813: */
814: #define AR5K_AR5211_MCAST_FIL1 0x8044
815:
816: /*
817: * PCU control register
818: */
819: #define AR5K_AR5211_DIAG_SW 0x8048
820: #define AR5K_AR5211_DIAG_SW_DIS_WEP_ACK 0x00000001
821: #define AR5K_AR5211_DIAG_SW_DIS_ACK 0x00000002
822: #define AR5K_AR5211_DIAG_SW_DIS_CTS 0x00000004
823: #define AR5K_AR5211_DIAG_SW_DIS_ENC 0x00000008
824: #define AR5K_AR5211_DIAG_SW_DIS_DEC 0x00000010
825: #define AR5K_AR5211_DIAG_SW_DIS_RX 0x00000020
826: #define AR5K_AR5211_DIAG_SW_LOOP_BACK 0x00000040
827: #define AR5K_AR5211_DIAG_SW_CORR_FCS 0x00000080
828: #define AR5K_AR5211_DIAG_SW_CHAN_INFO 0x00000100
829: #define AR5K_AR5211_DIAG_SW_EN_SCRAM_SEED 0x00000200
830: #define AR5K_AR5211_DIAG_SW_ECO_ENABLE 0x00000400
831: #define AR5K_AR5211_DIAG_SW_SCRAM_SEED_M 0x0001fc00
832: #define AR5K_AR5211_DIAG_SW_SCRAM_SEED_S 10
833: #define AR5K_AR5211_DIAG_SW_FRAME_NV0 0x00020000
834: #define AR5K_AR5211_DIAG_SW_OBSPT_M 0x000c0000
835: #define AR5K_AR5211_DIAG_SW_OBSPT_S 18
836:
837: /*
838: * TSF (clock) register (lower 32 bits)
839: */
840: #define AR5K_AR5211_TSF_L32 0x804c
841:
842: /*
843: * TSF (clock) register (higher 32 bits)
844: */
845: #define AR5K_AR5211_TSF_U32 0x8050
846:
847: /*
848: * ADDAC test register
849: */
850: #define AR5K_AR5211_ADDAC_TEST 0x8054
851:
852: /*
853: * Default antenna register
854: */
855: #define AR5K_AR5211_DEFAULT_ANTENNA 0x8058
856:
857: /*
858: * Last beacon timestamp register
859: */
860: #define AR5K_AR5211_LAST_TSTP 0x8080
861:
862: /*
863: * NAV register (current)
864: */
865: #define AR5K_AR5211_NAV 0x8084
866:
867: /*
868: * RTS success register
869: */
870: #define AR5K_AR5211_RTS_OK 0x8088
871:
872: /*
873: * RTS failure register
874: */
875: #define AR5K_AR5211_RTS_FAIL 0x808c
876:
877: /*
878: * ACK failure register
879: */
880: #define AR5K_AR5211_ACK_FAIL 0x8090
881:
882: /*
883: * FCS failure register
884: */
885: #define AR5K_AR5211_FCS_FAIL 0x8094
886:
887: /*
888: * Beacon count register
889: */
890: #define AR5K_AR5211_BEACON_CNT 0x8098
891:
892: /*
893: * Key table (WEP) register
894: */
895: #define AR5K_AR5211_KEYTABLE_0 0x8800
896: #define AR5K_AR5211_KEYTABLE(n) (AR5K_AR5211_KEYTABLE_0 + ((n) * 32))
897: #define AR5K_AR5211_KEYTABLE_OFF(_n, x) (AR5K_AR5211_KEYTABLE(_n) + (x << 2))
898: #define AR5K_AR5211_KEYTABLE_TYPE(_n) AR5K_AR5211_KEYTABLE_OFF(_n, 5)
899: #define AR5K_AR5211_KEYTABLE_TYPE_40 0x00000000
900: #define AR5K_AR5211_KEYTABLE_TYPE_104 0x00000001
901: #define AR5K_AR5211_KEYTABLE_TYPE_128 0x00000003
902: #define AR5K_AR5211_KEYTABLE_TYPE_AES 0x00000005
903: #define AR5K_AR5211_KEYTABLE_TYPE_NULL 0x00000007
904: #define AR5K_AR5211_KEYTABLE_MAC0(_n) AR5K_AR5211_KEYTABLE_OFF(_n, 6)
905: #define AR5K_AR5211_KEYTABLE_MAC1(_n) AR5K_AR5211_KEYTABLE_OFF(_n, 7)
906: #define AR5K_AR5211_KEYTABLE_VALID 0x00008000
907:
908: #define AR5K_AR5211_KEYTABLE_SIZE 128
909: #define AR5K_AR5211_KEYCACHE_SIZE 8
910:
911: /*
912: * PHY register
913: */
914: #define AR5K_AR5211_PHY(_n) (0x9800 + ((_n) << 2))
915: #define AR5K_AR5211_PHY_SHIFT_2GHZ 0x00004007
916: #define AR5K_AR5211_PHY_SHIFT_5GHZ 0x00000007
917:
918: /*
919: * PHY turbo mode register
920: */
921: #define AR5K_AR5211_PHY_TURBO 0x9804
922: #define AR5K_AR5211_PHY_TURBO_MODE 0x00000001
923: #define AR5K_AR5211_PHY_TURBO_SHORT 0x00000002
924:
925: /*
926: * PHY agility command register
927: */
928: #define AR5K_AR5211_PHY_AGC 0x9808
929: #define AR5K_AR5211_PHY_AGC_DISABLE 0x08000000
930:
931: /*
932: * PHY chip revision register
933: */
934: #define AR5K_AR5211_PHY_CHIP_ID 0x9818
935:
936: /*
937: * PHY activation register
938: */
939: #define AR5K_AR5211_PHY_ACTIVE 0x981c
940: #define AR5K_AR5211_PHY_ENABLE 0x00000001
941: #define AR5K_AR5211_PHY_DISABLE 0x00000002
942:
943: /*
944: * PHY agility control register
945: */
946: #define AR5K_AR5211_PHY_AGCCTL 0x9860
947: #define AR5K_AR5211_PHY_AGCCTL_CAL 0x00000001
948: #define AR5K_AR5211_PHY_AGCCTL_NF 0x00000002
949:
950: /*
951: * PHY noise floor status register
952: */
953: #define AR5K_AR5211_PHY_NF 0x9864
954: #define AR5K_AR5211_PHY_NF_M 0x000001ff
955: #define AR5K_AR5211_PHY_NF_ACTIVE 0x00000100
956: #define AR5K_AR5211_PHY_NF_RVAL(_n) (((_n) >> 19) & AR5K_AR5211_PHY_NF_M)
957: #define AR5K_AR5211_PHY_NF_AVAL(_n) (-((_n) ^ AR5K_AR5211_PHY_NF_M) + 1)
958: #define AR5K_AR5211_PHY_NF_SVAL(_n) (((_n) & AR5K_AR5211_PHY_NF_M) | (1 << 9))
959:
960: /*
961: * PHY PLL control register
962: */
963: #define AR5K_AR5211_PHY_PLL 0x987c
964: #define AR5K_AR5211_PHY_PLL_20MHZ 0x13
965: #define AR5K_AR5211_PHY_PLL_40MHZ 0x18
966: #define AR5K_AR5211_PHY_PLL_44MHZ 0x19
967:
968: /*
969: * PHY receiver delay register
970: */
971: #define AR5K_AR5211_PHY_RX_DELAY 0x9914
972: #define AR5K_AR5211_PHY_RX_DELAY_M 0x00003fff
973:
974: /*
975: * PHY timing IQ control register
976: */
977: #define AR5K_AR5211_PHY_IQ 0x9920
978: #define AR5K_AR5211_PHY_IQ_CORR_Q_Q_COFF 0x0000001f
979: #define AR5K_AR5211_PHY_IQ_CORR_Q_I_COFF 0x000007e0
980: #define AR5K_AR5211_PHY_IQ_CORR_Q_I_COFF_S 5
981: #define AR5K_AR5211_PHY_IQ_CORR_ENABLE 0x00000800
982: #define AR5K_AR5211_PHY_IQ_CAL_NUM_LOG_MAX 0x0000f000
983: #define AR5K_AR5211_PHY_IQ_CAL_NUM_LOG_MAX_S 12
984: #define AR5K_AR5211_PHY_IQ_RUN 0x00010000
985:
986: /*
987: * PHY PAPD probe register
988: */
989: #define AR5K_AR5211_PHY_PAPD_PROBE 0x9930
990: #define AR5K_AR5211_PHY_PAPD_PROBE_TX_PWR 0x00007e00
991: #define AR5K_AR5211_PHY_PAPD_PROBE_TX_PWR_S 9
992: #define AR5K_AR5211_PHY_PAPD_PROBE_TX_NEXT 0x00008000
993: #define AR5K_AR5211_PHY_PAPD_PROBE_GAINF 0xfe000000
994: #define AR5K_AR5211_PHY_PAPD_PROBE_GAINF_S 25
995:
996: /*
997: * PHY frame control register
998: */
999: #define AR5K_AR5211_PHY_FC 0x9944
1000: #define AR5K_AR5211_PHY_FC_TX_CLIP 0x00000038
1001: #define AR5K_AR5211_PHY_FC_TX_CLIP_S 3
1002:
1003: /*
1004: * PHY radar detection enable register
1005: */
1006: #define AR5K_AR5211_PHY_RADAR 0x9954
1007: #define AR5K_AR5211_PHY_RADAR_DISABLE 0x00000000
1008: #define AR5K_AR5211_PHY_RADAR_ENABLE 0x00000001
1009:
1010: /*
1011: * PHY antenna switch table registers
1012: */
1013: #define AR5K_AR5211_PHY_ANT_SWITCH_TABLE_0 0x9960
1014: #define AR5K_AR5211_PHY_ANT_SWITCH_TABLE_1 0x9964
1015:
1016: /*
1017: * PHY timing IQ calibration result register
1018: */
1019: #define AR5K_AR5211_PHY_IQRES_CAL_PWR_I 0x9c10
1020: #define AR5K_AR5211_PHY_IQRES_CAL_PWR_Q 0x9c14
1021: #define AR5K_AR5211_PHY_IQRES_CAL_CORR 0x9c18
1022:
1023: /*
1024: * PHY current RSSI register
1025: */
1026: #define AR5K_AR5211_PHY_CURRENT_RSSI 0x9c1c
1027:
1028: /*
1029: * PHY mode register
1030: */
1031: #define AR5K_AR5211_PHY_MODE 0xa200
1032: #define AR5K_AR5211_PHY_MODE_MOD 0x00000001
1033: #define AR5K_AR5211_PHY_MODE_MOD_OFDM 0
1034: #define AR5K_AR5211_PHY_MODE_MOD_CCK 1
1035: #define AR5K_AR5211_PHY_MODE_FREQ 0x00000002
1036: #define AR5K_AR5211_PHY_MODE_FREQ_5GHZ 0
1037: #define AR5K_AR5211_PHY_MODE_FREQ_2GHZ 2
1038:
1039: /*
1040: * Misc PHY/radio registers
1041: */
1042: #define AR5K_AR5211_BB_GAIN(_n) (0x9b00 + ((_n) << 2))
1043: #define AR5K_AR5211_RF_GAIN(_n) (0x9a00 + ((_n) << 2))
1044:
1045: #endif
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