Annotation of sys/dev/ic/am7930reg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: am7930reg.h,v 1.5 2007/05/23 09:00:17 jmc Exp $ */
! 2: /* $NetBSD: am7930reg.h,v 1.1 1995/04/24 19:17:17 pk Exp $ */
! 3:
! 4: /*
! 5: * Copyright (c) 1992, 1993
! 6: * The Regents of the University of California. All rights reserved.
! 7: *
! 8: * This software was developed by the Computer Systems Engineering group
! 9: * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
! 10: * contributed to Berkeley.
! 11: *
! 12: * All advertising materials mentioning features or use of this software
! 13: * must display the following acknowledgement:
! 14: * This product includes software developed by the University of
! 15: * California, Lawrence Berkeley Laboratory.
! 16: *
! 17: * Redistribution and use in source and binary forms, with or without
! 18: * modification, are permitted provided that the following conditions
! 19: * are met:
! 20: * 1. Redistributions of source code must retain the above copyright
! 21: * notice, this list of conditions and the following disclaimer.
! 22: * 2. Redistributions in binary form must reproduce the above copyright
! 23: * notice, this list of conditions and the following disclaimer in the
! 24: * documentation and/or other materials provided with the distribution.
! 25: * 3. Neither the name of the University nor the names of its contributors
! 26: * may be used to endorse or promote products derived from this software
! 27: * without specific prior written permission.
! 28: *
! 29: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
! 30: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
! 31: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
! 32: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
! 33: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
! 34: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
! 35: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
! 36: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
! 37: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
! 38: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
! 39: * SUCH DAMAGE.
! 40: *
! 41: * @(#)bsd_audioreg.h 8.1 (Berkeley) 6/11/93
! 42: */
! 43:
! 44: /*
! 45: * Bit encodings for chip commands from "Microprocessor Access Guide for
! 46: * Indirect Registers", p.19 Am79C30A/32A Advanced Micro Devices spec
! 47: * sheet (preliminary).
! 48: *
! 49: * Indirect register numbers (the value written into cr to select a given
! 50: * chip registers) have the form AMDR_*. Register fields look like AMD_*.
! 51: *
! 52: */
! 53:
! 54: /*
! 55: * Documentation for this chip:
! 56: * PCnet-Mobile Single Chip Wireless LAN Media Access Controller
! 57: * AMD Publication #: 20183, Rev B, Jan 1997
! 58: */
! 59:
! 60: struct amd7930 {
! 61: u_char cr; /* command register (wo) */
! 62: #define ir cr /* interrupt register (ro) */
! 63: u_char dr; /* data register (rw) */
! 64: u_char dsr1; /* D-channel status register 1 (ro) */
! 65: u_char der; /* D-channel error register (ro) */
! 66: u_char dctb; /* D-channel transmit register (wo) */
! 67: #define dcrb dctb /* D-channel receive register (ro) */
! 68: u_char bbtb; /* Bb-channel transmit register (wo) */
! 69: #define bbrb bbtb /* Bb-channel receive register (ro) */
! 70: u_char bctb; /* Bc-channel transmit register (wo) */
! 71: #define bcrb bctb /* Bc-channel receive register (ro) */
! 72: u_char dsr2; /* D-channel status register 2 (ro) */
! 73: };
! 74:
! 75: #define AMDR_INIT 0x21
! 76: #define AMD_INIT_PMS_IDLE 0x00
! 77: #define AMD_INIT_PMS_ACTIVE 0x01
! 78: #define AMD_INIT_PMS_ACTIVE_DATA 0x02
! 79: #define AMD_INIT_INT_DISABLE (0x01 << 2)
! 80: #define AMD_INIT_CDS_DIV2 (0x00 << 3)
! 81: #define AMD_INIT_CDS_DIV1 (0x01 << 3)
! 82: #define AMD_INIT_CDS_DIV4 (0x02 << 3)
! 83: #define AMD_INIT_AS_RX (0x01 << 6)
! 84: #define AMD_INIT_AS_TX (0x01 << 7)
! 85:
! 86: #define AMDR_LIU_LSR 0xa1
! 87: #define AMDR_LIU_LPR 0xa2
! 88: #define AMDR_LIU_LMR1 0xa3
! 89: #define AMDR_LIU_LMR2 0xa4
! 90: #define AMDR_LIU_2_4 0xa5
! 91: #define AMDR_LIU_MF 0xa6
! 92: #define AMDR_LIU_MFSB 0xa7
! 93: #define AMDR_LIU_MFQB 0xa8
! 94:
! 95: #define AMDR_MUX_MCR1 0x41
! 96: #define AMDR_MUX_MCR2 0x42
! 97: #define AMDR_MUX_MCR3 0x43
! 98: #define AMD_MCRCHAN_NC 0x00
! 99: #define AMD_MCRCHAN_B1 0x01
! 100: #define AMD_MCRCHAN_B2 0x02
! 101: #define AMD_MCRCHAN_BA 0x03
! 102: #define AMD_MCRCHAN_BB 0x04
! 103: #define AMD_MCRCHAN_BC 0x05
! 104: #define AMD_MCRCHAN_BD 0x06
! 105: #define AMD_MCRCHAN_BE 0x07
! 106: #define AMD_MCRCHAN_BF 0x08
! 107: #define AMDR_MUX_MCR4 0x44
! 108: #define AMD_MCR4_INT_ENABLE (1 << 3)
! 109: #define AMD_MCR4_SWAPBB (1 << 4)
! 110: #define AMD_MCR4_SWAPBC (1 << 5)
! 111:
! 112: #define AMDR_MUX_1_4 0x45
! 113:
! 114: #define AMDR_MAP_X 0x61
! 115: #define AMDR_MAP_R 0x62
! 116: #define AMDR_MAP_GX 0x63
! 117: #define AMDR_MAP_GR 0x64
! 118: #define AMDR_MAP_GER 0x65
! 119: #define AMDR_MAP_STG 0x66
! 120: #define AMDR_MAP_FTGR 0x67
! 121: #define AMDR_MAP_ATGR 0x68
! 122: #define AMDR_MAP_MMR1 0x69
! 123: #define AMD_MMR1_ALAW 0x01
! 124: #define AMD_MMR1_GX 0x02
! 125: #define AMD_MMR1_GR 0x04
! 126: #define AMD_MMR1_GER 0x08
! 127: #define AMD_MMR1_X 0x10
! 128: #define AMD_MMR1_R 0x20
! 129: #define AMD_MMR1_STG 0x40
! 130: #define AMD_MMR1_LOOP 0x80
! 131: #define AMDR_MAP_MMR2 0x6a
! 132: #define AMD_MMR2_AINB 0x01
! 133: #define AMD_MMR2_LS 0x02
! 134: #define AMD_MMR2_DTMF 0x04
! 135: #define AMD_MMR2_GEN 0x08
! 136: #define AMD_MMR2_RNG 0x10
! 137: #define AMD_MMR2_DIS_HPF 0x20
! 138: #define AMD_MMR2_DIS_AZ 0x40
! 139: #define AMDR_MAP_1_10 0x6b
! 140:
! 141: #define AMDR_DLC_FRAR123 0x81
! 142: #define AMDR_DLC_SRAR123 0x82
! 143: #define AMDR_DLC_TAR 0x83
! 144: #define AMDR_DLC_DRLR 0x84
! 145: #define AMDR_DLC_DTCR 0x85
! 146: #define AMDR_DLC_DMR1 0x86
! 147: #define AMDR_DLC_DMR2 0x87
! 148: #define AMDR_DLC_1_7 0x88
! 149: #define AMDR_DLC_DRCR 0x89
! 150: #define AMDR_DLC_RNGR1 0x8a
! 151: #define AMDR_DLC_RNGR2 0x8b
! 152: #define AMDR_DLC_FRAR4 0x8c
! 153: #define AMDR_DLC_SRAR4 0x8d
! 154: #define AMDR_DLC_DMR3 0x8e
! 155: #define AMDR_DLC_DMR4 0x8f
! 156: #define AMDR_DLC_12_15 0x90
! 157: #define AMDR_DLC_ASR 0x91
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