Annotation of sys/dev/ic/aic6360reg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: aic6360reg.h,v 1.2 2003/11/08 19:17:28 jmc Exp $ */
2: /* $NetBSD: aic6360.c,v 1.52 1996/12/10 21:27:51 thorpej Exp $ */
3:
4: /*
5: * Copyright (c) 1994, 1995, 1996 Charles Hannum. All rights reserved.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: * 3. All advertising materials mentioning features or use of this software
16: * must display the following acknowledgement:
17: * This product includes software developed by Charles M. Hannum.
18: * 4. The name of the author may not be used to endorse or promote products
19: * derived from this software without specific prior written permission.
20: *
21: * Copyright (c) 1994 Jarle Greipsland
22: * All rights reserved.
23: *
24: * Redistribution and use in source and binary forms, with or without
25: * modification, are permitted provided that the following conditions
26: * are met:
27: * 1. Redistributions of source code must retain the above copyright
28: * notice, this list of conditions and the following disclaimer.
29: * 2. Redistributions in binary form must reproduce the above copyright
30: * notice, this list of conditions and the following disclaimer in the
31: * documentation and/or other materials provided with the distribution.
32: * 3. The name of the author may not be used to endorse or promote products
33: * derived from this software without specific prior written permission.
34: *
35: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
36: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
37: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
38: * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
39: * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
40: * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
41: * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
42: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
43: * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
44: * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
45: * POSSIBILITY OF SUCH DAMAGE.
46: */
47:
48: /*
49: * Acknowledgements: Many of the algorithms used in this driver are
50: * inspired by the work of Julian Elischer (julian@tfs.com) and
51: * Charles Hannum (mycroft@duality.gnu.ai.mit.edu). Thanks a million!
52: */
53:
54: /* Definitions, most of them have turned out to be unnecessary, but here they
55: * are anyway.
56: */
57:
58: /* AIC6360 definitions */
59: #define SCSISEQ 0x00 /* SCSI sequence control */
60: #define SXFRCTL0 0x01 /* SCSI transfer control 0 */
61: #define SXFRCTL1 0x02 /* SCSI transfer control 1 */
62: #define SCSISIG 0x03 /* SCSI signal in/out */
63: #define SCSIRATE 0x04 /* SCSI rate control */
64: #define SCSIID 0x05 /* SCSI ID */
65: #define SELID 0x05 /* Selection/Reselection ID */
66: #define SCSIDAT 0x06 /* SCSI Latched Data */
67: #define SCSIBUS 0x07 /* SCSI Data Bus*/
68: #define STCNT0 0x08 /* SCSI transfer count */
69: #define STCNT1 0x09
70: #define STCNT2 0x0a
71: #define CLRSINT0 0x0b /* Clear SCSI interrupts 0 */
72: #define SSTAT0 0x0b /* SCSI interrupt status 0 */
73: #define CLRSINT1 0x0c /* Clear SCSI interrupts 1 */
74: #define SSTAT1 0x0c /* SCSI status 1 */
75: #define SSTAT2 0x0d /* SCSI status 2 */
76: #define SCSITEST 0x0e /* SCSI test control */
77: #define SSTAT3 0x0e /* SCSI status 3 */
78: #define CLRSERR 0x0f /* Clear SCSI errors */
79: #define SSTAT4 0x0f /* SCSI status 4 */
80: #define SIMODE0 0x10 /* SCSI interrupt mode 0 */
81: #define SIMODE1 0x11 /* SCSI interrupt mode 1 */
82: #define DMACNTRL0 0x12 /* DMA control 0 */
83: #define DMACNTRL1 0x13 /* DMA control 1 */
84: #define DMASTAT 0x14 /* DMA status */
85: #define FIFOSTAT 0x15 /* FIFO status */
86: #define DMADATA 0x16 /* DMA data */
87: #define DMADATAL 0x16 /* DMA data low byte */
88: #define DMADATAH 0x17 /* DMA data high byte */
89: #define BRSTCNTRL 0x18 /* Burst Control */
90: #define DMADATALONG 0x18
91: #define PORTA 0x1a /* Port A */
92: #define PORTB 0x1b /* Port B */
93: #define REV 0x1c /* Revision (001 for 6360) */
94: #define STACK 0x1d /* Stack */
95: #define TEST 0x1e /* Test register */
96: #define ID 0x1f /* ID register */
97:
98: #define IDSTRING "(C)1991ADAPTECAIC6360 "
99:
100: /* What all the bits do */
101:
102: /* SCSISEQ */
103: #define TEMODEO 0x80
104: #define ENSELO 0x40
105: #define ENSELI 0x20
106: #define ENRESELI 0x10
107: #define ENAUTOATNO 0x08
108: #define ENAUTOATNI 0x04
109: #define ENAUTOATNP 0x02
110: #define SCSIRSTO 0x01
111:
112: /* SXFRCTL0 */
113: #define SCSIEN 0x80
114: #define DMAEN 0x40
115: #define CHEN 0x20
116: #define CLRSTCNT 0x10
117: #define SPIOEN 0x08
118: #define CLRCH 0x02
119:
120: /* SXFRCTL1 */
121: #define BITBUCKET 0x80
122: #define SWRAPEN 0x40
123: #define ENSPCHK 0x20
124: #define STIMESEL1 0x10
125: #define STIMESEL0 0x08
126: #define STIMO_256ms 0x00
127: #define STIMO_128ms 0x08
128: #define STIMO_64ms 0x10
129: #define STIMO_32ms 0x18
130: #define ENSTIMER 0x04
131: #define BYTEALIGN 0x02
132:
133: /* SCSISIG (in) */
134: #define CDI 0x80
135: #define IOI 0x40
136: #define MSGI 0x20
137: #define ATNI 0x10
138: #define SELI 0x08
139: #define BSYI 0x04
140: #define REQI 0x02
141: #define ACKI 0x01
142:
143: /* Important! The 3 most significant bits of this register, in initiator mode,
144: * represents the "expected" SCSI bus phase and can be used to trigger phase
145: * mismatch and phase change interrupts. But more important: If there is a
146: * phase mismatch the chip will not transfer any data! This is actually a nice
147: * feature as it gives us a bit more control over what is happening when we are
148: * bursting data (in) through the FIFOs and the phase suddenly changes from
149: * DATA IN to STATUS or MESSAGE IN. The transfer will stop and wait for the
150: * proper phase to be set in this register instead of dumping the bits into the
151: * FIFOs.
152: */
153: /* SCSISIG (out) */
154: #define CDO 0x80
155: #define IOO 0x40
156: #define MSGO 0x20
157: #define ATNO 0x10
158: #define SELO 0x08
159: #define BSYO 0x04
160: #define REQO 0x02
161: #define ACKO 0x01
162:
163: /* Information transfer phases */
164: #define PH_DATAOUT (0)
165: #define PH_DATAIN (IOI)
166: #define PH_CMD (CDI)
167: #define PH_STAT (CDI | IOI)
168: #define PH_MSGOUT (MSGI | CDI)
169: #define PH_MSGIN (MSGI | CDI | IOI)
170:
171: #define PH_MASK (MSGI | CDI | IOI)
172:
173: #define PH_INVALID 0xff
174:
175: /* SCSIRATE */
176: #define SXFR2 0x40
177: #define SXFR1 0x20
178: #define SXFR0 0x10
179: #define SOFS3 0x08
180: #define SOFS2 0x04
181: #define SOFS1 0x02
182: #define SOFS0 0x01
183:
184: /* SCSI ID */
185: #define OID2 0x40
186: #define OID1 0x20
187: #define OID0 0x10
188: #define OID_S 4 /* shift value */
189: #define TID2 0x04
190: #define TID1 0x02
191: #define TID0 0x01
192: #define SCSI_ID_MASK 0x7
193:
194: /* SCSI selection/reselection ID (both target *and* initiator) */
195: #define SELID7 0x80
196: #define SELID6 0x40
197: #define SELID5 0x20
198: #define SELID4 0x10
199: #define SELID3 0x08
200: #define SELID2 0x04
201: #define SELID1 0x02
202: #define SELID0 0x01
203:
204: /* CLRSINT0 Clears what? (interrupt and/or status bit) */
205: #define SETSDONE 0x80
206: #define CLRSELDO 0x40 /* I */
207: #define CLRSELDI 0x20 /* I+ */
208: #define CLRSELINGO 0x10 /* I */
209: #define CLRSWRAP 0x08 /* I+S */
210: #define CLRSDONE 0x04 /* I+S */
211: #define CLRSPIORDY 0x02 /* I */
212: #define CLRDMADONE 0x01 /* I */
213:
214: /* SSTAT0 Howto clear */
215: #define TARGET 0x80
216: #define SELDO 0x40 /* Selfclearing */
217: #define SELDI 0x20 /* Selfclearing when CLRSELDI is set */
218: #define SELINGO 0x10 /* Selfclearing */
219: #define SWRAP 0x08 /* CLRSWAP */
220: #define SDONE 0x04 /* Not used in initiator mode */
221: #define SPIORDY 0x02 /* Selfclearing (op on SCSIDAT) */
222: #define DMADONE 0x01 /* Selfclearing (all FIFOs empty & T/C */
223:
224: /* CLRSINT1 Clears what? */
225: #define CLRSELTIMO 0x80 /* I+S */
226: #define CLRATNO 0x40
227: #define CLRSCSIRSTI 0x20 /* I+S */
228: #define CLRBUSFREE 0x08 /* I+S */
229: #define CLRSCSIPERR 0x04 /* I+S */
230: #define CLRPHASECHG 0x02 /* I+S */
231: #define CLRREQINIT 0x01 /* I+S */
232:
233: /* SSTAT1 How to clear? When set?*/
234: #define SELTO 0x80 /* C select out timeout */
235: #define ATNTARG 0x40 /* Not used in initiator mode */
236: #define SCSIRSTI 0x20 /* C RST asserted */
237: #define PHASEMIS 0x10 /* Selfclearing */
238: #define BUSFREE 0x08 /* C bus free condition */
239: #define SCSIPERR 0x04 /* C parity error on inbound data */
240: #define PHASECHG 0x02 /* C phase in SCSISIG doesn't match */
241: #define REQINIT 0x01 /* C or ACK asserting edge of REQ */
242:
243: /* SSTAT2 */
244: #define SOFFSET 0x20
245: #define SEMPTY 0x10
246: #define SFULL 0x08
247: #define SFCNT2 0x04
248: #define SFCNT1 0x02
249: #define SFCNT0 0x01
250:
251: /* SCSITEST */
252: #define SCTESTU 0x08
253: #define SCTESTD 0x04
254: #define STCTEST 0x01
255:
256: /* SSTAT3 */
257: #define SCSICNT3 0x80
258: #define SCSICNT2 0x40
259: #define SCSICNT1 0x20
260: #define SCSICNT0 0x10
261: #define OFFCNT3 0x08
262: #define OFFCNT2 0x04
263: #define OFFCNT1 0x02
264: #define OFFCNT0 0x01
265:
266: /* CLRSERR */
267: #define CLRSYNCERR 0x04
268: #define CLRFWERR 0x02
269: #define CLRFRERR 0x01
270:
271: /* SSTAT4 */
272: #define SYNCERR 0x04
273: #define FWERR 0x02
274: #define FRERR 0x01
275:
276: /* SIMODE0 */
277: #define ENSELDO 0x40
278: #define ENSELDI 0x20
279: #define ENSELINGO 0x10
280: #define ENSWRAP 0x08
281: #define ENSDONE 0x04
282: #define ENSPIORDY 0x02
283: #define ENDMADONE 0x01
284:
285: /* SIMODE1 */
286: #define ENSELTIMO 0x80
287: #define ENATNTARG 0x40
288: #define ENSCSIRST 0x20
289: #define ENPHASEMIS 0x10
290: #define ENBUSFREE 0x08
291: #define ENSCSIPERR 0x04
292: #define ENPHASECHG 0x02
293: #define ENREQINIT 0x01
294:
295: /* DMACNTRL0 */
296: #define ENDMA 0x80
297: #define B8MODE 0x40
298: #define DMA 0x20
299: #define DWORDPIO 0x10
300: #define WRITE 0x08
301: #define INTEN 0x04
302: #define RSTFIFO 0x02
303: #define SWINT 0x01
304:
305: /* DMACNTRL1 */
306: #define PWRDWN 0x80
307: #define ENSTK32 0x40
308: #define STK4 0x10
309: #define STK3 0x08
310: #define STK2 0x04
311: #define STK1 0x02
312: #define STK0 0x01
313:
314: /* DMASTAT */
315: #define ATDONE 0x80
316: #define WORDRDY 0x40
317: #define INTSTAT 0x20
318: #define DFIFOFULL 0x10
319: #define DFIFOEMP 0x08
320: #define DFIFOHF 0x04
321: #define DWORDRDY 0x02
322:
323: /* BRSTCNTRL */
324: #define BON3 0x80
325: #define BON2 0x40
326: #define BON1 0x20
327: #define BON0 0x10
328: #define BOFF3 0x08
329: #define BOFF2 0x04
330: #define BOFF1 0x02
331: #define BOFF0 0x01
332:
333: /* TEST */
334: #define BOFFTMR 0x40
335: #define BONTMR 0x20
336: #define STCNTH 0x10
337: #define STCNTM 0x08
338: #define STCNTL 0x04
339: #define SCSIBLK 0x02
340: #define DMABLK 0x01
341:
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