Annotation of sys/dev/ic/adwlib.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: adwlib.h,v 1.10 2002/03/14 01:26:53 millert Exp $ */
! 2: /* $NetBSD: adwlib.h,v 1.14 2000/07/03 18:14:18 dante Exp $ */
! 3:
! 4: /*
! 5: * Definitions for low level routines and data structures
! 6: * for the Advanced Systems Inc. SCSI controllers chips.
! 7: *
! 8: * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
! 9: * All rights reserved.
! 10: *
! 11: * Author: Baldassare Dante Profeta <dante@mclink.it>
! 12: *
! 13: * Redistribution and use in source and binary forms, with or without
! 14: * modification, are permitted provided that the following conditions
! 15: * are met:
! 16: * 1. Redistributions of source code must retain the above copyright
! 17: * notice, this list of conditions and the following disclaimer.
! 18: * 2. Redistributions in binary form must reproduce the above copyright
! 19: * notice, this list of conditions and the following disclaimer in the
! 20: * documentation and/or other materials provided with the distribution.
! 21: * 3. All advertising materials mentioning features or use of this software
! 22: * must display the following acknowledgement:
! 23: * This product includes software developed by the NetBSD
! 24: * Foundation, Inc. and its contributors.
! 25: * 4. Neither the name of The NetBSD Foundation nor the names of its
! 26: * contributors may be used to endorse or promote products derived
! 27: * from this software without specific prior written permission.
! 28: *
! 29: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
! 30: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
! 31: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
! 32: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
! 33: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
! 34: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
! 35: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
! 36: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
! 37: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
! 38: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
! 39: * POSSIBILITY OF SUCH DAMAGE.
! 40: */
! 41: /*
! 42: * Ported from:
! 43: */
! 44: /*
! 45: * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
! 46: *
! 47: * Copyright (c) 1995-2000 Advanced System Products, Inc.
! 48: * All Rights Reserved.
! 49: *
! 50: * Redistribution and use in source and binary forms, with or without
! 51: * modification, are permitted provided that redistributions of source
! 52: * code retain the above copyright notice and this comment without
! 53: * modification.
! 54: */
! 55:
! 56: #ifndef _ADVANSYS_WIDE_LIBRARY_H_
! 57: #define _ADVANSYS_WIDE_LIBRARY_H_
! 58:
! 59:
! 60: /*
! 61: * --- Adw Library Constants and Macros
! 62: */
! 63:
! 64: #define ADW_LIB_VERSION_MAJOR 5
! 65: #define ADW_LIB_VERSION_MINOR 8
! 66:
! 67:
! 68: /* If the result wraps when calculating tenths, return 0. */
! 69: #define ADW_TENTHS(num, den) \
! 70: (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
! 71: 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
! 72:
! 73:
! 74: /*
! 75: * Define Adw Reset Hold Time grater than 25 uSec.
! 76: * See AdwResetSCSIBus() for more info.
! 77: */
! 78: #define ADW_SCSI_RESET_HOLD_TIME_US 60
! 79:
! 80: /*
! 81: * Define Adw EEPROM constants.
! 82: */
! 83:
! 84: #define ADW_EEP_DVC_CFG_BEGIN (0x00)
! 85: #define ADW_EEP_DVC_CFG_END (0x15)
! 86: #define ADW_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */
! 87: #define ADW_EEP_MAX_WORD_ADDR (0x1E)
! 88:
! 89: #define ADW_EEP_DELAY_MS 100
! 90:
! 91: /*
! 92: * EEPROM bits reference by the RISC after initialization.
! 93: */
! 94: #define ADW_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
! 95: #define ADW_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
! 96: #define ADW_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
! 97:
! 98: /*
! 99: * EEPROM configuration format
! 100: *
! 101: * Field naming convention:
! 102: *
! 103: * *_enable indicates the field enables or disables the feature. The
! 104: * value is never reset.
! 105: *
! 106: * *_able indicates both whether a feature should be enabled or disabled
! 107: * and whether a device isi capable of the feature. At initialization
! 108: * this field may be set, but later if a device is found to be incapable
! 109: * of the feature, the field is cleared.
! 110: *
! 111: * Default values are maintained in the structure Default_EEPROM_Config.
! 112: */
! 113: #define ADW_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
! 114: #define ADW_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
! 115: /*
! 116: * For the ASC3550 Bit 13 is Termination Polarity control bit.
! 117: * For later ICs Bit 13 controls whether the CIS (Card Information
! 118: * Service Section) is loaded from EEPROM.
! 119: */
! 120: #define ADW_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
! 121: #define ADW_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */
! 122:
! 123: /*
! 124: * ASC38C1600 Bit 11
! 125: *
! 126: * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
! 127: * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
! 128: * Function 0 will specify INT B.
! 129: *
! 130: * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
! 131: * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
! 132: * Function 1 will specify INT A.
! 133: */
! 134: #define ADW_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */
! 135:
! 136: typedef struct adw_eeprom
! 137: {
! 138: /* Word Offset, Description */
! 139:
! 140: u_int16_t cfg_lsw; /* 00 power up initialization */
! 141: /* bit 13 set - Term Polarity Control */
! 142: /* bit 14 set - BIOS Enable */
! 143: /* bit 15 set - Big Endian Mode */
! 144: u_int16_t cfg_msw; /* 01 unused */
! 145: u_int16_t disc_enable; /* 02 disconnect enable */
! 146: u_int16_t wdtr_able; /* 03 Wide DTR able */
! 147: union {
! 148: u_int16_t sdtr_able; /* 04 Synchronous DTR able */
! 149: u_int16_t sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
! 150: } sdtr1;
! 151: u_int16_t start_motor; /* 05 send start up motor */
! 152: u_int16_t tagqng_able; /* 06 tag queuing able */
! 153: u_int16_t bios_scan; /* 07 BIOS device control */
! 154: u_int16_t scam_tolerant; /* 08 no scam */
! 155:
! 156: u_int8_t adapter_scsi_id; /* 09 Host Adapter ID */
! 157: u_int8_t bios_boot_delay; /* power up wait */
! 158:
! 159: u_int8_t scsi_reset_delay; /* 10 reset delay */
! 160: u_int8_t bios_id_lun; /* first boot device scsi id & lun */
! 161: /* high nibble is lun */
! 162: /* low nibble is scsi id */
! 163:
! 164: u_int8_t termination_se; /* 11 0 - automatic */
! 165: /* 1 - low off / high off */
! 166: /* 2 - low off / high on */
! 167: /* 3 - low on / high on */
! 168: /* There is no low on / high off */
! 169:
! 170: u_int8_t termination_lvd; /* 11 0 - automatic */
! 171: /* 1 - low off / high off */
! 172: /* 2 - low off / high on */
! 173: /* 3 - low on / high on */
! 174: /* There is no low on / high off */
! 175:
! 176: u_int16_t bios_ctrl; /* 12 BIOS control bits */
! 177: /* bit 0 BIOS don't act as initiator. */
! 178: /* bit 1 BIOS > 1 GB support */
! 179: /* bit 2 BIOS > 2 Disk Support */
! 180: /* bit 3 BIOS don't support removables */
! 181: /* bit 4 BIOS support bootable CD */
! 182: /* bit 5 BIOS scan enabled */
! 183: /* bit 6 BIOS support multiple LUNs */
! 184: /* bit 7 BIOS display of message */
! 185: /* bit 8 SCAM disabled */
! 186: /* bit 9 Reset SCSI bus during init. */
! 187: /* bit 10 */
! 188: /* bit 11 No verbose initialization. */
! 189: /* bit 12 SCSI parity enabled */
! 190: /* bit 13 */
! 191: /* bit 14 */
! 192: /* bit 15 */
! 193: union {
! 194: u_int16_t ultra_able; /* 13 ULTRA speed able */
! 195: u_int16_t sdtr_speed2; /* 13 SDTR speed TID 4-7 */
! 196: } sdtr2;
! 197: union {
! 198: u_int16_t reserved2; /* 14 reserved */
! 199: u_int16_t sdtr_speed3; /* 14 SDTR speed TID 8-11 */
! 200: } sdtr3;
! 201: u_int8_t max_host_qng; /* 15 maximum host queuing */
! 202: u_int8_t max_dvc_qng; /* maximum per device queuing */
! 203: u_int16_t dvc_cntl; /* 16 control bit for driver */
! 204: union {
! 205: u_int16_t bug_fix; /* 17 control bit for bug fix */
! 206: u_int16_t sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
! 207: } sdtr4;
! 208: u_int16_t serial_number[3]; /* 18 - 20 Board serial number */
! 209: u_int16_t check_sum; /* 21 EEP check sum */
! 210: u_int8_t oem_name[16]; /* 22 OEM name */
! 211: u_int16_t dvc_err_code; /* 30 last device driver error code */
! 212: u_int16_t adw_err_code; /* 31 last uc and Adw Lib error code */
! 213: u_int16_t adw_err_addr; /* 32 last uc error address */
! 214: u_int16_t saved_dvc_err_code; /* 33 saved last dev. driver error code */
! 215: u_int16_t saved_adw_err_code; /* 34 saved last uc and Adw Lib error code */
! 216: u_int16_t saved_adw_err_addr; /* 35 saved last uc error address */
! 217: u_int16_t reserved1[20]; /* 36 - 55 reserved */
! 218: u_int16_t cisptr_lsw; /* 56 CIS PTR LSW */
! 219: u_int16_t cisprt_msw; /* 57 CIS PTR MSW */
! 220: u_int16_t subsysvid; /* 58 SubSystem Vendor ID */
! 221: u_int16_t subsysid; /* 59 SubSystem ID */
! 222: u_int16_t reserved2[4]; /* 60 - 63 reserved */
! 223: } ADW_EEPROM;
! 224:
! 225:
! 226: /*
! 227: * EEPROM Commands
! 228: */
! 229: #define ADW_EEP_CMD_READ 0x80
! 230: #define ADW_EEP_CMD_WRITE 0x40
! 231: #define ADW_EEP_CMD_WRITE_ABLE 0x30
! 232: #define ADW_EEP_CMD_WRITE_DISABLE 0x00
! 233:
! 234: #define ADW_EEP_CMD_DONE 0x0200
! 235: #define ADW_EEP_CMD_DONE_ERR 0x0001
! 236:
! 237: /* cfg_word */
! 238: #define EEP_CFG_WORD_BIG_ENDIAN 0x8000
! 239:
! 240: /* bios_ctrl */
! 241: #define BIOS_CTRL_BIOS 0x0001
! 242: #define BIOS_CTRL_EXTENDED_XLAT 0x0002
! 243: #define BIOS_CTRL_GT_2_DISK 0x0004
! 244: #define BIOS_CTRL_BIOS_REMOVABLE 0x0008
! 245: #define BIOS_CTRL_BOOTABLE_CD 0x0010
! 246: #define BIOS_CTRL_MULTIPLE_LUN 0x0040
! 247: #define BIOS_CTRL_DISPLAY_MSG 0x0080
! 248: #define BIOS_CTRL_NO_SCAM 0x0100
! 249: #define BIOS_CTRL_RESET_SCSI_BUS 0x0200
! 250: #define BIOS_CTRL_INIT_VERBOSE 0x0800
! 251: #define BIOS_CTRL_SCSI_PARITY 0x1000
! 252: #define BIOS_CTRL_AIPP_DIS 0x2000
! 253:
! 254: #define ADW_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
! 255: #define ADW_3550_IOLEN 0x40 /* I/O Port Range in bytes */
! 256:
! 257: #define ADW_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
! 258: #define ADW_38C0800_IOLEN 0x100 /* I/O Port Range in bytes */
! 259:
! 260: #define ADW_38C1600_MEMSIZE 0x8000 /* 32 KB Internal Memory */
! 261: #define ADW_38C1600_IOLEN 0x100 /* I/O Port Range 256 bytes */
! 262: #define ADW_38C1600_MEMLEN 0x1000 /* Memory Range 4KB bytes */
! 263:
! 264: /*
! 265: * Byte I/O register address from base of 'iop_base'.
! 266: */
! 267: #define IOPB_INTR_STATUS_REG 0x00
! 268: #define IOPB_CHIP_ID_1 0x01
! 269: #define IOPB_INTR_ENABLES 0x02
! 270: #define IOPB_CHIP_TYPE_REV 0x03
! 271: #define IOPB_RES_ADDR_4 0x04
! 272: #define IOPB_RES_ADDR_5 0x05
! 273: #define IOPB_RAM_DATA 0x06
! 274: #define IOPB_RES_ADDR_7 0x07
! 275: #define IOPB_FLAG_REG 0x08
! 276: #define IOPB_RES_ADDR_9 0x09
! 277: #define IOPB_RISC_CSR 0x0A
! 278: #define IOPB_RES_ADDR_B 0x0B
! 279: #define IOPB_RES_ADDR_C 0x0C
! 280: #define IOPB_RES_ADDR_D 0x0D
! 281: #define IOPB_SOFT_OVER_WR 0x0E
! 282: #define IOPB_RES_ADDR_F 0x0F
! 283: #define IOPB_MEM_CFG 0x10
! 284: #define IOPB_RES_ADDR_11 0x11
! 285: #define IOPB_GPIO_DATA 0x12
! 286: #define IOPB_RES_ADDR_13 0x13
! 287: #define IOPB_FLASH_PAGE 0x14
! 288: #define IOPB_RES_ADDR_15 0x15
! 289: #define IOPB_GPIO_CNTL 0x16
! 290: #define IOPB_RES_ADDR_17 0x17
! 291: #define IOPB_FLASH_DATA 0x18
! 292: #define IOPB_RES_ADDR_19 0x19
! 293: #define IOPB_RES_ADDR_1A 0x1A
! 294: #define IOPB_RES_ADDR_1B 0x1B
! 295: #define IOPB_RES_ADDR_1C 0x1C
! 296: #define IOPB_RES_ADDR_1D 0x1D
! 297: #define IOPB_RES_ADDR_1E 0x1E
! 298: #define IOPB_RES_ADDR_1F 0x1F
! 299: #define IOPB_DMA_CFG0 0x20
! 300: #define IOPB_DMA_CFG1 0x21
! 301: #define IOPB_TICKLE 0x22
! 302: #define IOPB_DMA_REG_WR 0x23
! 303: #define IOPB_SDMA_STATUS 0x24
! 304: #define IOPB_SCSI_BYTE_CNT 0x25
! 305: #define IOPB_HOST_BYTE_CNT 0x26
! 306: #define IOPB_BYTE_LEFT_TO_XFER 0x27
! 307: #define IOPB_BYTE_TO_XFER_0 0x28
! 308: #define IOPB_BYTE_TO_XFER_1 0x29
! 309: #define IOPB_BYTE_TO_XFER_2 0x2A
! 310: #define IOPB_BYTE_TO_XFER_3 0x2B
! 311: #define IOPB_ACC_GRP 0x2C
! 312: #define IOPB_RES_ADDR_2D 0x2D
! 313: #define IOPB_DEV_ID 0x2E
! 314: #define IOPB_RES_ADDR_2F 0x2F
! 315: #define IOPB_SCSI_DATA 0x30
! 316: #define IOPB_RES_ADDR_31 0x31
! 317: #define IOPB_RES_ADDR_32 0x32
! 318: #define IOPB_SCSI_DATA_HSHK 0x33
! 319: #define IOPB_SCSI_CTRL 0x34
! 320: #define IOPB_RES_ADDR_35 0x35
! 321: #define IOPB_RES_ADDR_36 0x36
! 322: #define IOPB_RES_ADDR_37 0x37
! 323: #define IOPB_RAM_BIST 0x38
! 324: #define IOPB_PLL_TEST 0x39
! 325: #define IOPB_PCI_INT_CFG 0x3A
! 326: #define IOPB_RES_ADDR_3B 0x3B
! 327: #define IOPB_RFIFO_CNT 0x3C
! 328: #define IOPB_RES_ADDR_3D 0x3D
! 329: #define IOPB_RES_ADDR_3E 0x3E
! 330: #define IOPB_RES_ADDR_3F 0x3F
! 331:
! 332: /*
! 333: * Word I/O register address from base of 'iop_base'.
! 334: */
! 335: #define IOPW_CHIP_ID_0 0x00 /* CID0 */
! 336: #define IOPW_CTRL_REG 0x02 /* CC */
! 337: #define IOPW_RAM_ADDR 0x04 /* LA */
! 338: #define IOPW_RAM_DATA 0x06 /* LD */
! 339: #define IOPW_RES_ADDR_08 0x08
! 340: #define IOPW_RISC_CSR 0x0A /* CSR */
! 341: #define IOPW_SCSI_CFG0 0x0C /* CFG0 */
! 342: #define IOPW_SCSI_CFG1 0x0E /* CFG1 */
! 343: #define IOPW_RES_ADDR_10 0x10
! 344: #define IOPW_SEL_MASK 0x12 /* SM */
! 345: #define IOPW_RES_ADDR_14 0x14
! 346: #define IOPW_FLASH_ADDR 0x16 /* FA */
! 347: #define IOPW_RES_ADDR_18 0x18
! 348: #define IOPW_EE_CMD 0x1A /* EC */
! 349: #define IOPW_EE_DATA 0x1C /* ED */
! 350: #define IOPW_SFIFO_CNT 0x1E /* SFC */
! 351: #define IOPW_RES_ADDR_20 0x20
! 352: #define IOPW_Q_BASE 0x22 /* QB */
! 353: #define IOPW_QP 0x24 /* QP */
! 354: #define IOPW_IX 0x26 /* IX */
! 355: #define IOPW_SP 0x28 /* SP */
! 356: #define IOPW_PC 0x2A /* PC */
! 357: #define IOPW_RES_ADDR_2C 0x2C
! 358: #define IOPW_RES_ADDR_2E 0x2E
! 359: #define IOPW_SCSI_DATA 0x30 /* SD */
! 360: #define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */
! 361: #define IOPW_SCSI_CTRL 0x34 /* SC */
! 362: #define IOPW_HSHK_CFG 0x36 /* HCFG */
! 363: #define IOPW_SXFR_STATUS 0x36 /* SXS */
! 364: #define IOPW_SXFR_CNTL 0x38 /* SXL */
! 365: #define IOPW_SXFR_CNTH 0x3A /* SXH */
! 366: #define IOPW_RES_ADDR_3C 0x3C
! 367: #define IOPW_RFIFO_DATA 0x3E /* RFD */
! 368:
! 369: /*
! 370: * Doubleword I/O register address from base of 'iop_base'.
! 371: */
! 372: #define IOPDW_RES_ADDR_0 0x00
! 373: #define IOPDW_RAM_DATA 0x04
! 374: #define IOPDW_RES_ADDR_8 0x08
! 375: #define IOPDW_RES_ADDR_C 0x0C
! 376: #define IOPDW_RES_ADDR_10 0x10
! 377: #define IOPDW_COMMA 0x14
! 378: #define IOPDW_COMMB 0x18
! 379: #define IOPDW_RES_ADDR_1C 0x1C
! 380: #define IOPDW_SDMA_ADDR0 0x20
! 381: #define IOPDW_SDMA_ADDR1 0x24
! 382: #define IOPDW_SDMA_COUNT 0x28
! 383: #define IOPDW_SDMA_ERROR 0x2C
! 384: #define IOPDW_RDMA_ADDR0 0x30
! 385: #define IOPDW_RDMA_ADDR1 0x34
! 386: #define IOPDW_RDMA_COUNT 0x38
! 387: #define IOPDW_RDMA_ERROR 0x3C
! 388:
! 389: #define ADW_CHIP_ID_BYTE 0x25
! 390: #define ADW_CHIP_ID_WORD 0x04C1
! 391:
! 392: #define ADW_SC_SCSI_BUS_RESET 0x2000
! 393:
! 394: #define ADW_INTR_ENABLE_HOST_INTR 0x01
! 395: #define ADW_INTR_ENABLE_SEL_INTR 0x02
! 396: #define ADW_INTR_ENABLE_DPR_INTR 0x04
! 397: #define ADW_INTR_ENABLE_RTA_INTR 0x08
! 398: #define ADW_INTR_ENABLE_RMA_INTR 0x10
! 399: #define ADW_INTR_ENABLE_RST_INTR 0x20
! 400: #define ADW_INTR_ENABLE_DPE_INTR 0x40
! 401: #define ADW_INTR_ENABLE_GLOBAL_INTR 0x80
! 402:
! 403: #define ADW_INTR_STATUS_INTRA 0x01
! 404: #define ADW_INTR_STATUS_INTRB 0x02
! 405: #define ADW_INTR_STATUS_INTRC 0x04
! 406:
! 407: #define ADW_RISC_CSR_STOP (0x0000)
! 408: #define ADW_RISC_TEST_COND (0x2000)
! 409: #define ADW_RISC_CSR_RUN (0x4000)
! 410: #define ADW_RISC_CSR_SINGLE_STEP (0x8000)
! 411:
! 412: #define ADW_CTRL_REG_HOST_INTR 0x0100
! 413: #define ADW_CTRL_REG_SEL_INTR 0x0200
! 414: #define ADW_CTRL_REG_DPR_INTR 0x0400
! 415: #define ADW_CTRL_REG_RTA_INTR 0x0800
! 416: #define ADW_CTRL_REG_RMA_INTR 0x1000
! 417: #define ADW_CTRL_REG_RES_BIT14 0x2000
! 418: #define ADW_CTRL_REG_DPE_INTR 0x4000
! 419: #define ADW_CTRL_REG_POWER_DONE 0x8000
! 420: #define ADW_CTRL_REG_ANY_INTR 0xFF00
! 421:
! 422: #define ADW_CTRL_REG_CMD_RESET 0x00C6
! 423: #define ADW_CTRL_REG_CMD_WR_IO_REG 0x00C5
! 424: #define ADW_CTRL_REG_CMD_RD_IO_REG 0x00C4
! 425: #define ADW_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3
! 426: #define ADW_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2
! 427:
! 428: #define ADW_TICKLE_NOP 0x00
! 429: #define ADW_TICKLE_A 0x01
! 430: #define ADW_TICKLE_B 0x02
! 431: #define ADW_TICKLE_C 0x03
! 432:
! 433: #define ADW_SCSI_CTRL_RSTOUT 0x2000
! 434:
! 435: #define ADW_IS_INT_PENDING(iot, ioh) \
! 436: (ADW_READ_WORD_REGISTER((iot), (ioh), IOPW_CTRL_REG) & ADW_CTRL_REG_HOST_INTR)
! 437:
! 438: /*
! 439: * SCSI_CFG0 Register bit definitions
! 440: */
! 441: #define ADW_TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */
! 442: #define ADW_PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */
! 443: #define ADW_EVEN_PARITY 0x1000 /* Select Even Parity */
! 444: #define ADW_WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */
! 445: #define ADW_QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */
! 446: #define ADW_PRIM_MODE 0x0100 /* Primitive SCSI mode */
! 447: #define ADW_SCAM_EN 0x0080 /* Enable SCAM selection */
! 448: #define ADW_SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
! 449: #define ADW_CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
! 450: #define ADW_OUR_ID_EN 0x0010 /* Enable OUR_ID bits */
! 451: #define ADW_OUR_ID 0x000F /* SCSI ID */
! 452:
! 453: /*
! 454: * SCSI_CFG1 Register bit definitions
! 455: */
! 456: #define ADW_BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */
! 457: #define ADW_TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
! 458: #define ADW_SLEW_RATE 0x1000 /* SCSI output buffer slew rate */
! 459: #define ADW_FILTER_SEL 0x0C00 /* Filter Period Selection */
! 460: #define ADW_FLTR_DISABLE 0x0000 /* Input Filtering Disabled */
! 461: #define ADW_FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
! 462: #define ADW_FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
! 463: #define ADW_ACTIVE_DBL 0x0200 /* Disable Active Negation */
! 464: #define ADW_DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */
! 465: #define ADW_DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */
! 466: #define ADW_TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */
! 467: #define ADW_TERM_CTL 0x0030 /* External SCSI Termination Bits */
! 468: #define ADW_TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */
! 469: #define ADW_TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */
! 470: #define ADW_CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */
! 471:
! 472: /*
! 473: * Addendum for ASC-38C0800 Chip
! 474: *
! 475: * The ASC-38C1600 Chip uses the same definitions except that the
! 476: * bus mode override bits [12:10] have been moved to byte register
! 477: * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
! 478: * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
! 479: * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
! 480: * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
! 481: * and [1:0]. Bits [14], [7:6], [3:2] are unused.
! 482: */
! 483: #define ADW_DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */
! 484: #define ADW_HVD_LVD_SE 0x1C00 /* Device Detect Bits */
! 485: #define ADW_HVD 0x1000 /* HVD Device Detect */
! 486: #define ADW_LVD 0x0800 /* LVD Device Detect */
! 487: #define ADW_SE 0x0400 /* SE Device Detect */
! 488: #define ADW_TERM_LVD 0x00C0 /* LVD Termination Bits */
! 489: #define ADW_TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */
! 490: #define ADW_TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */
! 491: #define ADW_TERM_SE 0x0030 /* SE Termination Bits */
! 492: #define ADW_TERM_SE_HI 0x0020 /* Enable SE Upper Termination */
! 493: #define ADW_TERM_SE_LO 0x0010 /* Enable SE Lower Termination */
! 494: #define ADW_C_DET_LVD 0x000C /* LVD Cable Detect Bits */
! 495: #define ADW_C_DET3 0x0008 /* Cable Detect for LVD External Wide */
! 496: #define ADW_C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */
! 497: #define ADW_C_DET_SE 0x0003 /* SE Cable Detect Bits */
! 498: #define ADW_C_DET1 0x0002 /* Cable Detect for SE Internal Wide */
! 499: #define ADW_C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */
! 500:
! 501:
! 502: #define CABLE_ILLEGAL_A 0x7
! 503: /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */
! 504:
! 505: #define CABLE_ILLEGAL_B 0xB
! 506: /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */
! 507:
! 508: /*
! 509: The following table details the SCSI_CFG1 Termination Polarity,
! 510: Termination Control and Cable Detect bits.
! 511:
! 512: Cable Detect | Termination
! 513: Bit 3 2 1 0 | 5 4 | Notes
! 514: _____________|________|____________________
! 515: 1 1 1 0 | on on | Internal wide only
! 516: 1 1 0 1 | on on | Internal narrow only
! 517: 1 0 1 1 | on on | External narrow only
! 518: 0 x 1 1 | on on | External wide only
! 519: 1 1 0 0 | on off| Internal wide and internal narrow
! 520: 1 0 1 0 | on off| Internal wide and external narrow
! 521: 0 x 1 0 | off off| Internal wide and external wide
! 522: 1 0 0 1 | on off| Internal narrow and external narrow
! 523: 0 x 0 1 | on off| Internal narrow and external wide
! 524: 1 1 1 1 | on on | No devices are attached
! 525: x 0 0 0 | on on | Illegal (all 3 connectors are used)
! 526: 0 x 0 0 | on on | Illegal (all 3 connectors are used)
! 527:
! 528: x means don't-care (either '0' or '1')
! 529:
! 530: If term_pol (bit 13) is '0' (active-low terminator enable), then:
! 531: 'on' is '0' and 'off' is '1'.
! 532:
! 533: If term_pol bit is '1' (meaning active-hi terminator enable), then:
! 534: 'on' is '1' and 'off' is '0'.
! 535: */
! 536:
! 537: /*
! 538: * MEM_CFG Register bit definitions
! 539: */
! 540: #define ADW_BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */
! 541: #define ADW_FAST_EE_CLK 0x20 /* Diagnostic Bit */
! 542: #define ADW_RAM_SZ 0x1C /* Specify size of RAM to RISC */
! 543: #define ADW_RAM_SZ_2KB 0x00 /* 2 KB */
! 544: #define ADW_RAM_SZ_4KB 0x04 /* 4 KB */
! 545: #define ADW_RAM_SZ_8KB 0x08 /* 8 KB */
! 546: #define ADW_RAM_SZ_16KB 0x0C /* 16 KB */
! 547: #define ADW_RAM_SZ_32KB 0x10 /* 32 KB */
! 548: #define ADW_RAM_SZ_64KB 0x14 /* 64 KB */
! 549:
! 550: /*
! 551: * DMA_CFG0 Register bit definitions
! 552: *
! 553: * This register is only accessible to the host.
! 554: */
! 555: #define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */
! 556: #define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */
! 557: #define FIFO_THRESH_16B 0x00 /* 16 bytes */
! 558: #define FIFO_THRESH_32B 0x20 /* 32 bytes */
! 559: #define FIFO_THRESH_48B 0x30 /* 48 bytes */
! 560: #define FIFO_THRESH_64B 0x40 /* 64 bytes */
! 561: #define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */
! 562: #define FIFO_THRESH_96B 0x60 /* 96 bytes */
! 563: #define FIFO_THRESH_112B 0x70 /* 112 bytes */
! 564: #define START_CTL 0x0C /* DMA start conditions */
! 565: #define START_CTL_TH 0x00 /* Wait threshold level (default) */
! 566: #define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */
! 567: #define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */
! 568: #define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */
! 569: #define READ_CMD 0x03 /* Memory Read Method */
! 570: #define READ_CMD_MR 0x00 /* Memory Read */
! 571: #define READ_CMD_MRL 0x02 /* Memory Read Long */
! 572: #define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */
! 573:
! 574: /*
! 575: * ASC-38C0800 RAM BIST Register bit definitions
! 576: */
! 577: #define RAM_TEST_MODE 0x80
! 578: #define PRE_TEST_MODE 0x40
! 579: #define NORMAL_MODE 0x00
! 580: #define RAM_TEST_DONE 0x10
! 581: #define RAM_TEST_STATUS 0x0F
! 582: #define RAM_TEST_HOST_ERROR 0x08
! 583: #define RAM_TEST_INTRAM_ERROR 0x04
! 584: #define RAM_TEST_RISC_ERROR 0x02
! 585: #define RAM_TEST_SCSI_ERROR 0x01
! 586: #define RAM_TEST_SUCCESS 0x00
! 587: #define PRE_TEST_VALUE 0x05
! 588: #define NORMAL_VALUE 0x00
! 589:
! 590: /*
! 591: * ASC38C1600 Definitions
! 592: *
! 593: * IOPB_PCI_INT_CFG Bit Field Definitions
! 594: */
! 595:
! 596: #define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */
! 597:
! 598: /*
! 599: * Bit 1 can be set to change the interrupt for the Function to operate in
! 600: * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
! 601: * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
! 602: * mode, otherwise the operating mode is undefined.
! 603: */
! 604: #define TOTEMPOLE 0x02
! 605:
! 606: /*
! 607: * Bit 0 can be used to change the Int Pin for the Function. The value is
! 608: * 0 by default for both Functions with Function 0 using INT A and Function
! 609: * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
! 610: * INT A is used.
! 611: *
! 612: * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
! 613: * value specified in the PCI Configuration Space.
! 614: */
! 615: #define INTAB 0x01
! 616:
! 617:
! 618: #define ADW_MAX_TID 15 /* max. target identifier */
! 619: #define ADW_MAX_LUN 7 /* max. logical unit number */
! 620:
! 621:
! 622: /*
! 623: * Adw Library Status Definitions
! 624: */
! 625: #define ADW_TRUE 1
! 626: #define ADW_FALSE 0
! 627: #define ADW_NOERROR 1
! 628: #define ADW_SUCCESS 1
! 629: #define ADW_BUSY 0
! 630: #define ADW_ERROR (-1)
! 631:
! 632:
! 633: /*
! 634: * Warning code values for AdwInitFrom*EEP() functions
! 635: */
! 636: #define ADW_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */
! 637: #define ADW_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */
! 638: #define ADW_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */
! 639: #define ADW_WARN_SET_PCI_CONFIG_SPACE 0x0080 /* PCI config space set error */
! 640: #define ADW_WARN_ERROR 0xFFFF /* ADW_ERROR return */
! 641:
! 642: /*
! 643: * Error code values for AdwInitAsc*Driver() functions
! 644: */
! 645: #define ADW_IERR_WRITE_EEPROM 0x0001 /* write EEPROM error */
! 646: #define ADW_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */
! 647: #define ADW_IERR_NO_CARRIER 0x0004 /* No more carrier memory. */
! 648: #define ADW_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */
! 649: #define ADW_IERR_CHIP_VERSION 0x0040 /* wrong chip version */
! 650: #define ADW_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */
! 651: #define ADW_IERR_HVD_DEVICE 0x0100 /* HVD attached to LVD connector. */
! 652: #define ADW_IERR_BAD_SIGNATURE 0x0200 /* signature not found */
! 653: #define ADW_IERR_ILLEGAL_CONNECTION 0x0400 /* Illegal cable connection */
! 654: #define ADW_IERR_SINGLE_END_DEVICE 0x0800 /* Single-end used w/differential */
! 655: #define ADW_IERR_REVERSED_CABLE 0x1000 /* Narrow flat cable reversed */
! 656: #define ADW_IERR_BIST_PRE_TEST 0x2000 /* BIST pre-test error */
! 657: #define ADW_IERR_BIST_RAM_TEST 0x4000 /* BIST RAM test error */
! 658: #define ADW_IERR_BAD_CHIPTYPE 0x8000 /* Invalid 'chip_type' setting. */
! 659:
! 660: /*
! 661: * BIOS LRAM variable absolute offsets.
! 662: */
! 663: #define BIOS_CODESEG 0x54
! 664: #define BIOS_CODELEN 0x56
! 665: #define BIOS_SIGNATURE 0x58
! 666: #define BIOS_VERSION 0x5A
! 667:
! 668: /*
! 669: * Chip Type flag values
! 670: */
! 671: #define ADW_CHIP_ASC3550 0x01 /* Ultra-Wide IC */
! 672: #define ADW_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */
! 673: #define ADW_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */
! 674:
! 675: /*
! 676: * Adapter temporary configuration structure
! 677: *
! 678: * This structure can be discarded after initialization. Don't add
! 679: * fields here needed after initialization.
! 680: *
! 681: * Field naming convention:
! 682: *
! 683: * *_enable indicates the field enables or disables a feature. The
! 684: * value of the field is never reset.
! 685: */
! 686: typedef struct adw_dvc_cfg {
! 687: u_int16_t disc_enable; /* enable disconnection */
! 688: u_int8_t chip_version; /* chip version */
! 689: u_int8_t termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 */
! 690: u_int16_t pci_device_id; /* PCI device code number */
! 691: u_int16_t lib_version; /* Adw Library version number */
! 692: u_int16_t control_flag; /* Microcode Control Flag */
! 693: u_int16_t mcode_date; /* Microcode date */
! 694: u_int16_t mcode_version; /* Microcode version */
! 695: u_int16_t pci_slot_info; /* high byte device/function number
! 696: bits 7-3 device num.,
! 697: bits 2-0 function num.
! 698: low byte bus num. */
! 699: u_int16_t serial1; /* EEPROM serial number word 1 */
! 700: u_int16_t serial2; /* EEPROM serial number word 2 */
! 701: u_int16_t serial3; /* EEPROM serial number word 3 */
! 702: } ADW_DVC_CFG;
! 703:
! 704:
! 705: #define NO_OF_SG_PER_BLOCK 15
! 706:
! 707: typedef struct adw_sg_block {
! 708: u_int8_t reserved1;
! 709: u_int8_t reserved2;
! 710: u_int8_t reserved3;
! 711: u_int8_t sg_cnt; /* Valid entries in block. */
! 712: u_int32_t sg_ptr; /* links to next sg block */
! 713: struct {
! 714: u_int32_t sg_addr; /* SG element address */
! 715: u_int32_t sg_count; /* SG element count */
! 716: } sg_list[NO_OF_SG_PER_BLOCK];
! 717: } ADW_SG_BLOCK;
! 718:
! 719:
! 720: /*
! 721: * Adapter operation variable structure.
! 722: *
! 723: * One structure is required per host adapter.
! 724: *
! 725: * Field naming convention:
! 726: *
! 727: * *_able indicates both whether a feature should be enabled or disabled
! 728: * and whether a device is capable of the feature. At initialization
! 729: * this field may be set, but later if a device is found to be incapable
! 730: * of the feature, the field is cleared.
! 731: */
! 732: #define CCB_HASH_SIZE 32 /* hash table size for phystokv */
! 733: #define CCB_HASH_SHIFT 9
! 734: #define CCB_HASH(x) ((((x)) >> CCB_HASH_SHIFT) & (CCB_HASH_SIZE - 1))
! 735:
! 736: typedef int (* ADW_CALLBACK) (int);
! 737:
! 738: typedef struct adw_softc {
! 739:
! 740: struct device sc_dev;
! 741:
! 742: bus_space_tag_t sc_iot;
! 743: bus_space_handle_t sc_ioh;
! 744: bus_dma_tag_t sc_dmat;
! 745: bus_dmamap_t sc_dmamap_control; /* maps the control structures */
! 746: bus_dmamap_t sc_dmamap_carrier; /* maps the carrier structures */
! 747: void *sc_ih;
! 748:
! 749: struct adw_control *sc_control; /* control structures */
! 750:
! 751: struct adw_ccb *sc_ccbhash[CCB_HASH_SIZE];
! 752: TAILQ_HEAD(, adw_ccb) sc_free_ccb, sc_waiting_ccb;
! 753: TAILQ_HEAD(adw_pending_ccb, adw_ccb) sc_pending_ccb;
! 754: struct scsi_link sc_link; /* prototype for devs */
! 755: struct scsi_adapter sc_adapter;
! 756:
! 757: LIST_HEAD(, scsi_xfer) sc_queue;
! 758: struct scsi_xfer *sc_queuelast;
! 759:
! 760: int sc_freeze_dev[ADW_MAX_TID+1];
! 761:
! 762: ADW_CALLBACK isr_callback; /* pointer to function, called in AdwISR() */
! 763: ADW_CALLBACK async_callback; /* pointer to function, called in AdwISR() */
! 764: u_int16_t bios_ctrl; /* BIOS control word, EEPROM word 12 */
! 765: u_int16_t wdtr_able; /* try WDTR for a device */
! 766: u_int16_t sdtr_able; /* try SDTR for a device */
! 767: u_int16_t ultra_able; /* try SDTR Ultra speed for a device */
! 768: u_int16_t sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */
! 769: u_int16_t sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */
! 770: u_int16_t sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */
! 771: u_int16_t sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */
! 772: u_int16_t tagqng_able; /* try tagged queuing with a device */
! 773: u_int16_t ppr_able; /* PPR message capable per TID bitmask. */
! 774: u_int16_t start_motor; /* start motor command allowed */
! 775: u_int8_t max_dvc_qng; /* maximum number of tagged commands per device */
! 776: u_int8_t scsi_reset_wait; /* delay in seconds after scsi bus reset */
! 777: u_int8_t chip_no; /* should be assigned by caller */
! 778: u_int8_t max_host_qng; /* maximum number of Q'ed command allowed */
! 779: u_int8_t irq_no; /* IRQ number */
! 780: u_int8_t chip_type; /* chip SCSI target ID */
! 781: u_int16_t no_scam; /* scam_tolerant of EEPROM */
! 782: u_int32_t drv_ptr; /* driver pointer to private structure */
! 783: u_int8_t chip_scsi_id; /* chip SCSI target ID */
! 784: u_int8_t bist_err_code;
! 785: u_int16_t carr_pending_cnt; /* Count of pending carriers. */
! 786: struct adw_carrier *carr_freelist; /* Carrier free list. */
! 787: struct adw_carrier *icq_sp; /* Initiator command queue stopper pointer. */
! 788: struct adw_carrier *irq_sp; /* Initiator response queue stopper pointer. */
! 789: /*
! 790: * Note: The following fields will not be used after initialization. The
! 791: * driver may discard the buffer after initialization is done.
! 792: */
! 793: ADW_DVC_CFG cfg; /* temporary configuration structure */
! 794: } ADW_SOFTC;
! 795:
! 796:
! 797: /*
! 798: * ADW_SCSI_REQ_Q - microcode request structure
! 799: *
! 800: * All fields in this structure up to byte 60 are used by the microcode.
! 801: * The microcode makes assumptions about the size and ordering of fields
! 802: * in this structure. Do not change the structure definition here without
! 803: * coordinating the change with the microcode.
! 804: */
! 805: typedef struct adw_scsi_req_q {
! 806: u_int8_t cntl; /* Ucode flags and state (ADW_MC_QC_*). */
! 807: u_int8_t target_cmd;
! 808: u_int8_t target_id; /* Device target identifier. */
! 809: u_int8_t target_lun; /* Device target logical unit number. */
! 810: u_int32_t data_addr; /* Data buffer physical address. */
! 811: u_int32_t data_cnt; /* Data count. Ucode sets to residual. */
! 812: u_int32_t sense_addr; /* Sense buffer physical address. */
! 813: u_int32_t carr_ba; /* Carrier p-address */
! 814: u_int8_t mflag; /* Adw Library flag field. */
! 815: u_int8_t sense_len; /* Auto-sense length. uCode sets to residual. */
! 816: u_int8_t cdb_len; /* SCSI CDB length. Must <= 16 bytes. */
! 817: u_int8_t scsi_cntl;
! 818: u_int8_t done_status; /* Completion status. (see below) */
! 819: u_int8_t scsi_status; /* SCSI status byte. (see below) */
! 820: u_int8_t host_status; /* ,uCode host status. (see below) */
! 821: u_int8_t sg_working_ix; /* ,uCode working SG variable. */
! 822: u_int8_t cdb[12]; /* SCSI CDB bytes 0-11. */
! 823: u_int32_t sg_real_addr; /* SG list physical address. */
! 824: u_int32_t scsiq_rptr; /* Internal pointer to ADW_SCSI_REQ_Q */
! 825: u_int8_t cdb16[4]; /* SCSI CDB bytes 12-15. */
! 826: u_int32_t ccb_ptr; /* CCB Physical Address */
! 827: u_int32_t carr_va; /* Carrier v-address (unused) */
! 828: /*
! 829: * End of microcode structure - 60 bytes. The rest of the structure
! 830: * is used by the Adw Library and ignored by the microcode.
! 831: */
! 832: struct scsi_sense_data *vsense_addr; /* Sense buffer virtual address. */
! 833: u_char *vdata_addr; /* Data buffer virtual address. */
! 834: } ADW_SCSI_REQ_Q;
! 835:
! 836: /*
! 837: * ADW_SCSI_REQ_Q 'done_status' return values.
! 838: */
! 839: #define QD_NO_STATUS 0x00 /* Request not completed yet. */
! 840: #define QD_NO_ERROR 0x01
! 841: #define QD_ABORTED_BY_HOST 0x02
! 842: #define QD_WITH_ERROR 0x04
! 843:
! 844: /*
! 845: * ADW_SCSI_REQ_Q 'host_status' return values.
! 846: */
! 847: #define QHSTA_NO_ERROR 0x00
! 848: #define QHSTA_M_SEL_TIMEOUT 0x11
! 849: #define QHSTA_M_DATA_OVER_RUN 0x12
! 850: #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
! 851: #define QHSTA_M_QUEUE_ABORTED 0x15
! 852: #define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */
! 853: #define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */
! 854: #define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */
! 855: #define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */
! 856: #define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */
! 857: #define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */
! 858: #define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */
! 859: /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
! 860: #define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */
! 861: #define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */
! 862: #define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */
! 863: #define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */
! 864: #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */
! 865: #define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */
! 866: #define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */
! 867: #define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */
! 868: #define QHSTA_M_WTM_TIMEOUT 0x41
! 869: #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
! 870: #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
! 871: #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
! 872: #define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */
! 873: #define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */
! 874: #define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */
! 875:
! 876: /*
! 877: * Microcode idle loop commands
! 878: */
! 879: #define IDLE_CMD_COMPLETED 0
! 880: #define IDLE_CMD_STOP_CHIP 0x0001
! 881: #define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002
! 882: #define IDLE_CMD_SEND_INT 0x0004
! 883: #define IDLE_CMD_ABORT 0x0008
! 884: #define IDLE_CMD_DEVICE_RESET 0x0010
! 885: #define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */
! 886: #define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */
! 887: #define IDLE_CMD_SCSIREQ 0x0080
! 888:
! 889: #define IDLE_CMD_STATUS_SUCCESS 0x0001
! 890: #define IDLE_CMD_STATUS_FAILURE 0x0002
! 891:
! 892: /*
! 893: * AdwSendIdleCmd() flag definitions.
! 894: */
! 895: #define ADW_NOWAIT 0x01
! 896:
! 897: /*
! 898: * Wait loop time out values.
! 899: */
! 900: #define SCSI_WAIT_10_SEC 10UL /* 10 seconds */
! 901: #define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */
! 902: #define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */
! 903: #define SCSI_MS_PER_SEC 1000UL /* milliseconds per second */
! 904: #define SCSI_MAX_RETRY 10 /* retry count */
! 905:
! 906: #define ADW_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
! 907: #define ADW_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */
! 908: #define ADW_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */
! 909:
! 910: #define ADW_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */
! 911:
! 912:
! 913: /* Read byte from a register. */
! 914: #define ADW_READ_BYTE_REGISTER(iot, ioh, reg_off) \
! 915: bus_space_read_1((iot), (ioh), (reg_off))
! 916:
! 917: /* Write byte to a register. */
! 918: #define ADW_WRITE_BYTE_REGISTER(iot, ioh, reg_off, byte) \
! 919: bus_space_write_1((iot), (ioh), (reg_off), (byte))
! 920:
! 921: /* Read word (2 bytes) from a register. */
! 922: #define ADW_READ_WORD_REGISTER(iot, ioh, reg_off) \
! 923: bus_space_read_2((iot), (ioh), (reg_off))
! 924:
! 925: /* Write word (2 bytes) to a register. */
! 926: #define ADW_WRITE_WORD_REGISTER(iot, ioh, reg_off, word) \
! 927: bus_space_write_2((iot), (ioh), (reg_off), (word))
! 928:
! 929: /* Write double word (4 bytes) to a register. */
! 930: #define ADW_WRITE_DWORD_REGISTER(iot, ioh, reg_off, dword) \
! 931: bus_space_write_4((iot), (ioh), (reg_off), (dword))
! 932:
! 933: /* Read byte from LRAM. */
! 934: #define ADW_READ_BYTE_LRAM(iot, ioh, addr, byte) \
! 935: do { \
! 936: bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \
! 937: (byte) = bus_space_read_1((iot), (ioh), IOPB_RAM_DATA); \
! 938: } while (0)
! 939:
! 940: /* Write byte to LRAM. */
! 941: #define ADW_WRITE_BYTE_LRAM(iot, ioh, addr, byte) \
! 942: do { \
! 943: bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \
! 944: bus_space_write_1((iot), (ioh), IOPB_RAM_DATA, (byte)); \
! 945: } while (0)
! 946:
! 947: /* Read word (2 bytes) from LRAM. */
! 948: #define ADW_READ_WORD_LRAM(iot, ioh, addr, word) \
! 949: do { \
! 950: bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \
! 951: (word) = bus_space_read_2((iot), (ioh), IOPW_RAM_DATA); \
! 952: } while (0)
! 953:
! 954: /* Write word (2 bytes) to LRAM. */
! 955: #define ADW_WRITE_WORD_LRAM(iot, ioh, addr, word) \
! 956: do { \
! 957: bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \
! 958: bus_space_write_2((iot), (ioh), IOPW_RAM_DATA, (word)); \
! 959: } while (0)
! 960:
! 961: /* Write double word (4 bytes) to LRAM */
! 962: /* Because of unspecified C language ordering don't use auto-increment. */
! 963: #define ADW_WRITE_DWORD_LRAM(iot, ioh, addr, dword) \
! 964: do { \
! 965: bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \
! 966: bus_space_write_2((iot), (ioh), IOPW_RAM_DATA, \
! 967: (u_int16_t) ((dword) & 0xFFFF)); \
! 968: bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr) + 2); \
! 969: bus_space_write_2((iot), (ioh), IOPW_RAM_DATA, \
! 970: (u_int16_t) ((dword >> 16) & 0xFFFF)); \
! 971: } while (0)
! 972:
! 973: /* Read word (2 bytes) from LRAM assuming that the address is already set. */
! 974: #define ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh) \
! 975: bus_space_read_2((iot), (ioh), IOPW_RAM_DATA) \
! 976:
! 977: /* Write word (2 bytes) to LRAM assuming that the address is already set. */
! 978: #define ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, word) \
! 979: bus_space_write_2((iot), (ioh), IOPW_RAM_DATA, (word))
! 980:
! 981: /*
! 982: * Define macro to check for Condor signature.
! 983: *
! 984: * Evaluate to ADW_TRUE if a Condor chip is found the specified port
! 985: * address 'iop_base'. Otherwise evalue to ADW_FALSE.
! 986: */
! 987: #define ADW_FIND_SIGNATURE(iot, ioh) \
! 988: (((ADW_READ_BYTE_REGISTER((iot), (ioh), IOPB_CHIP_ID_1) == \
! 989: ADW_CHIP_ID_BYTE) && \
! 990: (ADW_READ_WORD_REGISTER((iot), (ioh), IOPW_CHIP_ID_0) == \
! 991: ADW_CHIP_ID_WORD)) ? ADW_TRUE : ADW_FALSE)
! 992:
! 993: /*
! 994: * Define macro to Return the version number of the chip at 'iop_base'.
! 995: *
! 996: * The second parameter 'bus_type' is currently unused.
! 997: */
! 998: #define ADW_GET_CHIP_VERSION(iot, ioh, bus_type) \
! 999: ADW_READ_BYTE_REGISTER((iot), (ioh), IOPB_CHIP_TYPE_REV)
! 1000:
! 1001: /*
! 1002: * Abort a CCB in the chip's RISC Memory. The 'ccb_ptr' argument must
! 1003: * match the ADW_SCSI_REQ_Q 'ccb_ptr' field.
! 1004: *
! 1005: * If the request has not yet been sent to the device it will simply be
! 1006: * aborted from RISC memory. If the request is disconnected it will be
! 1007: * aborted on reselection by sending an Abort Message to the target ID.
! 1008: *
! 1009: * Return value:
! 1010: * ADW_TRUE(1) - ccb was successfully aborted.
! 1011: * ADW_FALSE(0) - ccb was not found on the active queue list.
! 1012: */
! 1013: #define ADW_ABORT_CCB(sc, ccb_ptr) \
! 1014: AdwSendIdleCmd((sc), (u_int16_t) IDLE_CMD_ABORT, (ccb_ptr)->hashkey)
! 1015:
! 1016: /*
! 1017: * Send a Bus Device Reset Message to the specified target ID.
! 1018: *
! 1019: * All outstanding commands will be purged if sending the
! 1020: * Bus Device Reset Message is successful.
! 1021: *
! 1022: * Return Value:
! 1023: * ADW_TRUE(1) - All requests on the target are purged.
! 1024: * ADW_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
! 1025: * are not purged.
! 1026: */
! 1027: #define ADW_RESET_DEVICE(sc, target_id) \
! 1028: AdwSendIdleCmd((sc), (u_int16_t) IDLE_CMD_DEVICE_RESET, (target_id), 0)
! 1029:
! 1030: /*
! 1031: * SCSI Wide Type definition.
! 1032: */
! 1033: #define ADW_SCSI_BIT_ID_TYPE u_int16_t
! 1034:
! 1035: /*
! 1036: * AdwInitScsiTarget() 'cntl_flag' options.
! 1037: */
! 1038: #define ADW_SCAN_LUN 0x01
! 1039: #define ADW_CAPINFO_NOLUN 0x02
! 1040:
! 1041: /*
! 1042: * Convert target id to target id bit mask.
! 1043: */
! 1044: #define ADW_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADW_MAX_TID))
! 1045:
! 1046: /*
! 1047: * SCSI Inquiry structure
! 1048: */
! 1049:
! 1050: #define INQ_CLOCKING_ST_ONLY 0x0
! 1051: #define INQ_CLOCKING_DT_ONLY 0x1
! 1052: #define INQ_CLOCKING_ST_AND_DT 0x3
! 1053:
! 1054: typedef struct {
! 1055: u_int8_t peri_dvc_type : 5; /* peripheral device type */
! 1056: u_int8_t peri_qualifier : 3; /* peripheral qualifier */
! 1057: u_int8_t dvc_type_modifier : 7; /* device type modifier (for SCSI I) */
! 1058: u_int8_t rmb : 1; /* RMB - removable medium bit */
! 1059: u_int8_t ansi_apr_ver : 3; /* ANSI approved version */
! 1060: u_int8_t ecma_ver : 3; /* ECMA version */
! 1061: u_int8_t iso_ver : 2; /* ISO version */
! 1062: u_int8_t rsp_data_fmt : 4; /* response data format */
! 1063: /* 0 SCSI 1 */
! 1064: /* 1 CCS */
! 1065: /* 2 SCSI-2 */
! 1066: /* 3-F reserved */
! 1067: u_int8_t res1 : 2; /* reserved */
! 1068: u_int8_t TemIOP : 1; /* terminate I/O process bit (see 5.6.22) */
! 1069: u_int8_t aenc : 1; /* asynch. event notification (processor) */
! 1070: u_int8_t add_len; /* additional length */
! 1071: u_int8_t res2 : 7; /* reserved */
! 1072: u_int8_t SCC : 1;
! 1073: u_int8_t Addr16 : 1;
! 1074: u_int8_t res3 : 2; /* reserved */
! 1075: u_int8_t MChngr : 1;
! 1076: u_int8_t MultiPort: 1;
! 1077: u_int8_t res4 : 1;
! 1078: u_int8_t EncServ : 1;
! 1079: u_int8_t BaseQue : 1;
! 1080: u_int8_t StfRe : 1; /* soft reset implemented */
! 1081: u_int8_t CmdQue : 1; /* command queuing */
! 1082: u_int8_t res5 : 1; /* reserved */
! 1083: u_int8_t Linked : 1; /* linked command for this logical unit */
! 1084: u_int8_t Sync : 1; /* synchronous data transfer */
! 1085: u_int8_t WBus16 : 1; /* wide bus 16 bit data transfer */
! 1086: u_int8_t WBus32 : 1; /* wide bus 32 bit data transfer */
! 1087: u_int8_t RelAdr : 1; /* relative addressing mode */
! 1088: u_int8_t vendor_id[8]; /* vendor identification */
! 1089: u_int8_t product_id[16]; /* product identification */
! 1090: u_int8_t product_rev_level[4]; /* product revision level */
! 1091: u_int8_t vendor_specific[20]; /* vendor specific */
! 1092: u_int8_t IUS : 1; /* information unit supported */
! 1093: u_int8_t QAS : 1; /* quick arbitrate supported */
! 1094: u_int8_t Clocking : 2; /* clocking field */
! 1095: u_int8_t res6 : 4; /* reserved */
! 1096: u_int8_t res7; /* reserved */
! 1097: u_int8_t version_descriptor[8][2];
! 1098: } ADW_SCSI_INQUIRY; /* 74 bytes */
! 1099:
! 1100: /*
! 1101: * Adw Library functions available to drivers.
! 1102: */
! 1103:
! 1104: int AdwInitFromEEPROM(ADW_SOFTC *);
! 1105: int AdwInitDriver(ADW_SOFTC *);
! 1106: int AdwExeScsiQueue(ADW_SOFTC *, ADW_SCSI_REQ_Q *);
! 1107: int AdwISR(ADW_SOFTC *);
! 1108: void AdwResetChip(bus_space_tag_t, bus_space_handle_t);
! 1109: int AdwSendIdleCmd(ADW_SOFTC *, u_int16_t, u_int32_t);
! 1110: int AdwResetSCSIBus(ADW_SOFTC *);
! 1111: int AdwResetCCB(ADW_SOFTC *);
! 1112:
! 1113: #endif /* _ADVANSYS_WIDE_LIBRARY_H_ */
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