Annotation of sys/dev/ic/advlib.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: advlib.h,v 1.8 2003/10/09 22:13:05 miod Exp $ */
2: /* $NetBSD: advlib.h,v 1.5 1998/10/28 20:39:46 dante Exp $ */
3:
4: /*
5: * Definitions for low level routines and data structures
6: * for the Advanced Systems Inc. SCSI controllers chips.
7: *
8: * Copyright (c) 1998 The NetBSD Foundation, Inc.
9: * All rights reserved.
10: *
11: * Author: Baldassare Dante Profeta <dante@mclink.it>
12: *
13: * Redistribution and use in source and binary forms, with or without
14: * modification, are permitted provided that the following conditions
15: * are met:
16: * 1. Redistributions of source code must retain the above copyright
17: * notice, this list of conditions and the following disclaimer.
18: * 2. Redistributions in binary form must reproduce the above copyright
19: * notice, this list of conditions and the following disclaimer in the
20: * documentation and/or other materials provided with the distribution.
21: * 3. All advertising materials mentioning features or use of this software
22: * must display the following acknowledgement:
23: * This product includes software developed by the NetBSD
24: * Foundation, Inc. and its contributors.
25: * 4. Neither the name of The NetBSD Foundation nor the names of its
26: * contributors may be used to endorse or promote products derived
27: * from this software without specific prior written permission.
28: *
29: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
30: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
31: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
32: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
33: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
34: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
37: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
39: * POSSIBILITY OF SUCH DAMAGE.
40: */
41: /*
42: * Ported from:
43: */
44: /*
45: * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
46: *
47: * Copyright (c) 1995-1996 Advanced System Products, Inc.
48: * All Rights Reserved.
49: *
50: * Redistribution and use in source and binary forms, with or without
51: * modification, are permitted provided that redistributions of source
52: * code retain the above copyright notice and this comment without
53: * modification.
54: */
55:
56: #ifndef _ADVANSYS_NARROW_LIBRARY_H_
57: #define _ADVANSYS_NARROW_LIBRARY_H_
58:
59: #include <dev/ic/adv.h>
60:
61: /******************************************************************************/
62:
63: #define ADV_VERSION "3.1E" /* AdvanSys Driver Version */
64:
65: #define ASC_LIB_VERSION_MAJOR 1
66: #define ASC_LIB_VERSION_MINOR 22
67: #define ASC_LIB_SERIAL_NUMBER 113
68:
69:
70: #define ASC_NOERROR 1
71: #define ASC_BUSY 0
72: #define ASC_ERROR -1
73:
74:
75: #if BYTE_ORDER == BIG_ENDIAN
76: #define LO_BYTE(x) (*((u_int8_t *)(&(x))+1))
77: #define HI_BYTE(x) (*((u_int8_t *)&(x)))
78: #define LO_WORD(x) (*((u_int16_t *)(&(x))+1))
79: #define HI_WORD(x) (*((u_int16_t *)&(x)))
80: #else
81: #define HI_BYTE(x) (*((u_int8_t *)(&(x))+1))
82: #define LO_BYTE(x) (*((u_int8_t *)&(x)))
83: #define HI_WORD(x) (*((u_int16_t *)(&(x))+1))
84: #define LO_WORD(x) (*((u_int16_t *)&(x)))
85: #endif
86:
87: #define MAKEWORD(lo, hi) ((u_int16_t) (((u_int16_t) (lo)) | \
88: ((u_int16_t) (hi) << 8)))
89:
90: #define MAKELONG(lo, hi) ((u_int32_t) (((u_int32_t) (lo)) | \
91: ((u_int32_t) (hi) << 16)))
92:
93: #define SWAPWORDS(dWord) ((u_int32_t) ((dWord) >> 16) | ((dWord) << 16))
94: #define SWAPBYTES(word) ((u_int16_t) ((word) >> 8) | ((word) << 8))
95: #define BIGTOLITTLE(dWord) (u_int32_t)(SWAPBYTES(SWAPWORDS(dWord) >> 16 ) << 16) | \
96: SWAPBYTES(SWAPWORDS(dWord) & 0xFFFF)
97: #define LITTLETOBIG(dWord) BIGTOLITTLE(dWord)
98:
99:
100: #define ASC_PCI_ID2BUS(id) ((id) & 0xFF)
101: #define ASC_PCI_ID2DEV(id) (((id) >> 11) & 0x1F)
102: #define ASC_PCI_ID2FUNC(id) (((id) >> 8) & 0x7)
103: #define ASC_PCI_MKID(bus, dev, func) ((((dev) & 0x1F) << 11) | \
104: (((func) & 0x7) << 8) | ((bus) & 0xFF))
105: #define ASC_PCI_REVISION_3150 0x02
106: #define ASC_PCI_REVISION_3050 0x03
107:
108:
109: #define ASC_MAX_SG_QUEUE 7
110: #define ASC_SG_LIST_PER_Q ASC_MAX_SG_QUEUE
111: #define ASC_MAX_SG_LIST (1 + ((ASC_SG_LIST_PER_Q) * \
112: (ASC_MAX_SG_QUEUE))) /* SG_ALL */
113:
114:
115: #define ASC_IS_ISA 0x0001
116: #define ASC_IS_ISAPNP 0x0081
117: #define ASC_IS_EISA 0x0002
118: #define ASC_IS_PCI 0x0004
119: #define ASC_IS_PCI_ULTRA 0x0104
120: #define ASC_IS_PCMCIA 0x0008
121: #define ASC_IS_MCA 0x0020
122: #define ASC_IS_VL 0x0040
123:
124:
125: #define ASC_ISA_PNP_PORT_ADDR 0x279
126: #define ASC_ISA_PNP_PORT_WRITE (ASC_ISA_PNP_PORT_ADDR+0x800)
127:
128: #define ASC_IS_WIDESCSI_16 0x0100
129: #define ASC_IS_WIDESCSI_32 0x0200
130: #define ASC_IS_BIG_ENDIAN 0x8000
131:
132:
133: #define ASC_CHIP_MIN_VER_VL 0x01
134: #define ASC_CHIP_MAX_VER_VL 0x07
135: #define ASC_CHIP_MIN_VER_PCI 0x09
136: #define ASC_CHIP_MAX_VER_PCI 0x0F
137: #define ASC_CHIP_VER_PCI_BIT 0x08
138: #define ASC_CHIP_MIN_VER_ISA 0x11
139: #define ASC_CHIP_MIN_VER_ISA_PNP 0x21
140: #define ASC_CHIP_MAX_VER_ISA 0x27
141: #define ASC_CHIP_VER_ISA_BIT 0x30
142: #define ASC_CHIP_VER_ISAPNP_BIT 0x20
143: #define ASC_CHIP_VER_ASYN_BUG 0x21
144: #define ASC_CHIP_VER_PCI 0x08
145: #define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02)
146: #define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03)
147: #define ASC_CHIP_MIN_VER_EISA 0x41
148: #define ASC_CHIP_MAX_VER_EISA 0x47
149: #define ASC_CHIP_VER_EISA_BIT 0x40
150: #define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
151:
152:
153: #define ASC_MAX_VL_DMA_ADDR 0x07FFFFFFL
154: #define ASC_MAX_VL_DMA_COUNT 0x07FFFFFFL
155: #define ASC_MAX_PCI_DMA_ADDR 0xFFFFFFFFL
156: #define ASC_MAX_PCI_DMA_COUNT 0xFFFFFFFFL
157: #define ASC_MAX_ISA_DMA_ADDR 0x00FFFFFFL
158: #define ASC_MAX_ISA_DMA_COUNT 0x00FFFFFFL
159: #define ASC_MAX_EISA_DMA_ADDR 0x07FFFFFFL
160: #define ASC_MAX_EISA_DMA_COUNT 0x07FFFFFFL
161:
162:
163: #define ASC_SCSI_ID_BITS 3
164: #define ASC_SCSI_TIX_TYPE u_int8_t
165:
166: #define ASC_ALL_DEVICE_BIT_SET 0xFF
167:
168: #ifdef ASC_WIDESCSI_16
169: #undef ASC_SCSI_ID_BITS
170: #define ASC_SCSI_ID_BITS 4
171: #define ASC_ALL_DEVICE_BIT_SET 0xFFFF
172: #endif
173:
174: #ifdef ASC_WIDESCSI_32
175: #undef ASC_SCSI_ID_BITS
176: #define ASC_SCSI_ID_BITS 5
177: #define ASC_ALL_DEVICE_BIT_SET 0xFFFFFFFFL
178: #endif
179:
180: #if ASC_SCSI_ID_BITS == 3
181: #define ASC_SCSI_BIT_ID_TYPE u_int8_t
182: #define ASC_MAX_TID 7
183: #define ASC_MAX_LUN 7
184: #define ASC_SCSI_WIDTH_BIT_SET 0xFF
185: #elif ASC_SCSI_ID_BITS == 4
186: #define ASC_SCSI_BIT_ID_TYPE u_int16_t
187: #define ASC_MAX_TID 15
188: #define ASC_MAX_LUN 7
189: #define ASC_SCSI_WIDTH_BIT_SET 0xFFFF
190: #elif ASC_SCSI_ID_BITS == 5
191: #define ASC_SCSI_BIT_ID_TYPE u_int32_t
192: #define ASC_MAX_TID 31
193: #define ASC_MAX_LUN 7
194: #define ASC_SCSI_WIDTH_BIT_SET 0xFFFFFFFF
195: #else
196: #error ASC_SCSI_ID_BITS definition is wrong
197: #endif
198:
199:
200: #define ASC_MAX_SENSE_LEN 32
201: #define ASC_MIN_SENSE_LEN 14
202: #define ASC_MAX_CDB_LEN 12
203:
204: #define ASC_SCSI_RESET_HOLD_TIME_US 60
205:
206:
207: #define SCSICMD_TestUnitReady 0x00
208: #define SCSICMD_Rewind 0x01
209: #define SCSICMD_Rezero 0x01
210: #define SCSICMD_RequestSense 0x03
211: #define SCSICMD_Format 0x04
212: #define SCSICMD_FormatUnit 0x04
213: #define SCSICMD_Read6 0x08
214: #define SCSICMD_Write6 0x0A
215: #define SCSICMD_Seek6 0x0B
216: #define SCSICMD_Inquiry 0x12
217: #define SCSICMD_Verify6 0x13
218: #define SCSICMD_ModeSelect6 0x15
219: #define SCSICMD_ModeSense6 0x1A
220: #define SCSICMD_StartStopUnit 0x1B
221: #define SCSICMD_LoadUnloadTape 0x1B
222: #define SCSICMD_ReadCapacity 0x25
223: #define SCSICMD_Read10 0x28
224: #define SCSICMD_Write10 0x2A
225: #define SCSICMD_Seek10 0x2B
226: #define SCSICMD_Erase10 0x2C
227: #define SCSICMD_WriteAndVerify10 0x2E
228: #define SCSICMD_Verify10 0x2F
229: #define SCSICMD_WriteBuffer 0x3B
230: #define SCSICMD_ReadBuffer 0x3C
231: #define SCSICMD_ReadLong 0x3E
232: #define SCSICMD_WriteLong 0x3F
233: #define SCSICMD_ReadTOC 0x43
234: #define SCSICMD_ReadHeader 0x44
235: #define SCSICMD_ModeSelect10 0x55
236: #define SCSICMD_ModeSense10 0x5A
237:
238:
239: #define SCSI_TYPE_DASD 0x00
240: #define SCSI_TYPE_SASD 0x01
241: #define SCSI_TYPE_PRN 0x02
242: #define SCSI_TYPE_PROC 0x03
243: #define SCSI_TYPE_WORM 0x04
244: #define SCSI_TYPE_CDROM 0x05
245: #define SCSI_TYPE_SCANNER 0x06
246: #define SCSI_TYPE_OPTMEM 0x07
247: #define SCSI_TYPE_MED_CHG 0x08
248: #define SCSI_TYPE_COMM 0x09
249: #define SCSI_TYPE_UNKNOWN 0x1F
250: #define SCSI_TYPE_NO_DVC 0xFF
251:
252:
253: #define ASC_SCSIDIR_NOCHK 0x00
254: #define ASC_SCSIDIR_T2H 0x08
255: #define ASC_SCSIDIR_H2T 0x10
256: #define ASC_SCSIDIR_NODATA 0x18
257:
258:
259: #define SCSI_SENKEY_NO_SENSE 0x00
260: #define SCSI_SENKEY_UNDEFINED 0x01
261: #define SCSI_SENKEY_NOT_READY 0x02
262: #define SCSI_SENKEY_MEDIUM_ERR 0x03
263: #define SCSI_SENKEY_HW_ERR 0x04
264: #define SCSI_SENKEY_ILLEGAL 0x05
265: #define SCSI_SENKEY_ATTENTION 0x06
266: #define SCSI_SENKEY_PROTECTED 0x07
267: #define SCSI_SENKEY_BLANK 0x08
268: #define SCSI_SENKEY_V_UNIQUE 0x09
269: #define SCSI_SENKEY_CPY_ABORT 0x0A
270: #define SCSI_SENKEY_ABORT 0x0B
271: #define SCSI_SENKEY_EQUAL 0x0C
272: #define SCSI_SENKEY_VOL_OVERFLOW 0x0D
273: #define SCSI_SENKEY_MISCOMP 0x0E
274: #define SCSI_SENKEY_RESERVED 0x0F
275: #define SCSI_ASC_NOMEDIA 0x3A
276:
277:
278: #define ASC_CCB_HOST(x) ((u_int8_t)((u_int8_t)(x) >> 4))
279: #define ASC_CCB_TID(x) ((u_int8_t)((u_int8_t)(x) & (u_int8_t)0x0F))
280: #define ASC_CCB_LUN(x) ((u_int8_t)((uint)(x) >> 13))
281:
282:
283: #define SS_GOOD 0x00
284: #define SS_CHK_CONDITION 0x02
285: #define SS_CONDITION_MET 0x04
286: #define SS_TARGET_BUSY 0x08
287: #define SS_INTERMID 0x10
288: #define SS_INTERMID_COND_MET 0x14
289: #define SS_RSERV_CONFLICT 0x18
290: #define SS_CMD_TERMINATED 0x22
291: #define SS_QUEUE_FULL 0x28
292:
293:
294: #define MS_CMD_DONE 0x00
295: #define MS_EXTEND 0x01
296: #define MS_SDTR_LEN 0x03
297: #define MS_SDTR_CODE 0x01
298: #define MS_WDTR_LEN 0x02
299: #define MS_WDTR_CODE 0x03
300: #define MS_MDP_LEN 0x05
301: #define MS_MDP_CODE 0x00
302:
303:
304: #define M1_SAVE_DATA_PTR 0x02
305: #define M1_RESTORE_PTRS 0x03
306: #define M1_DISCONNECT 0x04
307: #define M1_INIT_DETECTED_ERR 0x05
308: #define M1_ABORT 0x06
309: #define M1_MSG_REJECT 0x07
310: #define M1_NO_OP 0x08
311: #define M1_MSG_PARITY_ERR 0x09
312: #define M1_LINK_CMD_DONE 0x0A
313: #define M1_LINK_CMD_DONE_WFLAG 0x0B
314: #define M1_BUS_DVC_RESET 0x0C
315: #define M1_ABORT_TAG 0x0D
316: #define M1_CLR_QUEUE 0x0E
317: #define M1_INIT_RECOVERY 0x0F
318: #define M1_RELEASE_RECOVERY 0x10
319: #define M1_KILL_IO_PROC 0x11
320: #define M2_QTAG_MSG_SIMPLE 0x20
321: #define M2_QTAG_MSG_HEAD 0x21
322: #define M2_QTAG_MSG_ORDERED 0x22
323: #define M2_IGNORE_WIDE_RESIDUE 0x23
324:
325:
326: /*
327: * SCSI Inquiry structure
328: */
329:
330: typedef struct
331: {
332: u_int8_t peri_dvc_type:5;
333: u_int8_t peri_qualifier:3;
334: } ASC_SCSI_INQ0;
335:
336: typedef struct
337: {
338: u_int8_t dvc_type_modifier:7;
339: u_int8_t rmb:1;
340: } ASC_SCSI_INQ1;
341:
342: typedef struct
343: {
344: u_int8_t ansi_apr_ver:3;
345: u_int8_t ecma_ver:3;
346: u_int8_t iso_ver:2;
347: } ASC_SCSI_INQ2;
348:
349: typedef struct
350: {
351: u_int8_t rsp_data_fmt:4;
352: u_int8_t res:2;
353: u_int8_t TemIOP:1;
354: u_int8_t aenc:1;
355: } ASC_SCSI_INQ3;
356:
357: typedef struct
358: {
359: u_int8_t StfRe:1;
360: u_int8_t CmdQue:1;
361: u_int8_t Reserved:1;
362: u_int8_t Linked:1;
363: u_int8_t Sync:1;
364: u_int8_t WBus16:1;
365: u_int8_t WBus32:1;
366: u_int8_t RelAdr:1;
367: } ASC_SCSI_INQ7;
368:
369: typedef struct
370: {
371: ASC_SCSI_INQ0 byte0;
372: ASC_SCSI_INQ1 byte1;
373: ASC_SCSI_INQ2 byte2;
374: ASC_SCSI_INQ3 byte3;
375: u_int8_t add_len;
376: u_int8_t res1;
377: u_int8_t res2;
378: ASC_SCSI_INQ7 byte7;
379: u_int8_t vendor_id[8];
380: u_int8_t product_id[16];
381: u_int8_t product_rev_level[4];
382: } ASC_SCSI_INQUIRY;
383:
384:
385: /*
386: * SCSIQ Microcode offsets
387: */
388: #define ASC_SCSIQ_CPY_BEG 4
389: #define ASC_SCSIQ_SGHD_CPY_BEG 2
390: #define ASC_SCSIQ_B_FWD 0
391: #define ASC_SCSIQ_B_BWD 1
392: #define ASC_SCSIQ_B_STATUS 2
393: #define ASC_SCSIQ_B_QNO 3
394: #define ASC_SCSIQ_B_CNTL 4
395: #define ASC_SCSIQ_B_SG_QUEUE_CNT 5
396: #define ASC_SCSIQ_D_DATA_ADDR 8
397: #define ASC_SCSIQ_D_DATA_CNT 12
398: #define ASC_SCSIQ_B_SENSE_LEN 20
399: #define ASC_SCSIQ_DONE_INFO_BEG 22
400: #define ASC_SCSIQ_D_CCBPTR 22
401: #define ASC_SCSIQ_B_TARGET_IX 26
402: #define ASC_SCSIQ_B_CDB_LEN 28
403: #define ASC_SCSIQ_B_TAG_CODE 29
404: #define ASC_SCSIQ_W_VM_ID 30
405: #define ASC_SCSIQ_DONE_STATUS 32
406: #define ASC_SCSIQ_HOST_STATUS 33
407: #define ASC_SCSIQ_SCSI_STATUS 34
408: #define ASC_SCSIQ_CDB_BEG 36
409: #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
410: #define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60
411: #define ASC_SCSIQ_B_SG_WK_QP 49
412: #define ASC_SCSIQ_B_SG_WK_IX 50
413: #define ASC_SCSIQ_W_REQ_COUNT 52
414: #define ASC_SCSIQ_B_LIST_CNT 6
415: #define ASC_SCSIQ_B_CUR_LIST_CNT 7
416:
417:
418: #define ASC_DEF_SCSI1_QNG 4
419: #define ASC_MAX_SCSI1_QNG 4
420: #define ASC_DEF_SCSI2_QNG 16
421: #define ASC_MAX_SCSI2_QNG 32
422:
423: #define ASC_TAG_CODE_MASK 0x23
424:
425: #define ASC_STOP_REQ_RISC_STOP 0x01
426: #define ASC_STOP_ACK_RISC_STOP 0x03
427: #define ASC_STOP_CLEAN_UP_BUSY_Q 0x10
428: #define ASC_STOP_CLEAN_UP_DISC_Q 0x20
429: #define ASC_STOP_HOST_REQ_RISC_HALT 0x40
430:
431: #define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
432: #define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
433: #define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID))
434: #define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID)
435: #define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID)
436: #define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
437: #define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6))
438:
439:
440: /*
441: * Structures used to dialog with the RISC engine
442: */
443:
444: typedef struct asc_scisq_1
445: {
446: u_int8_t status; /* see below status values */
447: u_int8_t q_no; /* Queue ID of the first queue for this transaction */
448: u_int8_t cntl; /* see below cntl values */
449: u_int8_t sg_queue_cnt; /* number of SG entries */
450: u_int8_t target_id;
451: u_int8_t target_lun;
452: u_int32_t data_addr; /* physical address of first segment to transfer */
453: u_int32_t data_cnt; /* byte count of first segment to transfer */
454: u_int32_t sense_addr; /* physical address of the sense buffer */
455: u_int8_t sense_len; /* length of sense buffer */
456: u_int8_t extra_bytes;
457: } ASC_SCSIQ_1;
458:
459: /* status values */
460: #define ASC_QS_FREE 0x00
461: #define ASC_QS_READY 0x01
462: #define ASC_QS_DISC1 0x02
463: #define ASC_QS_DISC2 0x04
464: #define ASC_QS_BUSY 0x08
465: #define ASC_QS_ABORTED 0x40
466: #define ASC_QS_DONE 0x80
467:
468: /* cntl values */
469: #define ASC_QC_NO_CALLBACK 0x01
470: #define ASC_QC_SG_SWAP_QUEUE 0x02
471: #define ASC_QC_SG_HEAD 0x04
472: #define ASC_QC_DATA_IN 0x08
473: #define ASC_QC_DATA_OUT 0x10
474: #define ASC_QC_URGENT 0x20
475: #define ASC_QC_MSG_OUT 0x40
476: #define ASC_QC_REQ_SENSE 0x80
477:
478:
479: typedef struct asc_scisq_2
480: {
481: u_int32_t ccb_ptr; /* pointer to our CCB */
482: u_int8_t target_ix; /* combined TID and LUN */
483: u_int8_t flag;
484: u_int8_t cdb_len; /* bytes of Command Descriptor Block */
485: u_int8_t tag_code; /* type of this transaction. see below */
486: u_int16_t vm_id;
487: } ASC_SCSIQ_2;
488:
489: /* tag_code values */
490: #define ASC_TAG_FLAG_EXTRA_BYTES 0x10
491: #define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04
492: #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08
493: #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
494:
495:
496: typedef struct asc_scsiq_3
497: {
498: u_int8_t done_stat; /* see below done_stat values */
499: u_int8_t host_stat; /* see below host_stat values */
500: u_int8_t scsi_stat;
501: u_int8_t scsi_msg;
502: } ASC_SCSIQ_3;
503:
504: /* done_stat values */
505: #define ASC_QD_IN_PROGRESS 0x00
506: #define ASC_QD_NO_ERROR 0x01
507: #define ASC_QD_ABORTED_BY_HOST 0x02
508: #define ASC_QD_WITH_ERROR 0x04
509: #define ASC_QD_INVALID_REQUEST 0x80
510: #define ASC_QD_INVALID_HOST_NUM 0x81
511: #define ASC_QD_INVALID_DEVICE 0x82
512: #define ASC_QD_ERR_INTERNAL 0xFF
513:
514: /* host_stat values */
515: #define ASC_QHSTA_NO_ERROR 0x00
516: #define ASC_QHSTA_M_SEL_TIMEOUT 0x11
517: #define ASC_QHSTA_M_DATA_OVER_RUN 0x12
518: #define ASC_QHSTA_M_DATA_UNDER_RUN 0x12
519: #define ASC_QHSTA_M_UNEXPECTED_BUS_FREE 0x13
520: #define ASC_QHSTA_M_BAD_BUS_PHASE_SEQ 0x14
521: #define ASC_QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
522: #define ASC_QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22
523: #define ASC_QHSTA_D_HOST_ABORT_FAILED 0x23
524: #define ASC_QHSTA_D_EXE_SCSI_Q_FAILED 0x24
525: #define ASC_QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
526: #define ASC_QHSTA_D_ASPI_NO_BUF_POOL 0x26
527: #define ASC_QHSTA_M_WTM_TIMEOUT 0x41
528: #define ASC_QHSTA_M_BAD_CMPL_STATUS_IN 0x42
529: #define ASC_QHSTA_M_NO_AUTO_REQ_SENSE 0x43
530: #define ASC_QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
531: #define ASC_QHSTA_M_TARGET_STATUS_BUSY 0x45
532: #define ASC_QHSTA_M_BAD_TAG_CODE 0x46
533: #define ASC_QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47
534: #define ASC_QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
535: #define ASC_QHSTA_D_LRAM_CMP_ERROR 0x81
536: #define ASC_QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
537:
538:
539: typedef struct asc_scsiq_4
540: {
541: u_int8_t cdb[ASC_MAX_CDB_LEN];
542: u_int8_t y_first_sg_list_qp;
543: u_int8_t y_working_sg_qp;
544: u_int8_t y_working_sg_ix;
545: u_int8_t y_res;
546: u_int16_t x_req_count;
547: u_int16_t x_reconnect_rtn;
548: u_int32_t x_saved_data_addr;
549: u_int32_t x_saved_data_cnt;
550: } ASC_SCSIQ_4;
551:
552: typedef struct asc_q_done_info
553: {
554: ASC_SCSIQ_2 d2;
555: ASC_SCSIQ_3 d3;
556: u_int8_t q_status;
557: u_int8_t q_no;
558: u_int8_t cntl;
559: u_int8_t sense_len;
560: u_int8_t extra_bytes;
561: u_int8_t res;
562: u_int32_t remain_bytes;
563: } ASC_QDONE_INFO;
564:
565: typedef struct asc_sg_list
566: {
567: u_int32_t addr;
568: u_int32_t bytes;
569: } ASC_SG_LIST;
570:
571: typedef struct asc_sg_head
572: {
573: u_int16_t entry_cnt; /* number of SG entries */
574: u_int16_t queue_cnt; /* number of queues required to store SG entries */
575: u_int16_t entry_to_copy; /* number of SG entries to copy to the board */
576: u_int16_t res;
577: ASC_SG_LIST sg_list[ASC_MAX_SG_LIST];
578: } ASC_SG_HEAD;
579:
580: #define ASC_MIN_SG_LIST 2
581:
582: typedef struct asc_min_sg_head
583: {
584: u_int16_t entry_cnt;
585: u_int16_t queue_cnt;
586: u_int16_t entry_to_copy;
587: u_int16_t res;
588: ASC_SG_LIST sg_list[ASC_MIN_SG_LIST];
589: } ASC_MIN_SG_HEAD;
590:
591: #define ASC_QCX_SORT 0x0001
592: #define ASC_QCX_COALEASE 0x0002
593:
594: typedef struct asc_scsi_q
595: {
596: ASC_SCSIQ_1 q1;
597: ASC_SCSIQ_2 q2;
598: u_int8_t *cdbptr; /* pointer to CDB to execute */
599: ASC_SG_HEAD *sg_head; /* pointer to SG list */
600: } ASC_SCSI_Q;
601:
602: typedef struct asc_scsi_req_q
603: {
604: ASC_SCSIQ_1 q1;
605: ASC_SCSIQ_2 q2;
606: u_int8_t *cdbptr;
607: ASC_SG_HEAD *sg_head;
608: u_int8_t *sense_ptr;
609: ASC_SCSIQ_3 q3;
610: u_int8_t cdb[ASC_MAX_CDB_LEN];
611: u_int8_t sense[ASC_MIN_SENSE_LEN];
612: } ASC_SCSI_REQ_Q;
613:
614: typedef struct asc_scsi_bios_req_q
615: {
616: ASC_SCSIQ_1 q1;
617: ASC_SCSIQ_2 q2;
618: u_int8_t *cdbptr;
619: ASC_SG_HEAD *sg_head;
620: u_int8_t *sense_ptr;
621: ASC_SCSIQ_3 q3;
622: u_int8_t cdb[ASC_MAX_CDB_LEN];
623: u_int8_t sense[ASC_MIN_SENSE_LEN];
624: } ASC_SCSI_BIOS_REQ_Q;
625:
626: typedef struct asc_risc_q
627: {
628: u_int8_t fwd;
629: u_int8_t bwd;
630: ASC_SCSIQ_1 i1;
631: ASC_SCSIQ_2 i2;
632: ASC_SCSIQ_3 i3;
633: ASC_SCSIQ_4 i4;
634: } ASC_RISC_Q;
635:
636: typedef struct asc_sg_list_q
637: {
638: u_int8_t seq_no;
639: u_int8_t q_no;
640: u_int8_t cntl; /* see below cntl values */
641: u_int8_t sg_head_qp;
642: u_int8_t sg_list_cnt;
643: u_int8_t sg_cur_list_cnt;
644: } ASC_SG_LIST_Q;
645:
646: /* cntl values */
647: #define ASC_QCSG_SG_XFER_LIST 0x02
648: #define ASC_QCSG_SG_XFER_MORE 0x04
649: #define ASC_QCSG_SG_XFER_END 0x08
650:
651: #define ASC_SGQ_B_SG_CNTL 4
652: #define ASC_SGQ_B_SG_HEAD_QP 5
653: #define ASC_SGQ_B_SG_LIST_CNT 6
654: #define ASC_SGQ_B_SG_CUR_LIST_CNT 7
655: #define ASC_SGQ_LIST_BEG 8
656:
657:
658: typedef struct asc_risc_sg_list_q
659: {
660: u_int8_t fwd;
661: u_int8_t bwd;
662: ASC_SG_LIST_Q sg;
663: ASC_SG_LIST sg_list[7];
664: } ASC_RISC_SG_LIST_Q;
665:
666:
667: #define ASC_EXE_SCSI_IO_MAX_IDLE_LOOP 0x1000000UL
668: #define ASC_EXE_SCSI_IO_MAX_WAIT_LOOP 1024
669:
670: #define ASCQ_ERR_NO_ERROR 0x00
671: #define ASCQ_ERR_IO_NOT_FOUND 0x01
672: #define ASCQ_ERR_LOCAL_MEM 0x02
673: #define ASCQ_ERR_CHKSUM 0x03
674: #define ASCQ_ERR_START_CHIP 0x04
675: #define ASCQ_ERR_INT_TARGET_ID 0x05
676: #define ASCQ_ERR_INT_LOCAL_MEM 0x06
677: #define ASCQ_ERR_HALT_RISC 0x07
678: #define ASCQ_ERR_GET_ASPI_ENTRY 0x08
679: #define ASCQ_ERR_CLOSE_ASPI 0x09
680: #define ASCQ_ERR_HOST_INQUIRY 0x0A
681: #define ASCQ_ERR_SAVED_CCB_BAD 0x0B
682: #define ASCQ_ERR_QCNTL_SG_LIST 0x0C
683: #define ASCQ_ERR_Q_STATUS 0x0D
684: #define ASCQ_ERR_WR_SCSIQ 0x0E
685: #define ASCQ_ERR_PC_ADDR 0x0F
686: #define ASCQ_ERR_SYN_OFFSET 0x10
687: #define ASCQ_ERR_SYN_XFER_TIME 0x11
688: #define ASCQ_ERR_LOCK_DMA 0x12
689: #define ASCQ_ERR_UNLOCK_DMA 0x13
690: #define ASCQ_ERR_VDS_CHK_INSTALL 0x14
691: #define ASCQ_ERR_MICRO_CODE_HALT 0x15
692: #define ASCQ_ERR_SET_LRAM_ADDR 0x16
693: #define ASCQ_ERR_CUR_QNG 0x17
694: #define ASCQ_ERR_SG_Q_LINKS 0x18
695: #define ASCQ_ERR_SCSIQ_PTR 0x19
696: #define ASCQ_ERR_ISR_RE_ENTRY 0x1A
697: #define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B
698: #define ASCQ_ERR_ISR_ON_CRITICAL 0x1C
699: #define ASCQ_ERR_SG_LIST_ODD_ADDRESS 0x1D
700: #define ASCQ_ERR_XFER_ADDRESS_TOO_BIG 0x1E
701: #define ASCQ_ERR_SCSIQ_NULL_PTR 0x1F
702: #define ASCQ_ERR_SCSIQ_BAD_NEXT_PTR 0x20
703: #define ASCQ_ERR_GET_NUM_OF_FREE_Q 0x21
704: #define ASCQ_ERR_SEND_SCSI_Q 0x22
705: #define ASCQ_ERR_HOST_REQ_RISC_HALT 0x23
706: #define ASCQ_ERR_RESET_SDTR 0x24
707:
708: #define ASC_WARN_NO_ERROR 0x0000
709: #define ASC_WARN_IO_PORT_ROTATE 0x0001
710: #define ASC_WARN_EEPROM_CHKSUM 0x0002
711: #define ASC_WARN_IRQ_MODIFIED 0x0004
712: #define ASC_WARN_AUTO_CONFIG 0x0008
713: #define ASC_WARN_CMD_QNG_CONFLICT 0x0010
714: #define ASC_WARN_EEPROM_RECOVER 0x0020
715: #define ASC_WARN_CFG_MSW_RECOVER 0x0040
716: #define ASC_WARN_SET_PCI_CONFIG_SPACE 0x0080
717:
718: #define ASC_IERR_WRITE_EEPROM 0x0001
719: #define ASC_IERR_MCODE_CHKSUM 0x0002
720: #define ASC_IERR_SET_PC_ADDR 0x0004
721: #define ASC_IERR_START_STOP_CHIP 0x0008
722: #define ASC_IERR_IRQ_NO 0x0010
723: #define ASC_IERR_SET_IRQ_NO 0x0020
724: #define ASC_IERR_CHIP_VERSION 0x0040
725: #define ASC_IERR_SET_SCSI_ID 0x0080
726: #define ASC_IERR_GET_PHY_ADDR 0x0100
727: #define ASC_IERR_BAD_SIGNATURE 0x0200
728: #define ASC_IERR_NO_BUS_TYPE 0x0400
729: #define ASC_IERR_SCAM 0x0800
730: #define ASC_IERR_SET_SDTR 0x1000
731: #define ASC_IERR_RW_LRAM 0x8000
732:
733: #define ASC_DEF_IRQ_NO 10
734: #define ASC_MAX_IRQ_NO 15
735: #define ASC_MIN_IRQ_NO 10
736: #define ASC_MIN_REMAIN_Q 0x02
737: #define ASC_DEF_MAX_TOTAL_QNG 0xF0
738: #define ASC_MIN_TAG_Q_PER_DVC 0x04
739: #define ASC_DEF_TAG_Q_PER_DVC 0x04
740: #define ASC_MIN_FREE_Q ASC_MIN_REMAIN_Q
741: #define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
742: #define ASC_MAX_TOTAL_QNG 240
743: #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
744: #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
745: #define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
746: #define ASC_MAX_INRAM_TAG_QNG 16
747: #define ASC_IOADR_TABLE_MAX_IX 11
748: #define ASC_IOADR_GAP 0x10
749: #define ASC_SEARCH_IOP_GAP 0x10
750: #define ASC_MIN_IOP_ADDR 0x0100
751: #define ASC_MAX_IOP_ADDR 0x03F0
752:
753: #define ASC_IOADR_1 0x0110
754: #define ASC_IOADR_2 0x0130
755: #define ASC_IOADR_3 0x0150
756: #define ASC_IOADR_4 0x0190
757: #define ASC_IOADR_5 0x0210
758: #define ASC_IOADR_6 0x0230
759: #define ASC_IOADR_7 0x0250
760: #define ASC_IOADR_8 0x0330
761:
762: #define ASC_IOADR_DEF ASC_IOADR_8
763: #define ASC_LIB_SCSIQ_WK_SP 256
764: #define ASC_MAX_SYN_XFER_NO 16
765: #define ASC_SYN_MAX_OFFSET 0x0F
766: #define ASC_DEF_SDTR_OFFSET 0x0F
767: #define ASC_DEF_SDTR_INDEX 0x00
768: #define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
769:
770:
771: /*
772: * This structure is used to handle internal messages
773: * during interrupt handling routine
774: */
775: typedef struct ext_msg
776: {
777: u_int8_t msg_type;
778: u_int8_t msg_len;
779: u_int8_t msg_req;
780:
781: union
782: {
783: struct
784: {
785: u_int8_t sdtr_xfer_period;
786: u_int8_t sdtr_req_ack_offset;
787: } sdtr;
788:
789: struct
790: {
791: u_int8_t wdtr_width;
792: } wdtr;
793:
794: struct
795: {
796: u_int8_t mdp_b3;
797: u_int8_t mdp_b2;
798: u_int8_t mdp_b1;
799: u_int8_t mdp_b0;
800: } mdp;
801: } u_ext_msg;
802:
803: u_int8_t res;
804: } EXT_MSG;
805:
806: #define xfer_period u_ext_msg.sdtr.sdtr_xfer_period
807: #define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset
808: #define wdtr_width u_ext_msg.wdtr.wdtr_width
809: #define mdp_b3 u_ext_msg.mdp_b3
810: #define mdp_b2 u_ext_msg.mdp_b2
811: #define mdp_b1 u_ext_msg.mdp_b1
812: #define mdp_b0 u_ext_msg.mdp_b0
813:
814:
815: #define ASC_DEF_DVC_CNTL 0xFFFF
816: #define ASC_DEF_CHIP_SCSI_ID 7
817: #define ASC_DEF_ISA_DMA_SPEED 4
818:
819: #define ASC_PCI_DEVICE_ID_REV_A 0x1100
820: #define ASC_PCI_DEVICE_ID_REV_B 0x1200
821:
822: #define ASC_BUG_FIX_IF_NOT_DWB 0x0001
823: #define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
824:
825: #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
826:
827: #define ASC_MIN_TAGGED_CMD 7
828:
829: #define ASC_MAX_SCSI_RESET_WAIT 30
830:
831:
832: typedef struct asc_softc
833: {
834: struct device sc_dev;
835:
836: bus_space_tag_t sc_iot;
837: bus_space_handle_t sc_ioh;
838: bus_dma_tag_t sc_dmat;
839: bus_dmamap_t sc_dmamap_control; /* maps the control structures */
840: void *sc_ih;
841:
842: struct adv_control *sc_control; /* control structures */
843: TAILQ_HEAD(, adv_ccb) sc_free_ccb, sc_waiting_ccb;
844: struct scsi_link sc_link; /* prototype for devs */
845:
846: LIST_HEAD(, scsi_xfer) sc_queue;
847: struct scsi_xfer *sc_queuelast;
848:
849: u_int8_t *overrun_buf;
850:
851: u_int16_t sc_flags; /* see below sc_flags values */
852:
853: u_int16_t dvc_cntl;
854: u_int16_t bug_fix_cntl;
855: u_int16_t bus_type;
856:
857: ulong isr_callback;
858:
859: ASC_SCSI_BIT_ID_TYPE init_sdtr;
860: ASC_SCSI_BIT_ID_TYPE sdtr_done;
861: ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
862: ASC_SCSI_BIT_ID_TYPE unit_not_ready;
863: ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
864: ASC_SCSI_BIT_ID_TYPE start_motor;
865:
866: ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
867: ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
868: ASC_SCSI_BIT_ID_TYPE disc_enable;
869: ASC_SCSI_BIT_ID_TYPE sdtr_enable;
870: u_int8_t chip_scsi_id;
871: u_int8_t isa_dma_speed;
872: u_int8_t isa_dma_channel;
873: u_int8_t chip_version;
874: u_int16_t pci_device_id;
875: u_int16_t lib_serial_no;
876: u_int16_t lib_version;
877: u_int16_t mcode_date;
878: u_int16_t mcode_version;
879: u_int8_t max_tag_qng[ASC_MAX_TID + 1];
880: u_int8_t sdtr_period_offset[ASC_MAX_TID + 1];
881: u_int8_t adapter_info[6];
882:
883: u_int8_t scsi_reset_wait;
884: u_int8_t max_total_qng;
885: u_int8_t cur_total_qng;
886: u_int8_t irq_no;
887: u_int8_t last_q_shortage;
888:
889: u_int8_t cur_dvc_qng[ASC_MAX_TID + 1];
890: u_int8_t max_dvc_qng[ASC_MAX_TID + 1];
891: u_int8_t sdtr_period_tbl[ASC_MAX_SYN_XFER_NO];
892: u_int8_t sdtr_period_tbl_size; /* see below */
893: u_int8_t sdtr_data[ASC_MAX_TID+1];
894:
895: u_int16_t reqcnt[ASC_MAX_TID+1]; /* Starvation request count */
896:
897: u_int32_t max_dma_count;
898: ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
899: ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
900: u_int8_t max_sdtr_index;
901: u_int8_t host_init_sdtr_index;
902: } ASC_SOFTC;
903:
904: /* sc_flags values */
905: #define ASC_HOST_IN_RESET 0x01
906: #define ASC_HOST_IN_ABORT 0x02
907: #define ASC_WIDE_BOARD 0x04
908: #define ASC_SELECT_QUEUE_DEPTHS 0x08
909:
910: /* sdtr_period_tbl_size values */
911: #define SYN_XFER_NS_0 25
912: #define SYN_XFER_NS_1 30
913: #define SYN_XFER_NS_2 35
914: #define SYN_XFER_NS_3 40
915: #define SYN_XFER_NS_4 50
916: #define SYN_XFER_NS_5 60
917: #define SYN_XFER_NS_6 70
918: #define SYN_XFER_NS_7 85
919:
920: #define SYN_ULTRA_XFER_NS_0 12
921: #define SYN_ULTRA_XFER_NS_1 19
922: #define SYN_ULTRA_XFER_NS_2 25
923: #define SYN_ULTRA_XFER_NS_3 32
924: #define SYN_ULTRA_XFER_NS_4 38
925: #define SYN_ULTRA_XFER_NS_5 44
926: #define SYN_ULTRA_XFER_NS_6 50
927: #define SYN_ULTRA_XFER_NS_7 57
928: #define SYN_ULTRA_XFER_NS_8 63
929: #define SYN_ULTRA_XFER_NS_9 69
930: #define SYN_ULTRA_XFER_NS_10 75
931: #define SYN_ULTRA_XFER_NS_11 82
932: #define SYN_ULTRA_XFER_NS_12 88
933: #define SYN_ULTRA_XFER_NS_13 94
934: #define SYN_ULTRA_XFER_NS_14 100
935: #define SYN_ULTRA_XFER_NS_15 107
936:
937:
938: /* second level interrupt callback type definition */
939: typedef int (* ASC_ISR_CALLBACK) (ASC_SOFTC *, ASC_QDONE_INFO *);
940:
941:
942: #define ASC_MCNTL_NO_SEL_TIMEOUT 0x0001
943: #define ASC_MCNTL_NULL_TARGET 0x0002
944:
945: #define ASC_CNTL_INITIATOR 0x0001
946: #define ASC_CNTL_BIOS_GT_1GB 0x0002
947: #define ASC_CNTL_BIOS_GT_2_DISK 0x0004
948: #define ASC_CNTL_BIOS_REMOVABLE 0x0008
949: #define ASC_CNTL_NO_SCAM 0x0010
950: #define ASC_CNTL_INT_MULTI_Q 0x0080
951: #define ASC_CNTL_NO_LUN_SUPPORT 0x0040
952: #define ASC_CNTL_NO_VERIFY_COPY 0x0100
953: #define ASC_CNTL_RESET_SCSI 0x0200
954: #define ASC_CNTL_INIT_INQUIRY 0x0400
955: #define ASC_CNTL_INIT_VERBOSE 0x0800
956: #define ASC_CNTL_SCSI_PARITY 0x1000
957: #define ASC_CNTL_BURST_MODE 0x2000
958: #define ASC_CNTL_SDTR_ENABLE_ULTRA 0x4000
959:
960: #define ASC_EEP_DVC_CFG_BEG_VL 2
961: #define ASC_EEP_MAX_DVC_ADDR_VL 15
962: #define ASC_EEP_DVC_CFG_BEG 32
963: #define ASC_EEP_MAX_DVC_ADDR 45
964: #define ASC_EEP_DEFINED_WORDS 10
965: #define ASC_EEP_MAX_ADDR 63
966: #define ASC_EEP_RES_WORDS 0
967: #define ASC_EEP_MAX_RETRY 20
968: #define ASC_MAX_INIT_BUSY_RETRY 8
969: #define ASC_EEP_ISA_PNP_WSIZE 16
970:
971:
972: /*
973: * This structure is used to read/write EEProm configuration
974: */
975: typedef struct asceep_config
976: {
977: u_int16_t cfg_lsw;
978: u_int16_t cfg_msw;
979: #if BYTE_ORDER == BIG_ENDIAN
980: u_int8_t disc_enable;
981: u_int8_t init_sdtr;
982: u_int8_t start_motor;
983: u_int8_t use_cmd_qng;
984: u_int8_t max_tag_qng;
985: u_int8_t max_total_qng;
986: u_int8_t power_up_wait;
987: u_int8_t bios_scan;
988: u_int8_t isa_dma_speed:4;
989: u_int8_t chip_scsi_id:4;
990: u_int8_t no_scam;
991: #else
992: u_int8_t init_sdtr;
993: u_int8_t disc_enable;
994: u_int8_t use_cmd_qng;
995: u_int8_t start_motor;
996: u_int8_t max_total_qng;
997: u_int8_t max_tag_qng;
998: u_int8_t bios_scan;
999: u_int8_t power_up_wait;
1000: u_int8_t no_scam;
1001: u_int8_t chip_scsi_id:4;
1002: u_int8_t isa_dma_speed:4;
1003: #endif
1004: u_int8_t dos_int13_table[ASC_MAX_TID + 1];
1005: u_int8_t adapter_info[6];
1006: u_int16_t cntl;
1007: u_int16_t chksum;
1008: } ASCEEP_CONFIG;
1009:
1010: #define ASC_PCI_CFG_LSW_SCSI_PARITY 0x0800
1011: #define ASC_PCI_CFG_LSW_BURST_MODE 0x0080
1012: #define ASC_PCI_CFG_LSW_INTR_ABLE 0x0020
1013:
1014: #define ASC_EEP_CMD_READ 0x80
1015: #define ASC_EEP_CMD_WRITE 0x40
1016: #define ASC_EEP_CMD_WRITE_ABLE 0x30
1017: #define ASC_EEP_CMD_WRITE_DISABLE 0x00
1018:
1019: #define ASC_OVERRUN_BSIZE 0x00000048UL
1020:
1021: #define ASC_CTRL_BREAK_ONCE 0x0001
1022: #define ASC_CTRL_BREAK_STAY_IDLE 0x0002
1023:
1024: #define ASCV_MSGOUT_BEG 0x0000
1025: #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
1026: #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
1027: #define ASCV_BREAK_SAVED_CODE 0x0006
1028: #define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8)
1029: #define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3)
1030: #define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4)
1031: #define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8)
1032: #define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8)
1033: #define ASCV_MAX_DVC_QNG_BEG 0x0020
1034: #define ASCV_BREAK_ADDR 0x0028
1035: #define ASCV_BREAK_NOTIFY_COUNT 0x002A
1036: #define ASCV_BREAK_CONTROL 0x002C
1037: #define ASCV_BREAK_HIT_COUNT 0x002E
1038:
1039: #define ASCV_ASCDVC_ERR_CODE_W 0x0030
1040: #define ASCV_MCODE_CHKSUM_W 0x0032
1041: #define ASCV_MCODE_SIZE_W 0x0034
1042: #define ASCV_STOP_CODE_B 0x0036
1043: #define ASCV_DVC_ERR_CODE_B 0x0037
1044: #define ASCV_OVERRUN_PADDR_D 0x0038
1045: #define ASCV_OVERRUN_BSIZE_D 0x003C
1046: #define ASCV_HALTCODE_W 0x0040
1047: #define ASCV_CHKSUM_W 0x0042
1048: #define ASCV_MC_DATE_W 0x0044
1049: #define ASCV_MC_VER_W 0x0046
1050: #define ASCV_NEXTRDY_B 0x0048
1051: #define ASCV_DONENEXT_B 0x0049
1052: #define ASCV_USE_TAGGED_QNG_B 0x004A
1053: #define ASCV_SCSIBUSY_B 0x004B
1054: #define ASCV_Q_DONE_IN_PROGRESS_B 0x004C
1055: #define ASCV_CURCDB_B 0x004D
1056: #define ASCV_RCLUN_B 0x004E
1057: #define ASCV_BUSY_QHEAD_B 0x004F
1058: #define ASCV_DISC1_QHEAD_B 0x0050
1059: #define ASCV_DISC_ENABLE_B 0x0052
1060: #define ASCV_CAN_TAGGED_QNG_B 0x0053
1061: #define ASCV_HOSTSCSI_ID_B 0x0055
1062: #define ASCV_MCODE_CNTL_B 0x0056
1063: #define ASCV_NULL_TARGET_B 0x0057
1064: #define ASCV_FREE_Q_HEAD_W 0x0058
1065: #define ASCV_DONE_Q_TAIL_W 0x005A
1066: #define ASCV_FREE_Q_HEAD_B (ASCV_FREE_Q_HEAD_W+1)
1067: #define ASCV_DONE_Q_TAIL_B (ASCV_DONE_Q_TAIL_W+1)
1068: #define ASCV_HOST_FLAG_B 0x005D
1069: #define ASCV_TOTAL_READY_Q_B 0x0064
1070: #define ASCV_VER_SERIAL_B 0x0065
1071: #define ASCV_HALTCODE_SAVED_W 0x0066
1072: #define ASCV_WTM_FLAG_B 0x0068
1073: #define ASCV_RISC_FLAG_B 0x006A
1074: #define ASCV_REQ_SG_LIST_QP 0x006B
1075:
1076: #define ASC_HOST_FLAG_IN_ISR 0x01
1077: #define ASC_HOST_FLAG_ACK_INT 0x02
1078: #define ASC_RISC_FLAG_GEN_INT 0x01
1079: #define ASC_RISC_FLAG_REQ_SG_LIST 0x02
1080:
1081: #define ASC_IOP_CTRL 0x0F
1082: #define ASC_IOP_STATUS 0x0E
1083: #define ASC_IOP_INT_ACK ASC_IOP_STATUS
1084: #define ASC_IOP_REG_IFC 0x0D
1085: #define ASC_IOP_SYN_OFFSET 0x0B
1086: #define ASC_IOP_EXTRA_CONTROL 0x0D
1087: #define ASC_IOP_REG_PC 0x0C
1088: #define ASC_IOP_RAM_ADDR 0x0A
1089: #define ASC_IOP_RAM_DATA 0x08
1090: #define ASC_IOP_EEP_DATA 0x06
1091: #define ASC_IOP_EEP_CMD 0x07
1092: #define ASC_IOP_VERSION 0x03
1093: #define ASC_IOP_CONFIG_HIGH 0x04
1094: #define ASC_IOP_CONFIG_LOW 0x02
1095: #define ASC_IOP_SIG_BYTE 0x01
1096: #define ASC_IOP_SIG_WORD 0x00
1097: #define ASC_IOP_REG_DC1 0x0E
1098: #define ASC_IOP_REG_DC0 0x0C
1099: #define ASC_IOP_REG_SB 0x0B
1100: #define ASC_IOP_REG_DA1 0x0A
1101: #define ASC_IOP_REG_DA0 0x08
1102: #define ASC_IOP_REG_SC 0x09
1103: #define ASC_IOP_DMA_SPEED 0x07
1104: #define ASC_IOP_REG_FLAG 0x07
1105: #define ASC_IOP_FIFO_H 0x06
1106: #define ASC_IOP_FIFO_L 0x04
1107: #define ASC_IOP_REG_ID 0x05
1108: #define ASC_IOP_REG_QP 0x03
1109: #define ASC_IOP_REG_IH 0x02
1110: #define ASC_IOP_REG_IX 0x01
1111: #define ASC_IOP_REG_AX 0x00
1112:
1113: #define ASC_IFC_REG_LOCK 0x00
1114: #define ASC_IFC_REG_UNLOCK 0x09
1115: #define ASC_IFC_WR_EN_FILTER 0x10
1116: #define ASC_IFC_RD_NO_EEPROM 0x10
1117: #define ASC_IFC_SLEW_RATE 0x20
1118: #define ASC_IFC_ACT_NEG 0x40
1119: #define ASC_IFC_INP_FILTER 0x80
1120: #define ASC_IFC_INIT_DEFAULT (ASC_IFC_ACT_NEG | ASC_IFC_REG_UNLOCK)
1121:
1122: #define SC_SEL 0x80
1123: #define SC_BSY 0x40
1124: #define SC_ACK 0x20
1125: #define SC_REQ 0x10
1126: #define SC_ATN 0x08
1127: #define SC_IO 0x04
1128: #define SC_CD 0x02
1129: #define SC_MSG 0x01
1130:
1131: #define SEC_SCSI_CTL 0x80
1132: #define SEC_ACTIVE_NEGATE 0x40
1133: #define SEC_SLEW_RATE 0x20
1134: #define SEC_ENABLE_FILTER 0x10
1135:
1136: #define ASC_HALT_EXTMSG_IN 0x8000
1137: #define ASC_HALT_CHK_CONDITION 0x8100
1138: #define ASC_HALT_SS_QUEUE_FULL 0x8200
1139: #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX 0x8300
1140: #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX 0x8400
1141: #define ASC_HALT_SDTR_REJECTED 0x4000
1142:
1143: #define ASC_MAX_QNO 0xF8
1144:
1145: #define ASC_DATA_SEC_BEG 0x0080
1146: #define ASC_DATA_SEC_END 0x0080
1147: #define ASC_CODE_SEC_BEG 0x0080
1148: #define ASC_CODE_SEC_END 0x0080
1149: #define ASC_QADR_BEG (0x4000)
1150: #define ASC_QADR_USED (ASC_MAX_QNO * 64)
1151: #define ASC_QADR_END 0x7FFF
1152: #define ASC_QLAST_ADR 0x7FC0
1153: #define ASC_QBLK_SIZE 0x40
1154: #define ASC_BIOS_DATA_QBEG 0xF8
1155: #define ASC_MIN_ACTIVE_QNO 0x01
1156: #define ASC_QLINK_END 0xFF
1157: #define ASC_EEPROM_WORDS 0x10
1158: #define ASC_MAX_MGS_LEN 0x10
1159:
1160: #define ASC_BIOS_ADDR_DEF 0xDC00
1161: #define ASC_BIOS_SIZE 0x3800
1162: #define ASC_BIOS_RAM_OFF 0x3800
1163: #define ASC_BIOS_RAM_SIZE 0x800
1164: #define ASC_BIOS_MIN_ADDR 0xC000
1165: #define ASC_BIOS_MAX_ADDR 0xEC00
1166: #define ASC_BIOS_BANK_SIZE 0x0400
1167:
1168: #define ASC_MCODE_START_ADDR 0x0080
1169:
1170: #define ASC_CFG0_HOST_INT_ON 0x0020
1171: #define ASC_CFG0_BIOS_ON 0x0040
1172: #define ASC_CFG0_VERA_BURST_ON 0x0080
1173: #define ASC_CFG0_SCSI_PARITY_ON 0x0800
1174: #define ASC_CFG1_SCSI_TARGET_ON 0x0080
1175: #define ASC_CFG1_LRAM_8BITS_ON 0x0800
1176: #define ASC_CFG_MSW_CLR_MASK 0x3080
1177:
1178: #define ASC_CSW_TEST1 0x8000
1179: #define ASC_CSW_AUTO_CONFIG 0x4000
1180: #define ASC_CSW_RESERVED1 0x2000
1181: #define ASC_CSW_IRQ_WRITTEN 0x1000
1182: #define ASC_CSW_33MHZ_SELECTED 0x0800
1183: #define ASC_CSW_TEST2 0x0400
1184: #define ASC_CSW_TEST3 0x0200
1185: #define ASC_CSW_RESERVED2 0x0100
1186: #define ASC_CSW_DMA_DONE 0x0080
1187: #define ASC_CSW_FIFO_RDY 0x0040
1188: #define ASC_CSW_EEP_READ_DONE 0x0020
1189: #define ASC_CSW_HALTED 0x0010
1190: #define ASC_CSW_SCSI_RESET_ACTIVE 0x0008
1191: #define ASC_CSW_PARITY_ERR 0x0004
1192: #define ASC_CSW_SCSI_RESET_LATCH 0x0002
1193: #define ASC_CSW_INT_PENDING 0x0001
1194:
1195: #define ASC_CIW_CLR_SCSI_RESET_INT 0x1000
1196: #define ASC_CIW_INT_ACK 0x0100
1197: #define ASC_CIW_TEST1 0x0200
1198: #define ASC_CIW_TEST2 0x0400
1199: #define ASC_CIW_SEL_33MHZ 0x0800
1200: #define ASC_CIW_IRQ_ACT 0x1000
1201:
1202: #define ASC_CC_CHIP_RESET 0x80
1203: #define ASC_CC_SCSI_RESET 0x40
1204: #define ASC_CC_HALT 0x20
1205: #define ASC_CC_SINGLE_STEP 0x10
1206: #define ASC_CC_DMA_ABLE 0x08
1207: #define ASC_CC_TEST 0x04
1208: #define ASC_CC_BANK_ONE 0x02
1209: #define ASC_CC_DIAG 0x01
1210:
1211: #define ASC_1000_ID0W 0x04C1
1212: #define ASC_1000_ID0W_FIX 0x00C1
1213: #define ASC_1000_ID1B 0x25
1214:
1215: #define ASC_EISA_BIG_IOP_GAP (0x1C30-0x0C50)
1216: #define ASC_EISA_SMALL_IOP_GAP (0x0020)
1217: #define ASC_EISA_MIN_IOP_ADDR (0x0C30)
1218: #define ASC_EISA_MAX_IOP_ADDR (0xFC50)
1219: #define ASC_EISA_REV_IOP_MASK (0x0C83)
1220: #define ASC_EISA_PID_IOP_MASK (0x0C80)
1221: #define ASC_EISA_CFG_IOP_MASK (0x0C86)
1222:
1223: #define ASC_GET_EISA_SLOT(iop) ((iop) & 0xF000)
1224:
1225: #define ASC_EISA_ID_740 0x01745004UL
1226: #define ASC_EISA_ID_750 0x01755004UL
1227:
1228: #define ASC_INS_HALTINT 0x6281
1229: #define ASC_INS_HALT 0x6280
1230: #define ASC_INS_SINT 0x6200
1231: #define ASC_INS_RFLAG_WTM 0x7380
1232:
1233:
1234: /******************************************************************************/
1235: /* Macro */
1236: /******************************************************************************/
1237:
1238: /*
1239: * These Macros are used to deal with board CPU Registers and LRAM
1240: */
1241:
1242: #define ASC_GET_QDONE_IN_PROGRESS(iot, ioh) AscReadLramByte((iot), (ioh), ASCV_Q_DONE_IN_PROGRESS_B)
1243: #define ASC_PUT_QDONE_IN_PROGRESS(iot, ioh, val) AscWriteLramByte((iot), (ioh), ASCV_Q_DONE_IN_PROGRESS_B, val)
1244: #define ASC_GET_VAR_FREE_QHEAD(iot, ioh) AscReadLramWord((iot), (ioh), ASCV_FREE_Q_HEAD_W)
1245: #define ASC_GET_VAR_DONE_QTAIL(iot, ioh) AscReadLramWord((iot), (ioh), ASCV_DONE_Q_TAIL_W)
1246: #define ASC_PUT_VAR_FREE_QHEAD(iot, ioh, val) AscWriteLramWord((iot), (ioh), ASCV_FREE_Q_HEAD_W, val)
1247: #define ASC_PUT_VAR_DONE_QTAIL(iot, ioh, val) AscWriteLramWord((iot), (ioh), ASCV_DONE_Q_TAIL_W, val)
1248: #define ASC_GET_RISC_VAR_FREE_QHEAD(iot, ioh) AscReadLramByte((iot), (ioh), ASCV_NEXTRDY_B)
1249: #define ASC_GET_RISC_VAR_DONE_QTAIL(iot, ioh) AscReadLramByte((iot), (ioh), ASCV_DONENEXT_B)
1250: #define ASC_PUT_RISC_VAR_FREE_QHEAD(iot, ioh, val) AscWriteLramByte((iot), (ioh), ASCV_NEXTRDY_B, val)
1251: #define ASC_PUT_RISC_VAR_DONE_QTAIL(iot, ioh, val) AscWriteLramByte((iot), (ioh), ASCV_DONENEXT_B, val)
1252: #define ASC_PUT_MCODE_SDTR_DONE_AT_ID(iot, ioh, id, data) AscWriteLramByte((iot), (ioh), (u_int16_t)((u_int16_t)ASCV_SDTR_DONE_BEG+(u_int16_t)id), (data)) ;
1253: #define ASC_GET_MCODE_SDTR_DONE_AT_ID(iot, ioh, id) AscReadLramByte((iot), (ioh), (u_int16_t)((u_int16_t)ASCV_SDTR_DONE_BEG+(u_int16_t)id)) ;
1254: #define ASC_PUT_MCODE_INIT_SDTR_AT_ID(iot, ioh, id, data) AscWriteLramByte((iot), (ioh), (u_int16_t)((u_int16_t)ASCV_SDTR_DATA_BEG+(u_int16_t)id), data) ;
1255: #define ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, id) AscReadLramByte((iot), (ioh), (u_int16_t)((u_int16_t)ASCV_SDTR_DATA_BEG+(u_int16_t)id)) ;
1256: #define ASC_SYN_INDEX_TO_PERIOD(sc, index) (u_int8_t)((sc)->sdtr_period_tbl[ (index) ])
1257: #define ASC_GET_CHIP_SIGNATURE_BYTE(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_SIG_BYTE)
1258: #define ASC_GET_CHIP_SIGNATURE_WORD(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_SIG_WORD)
1259: #define ASC_GET_CHIP_VER_NO(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_VERSION)
1260: #define ASC_GET_CHIP_CFG_LSW(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_CONFIG_LOW)
1261: #define ASC_GET_CHIP_CFG_MSW(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_CONFIG_HIGH)
1262: #define ASC_SET_CHIP_CFG_LSW(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_CONFIG_LOW, data)
1263: #define ASC_SET_CHIP_CFG_MSW(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_CONFIG_HIGH, data)
1264: #define ASC_GET_CHIP_EEP_CMD(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_EEP_CMD)
1265: #define ASC_SET_CHIP_EEP_CMD(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_EEP_CMD, data)
1266: #define ASC_GET_CHIP_EEP_DATA(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_EEP_DATA)
1267: #define ASC_SET_CHIP_EEP_DATA(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_EEP_DATA, data)
1268: #define ASC_GET_CHIP_LRAM_ADDR(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_RAM_ADDR)
1269: #define ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr) bus_space_write_2((iot), (ioh), ASC_IOP_RAM_ADDR, addr)
1270: #define ASC_GET_CHIP_LRAM_DATA(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_RAM_DATA)
1271: #define ASC_SET_CHIP_LRAM_DATA(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_RAM_DATA, data)
1272: #if BYTE_ORDER == BIG_ENDIAN
1273: #define ASC_GET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh) SWAPBYTES(bus_space_read_2((iot), (ioh), ASC_IOP_RAM_DATA))
1274: #define ASC_SET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_RAM_DATA, SWAPBYTES(data))
1275: #else
1276: #define ASC_GET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_RAM_DATA)
1277: #define ASC_SET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_RAM_DATA, data)
1278: #endif
1279: #define ASC_GET_CHIP_IFC(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_REG_IFC)
1280: #define ASC_SET_CHIP_IFC(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_REG_IFC, data)
1281: #define ASC_GET_CHIP_STATUS(iot, ioh) (u_int16_t)bus_space_read_2((iot), (ioh), ASC_IOP_STATUS)
1282: #define ASC_SET_CHIP_STATUS(iot, ioh, cs_val) bus_space_write_2((iot), (ioh), ASC_IOP_STATUS, cs_val)
1283: #define ASC_GET_CHIP_CONTROL(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_CTRL)
1284: #define ASC_SET_CHIP_CONTROL(iot, ioh, cc_val) bus_space_write_1((iot), (ioh), ASC_IOP_CTRL, cc_val)
1285: #define ASC_GET_CHIP_SYN(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_SYN_OFFSET)
1286: #define ASC_SET_CHIP_SYN(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_SYN_OFFSET, data)
1287: #define ASC_SET_PC_ADDR(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_REG_PC, data)
1288: #define ASC_GET_PC_ADDR(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_PC)
1289: #define ASC_IS_INT_PENDING(iot, ioh) (ASC_GET_CHIP_STATUS((iot), (ioh)) & (ASC_CSW_INT_PENDING | ASC_CSW_SCSI_RESET_LATCH))
1290: #define ASC_GET_CHIP_SCSI_ID(iot, ioh) ((ASC_GET_CHIP_CFG_LSW((iot), (ioh)) >> 8) & ASC_MAX_TID)
1291: #define ASC_GET_EXTRA_CONTROL(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_EXTRA_CONTROL)
1292: #define ASC_SET_EXTRA_CONTROL(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_EXTRA_CONTROL, data)
1293: #define ASC_READ_CHIP_AX(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_AX)
1294: #define ASC_WRITE_CHIP_AX(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_REG_AX, data)
1295: #define ASC_READ_CHIP_IX(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_REG_IX)
1296: #define ASC_WRITE_CHIP_IX(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_REG_IX, data)
1297: #define ASC_READ_CHIP_IH(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_IH)
1298: #define ASC_WRITE_CHIP_IH(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_REG_IH, data)
1299: #define ASC_READ_CHIP_QP(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_REG_QP)
1300: #define ASC_WRITE_CHIP_QP(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_REG_QP, data)
1301: #define ASC_READ_CHIP_FIFO_L(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_FIFO_L)
1302: #define ASC_WRITE_CHIP_FIFO_L(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_REG_FIFO_L, data)
1303: #define ASC_READ_CHIP_FIFO_H(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_FIFO_H)
1304: #define ASC_WRITE_CHIP_FIFO_H(iot, ioh, data) bus_space_write_2((iot), (ioh), ASC_IOP_REG_FIFO_H, data)
1305: #define ASC_READ_CHIP_DMA_SPEED(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_DMA_SPEED)
1306: #define ASC_WRITE_CHIP_DMA_SPEED(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_DMA_SPEED, data)
1307: #define ASC_READ_CHIP_DA0(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_DA0)
1308: #define ASC_WRITE_CHIP_DA0(iot, ioh) bus_space_write_2((iot), (ioh), ASC_IOP_REG_DA0, data)
1309: #define ASC_READ_CHIP_DA1(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_DA1)
1310: #define ASC_WRITE_CHIP_DA1(iot, ioh) bus_space_write_2((iot), (ioh), ASC_IOP_REG_DA1, data)
1311: #define ASC_READ_CHIP_DC0(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_DC0)
1312: #define ASC_WRITE_CHIP_DC0(iot, ioh) bus_space_write_2((iot), (ioh), ASC_IOP_REG_DC0, data)
1313: #define ASC_READ_CHIP_DC1(iot, ioh) bus_space_read_2((iot), (ioh), ASC_IOP_REG_DC1)
1314: #define ASC_WRITE_CHIP_DC1(iot, ioh) bus_space_write_2((iot), (ioh), ASC_IOP_REG_DC1, data)
1315: #define ASC_READ_CHIP_DVC_ID(iot, ioh) bus_space_read_1((iot), (ioh), ASC_IOP_REG_ID)
1316: #define ASC_WRITE_CHIP_DVC_ID(iot, ioh, data) bus_space_write_1((iot), (ioh), ASC_IOP_REG_ID, data)
1317:
1318:
1319: /******************************************************************************/
1320: /* Exported functions */
1321: /******************************************************************************/
1322:
1323:
1324: void AscInitASC_SOFTC(ASC_SOFTC *);
1325: u_int16_t AscInitFromEEP(ASC_SOFTC *);
1326: u_int16_t AscInitFromASC_SOFTC(ASC_SOFTC *);
1327: int AscInitDriver(ASC_SOFTC *);
1328: void AscReInitLram(ASC_SOFTC *);
1329: int AscFindSignature(bus_space_tag_t, bus_space_handle_t);
1330: int AscISR(ASC_SOFTC *);
1331: int AscExeScsiQueue(ASC_SOFTC *, ASC_SCSI_Q *);
1332: void AscInquiryHandling(ASC_SOFTC *, u_int8_t, ASC_SCSI_INQUIRY *);
1333: int AscAbortCCB(ASC_SOFTC *, u_int32_t);
1334: int AscResetBus(ASC_SOFTC *);
1335: int AscResetDevice(ASC_SOFTC *, u_char);
1336:
1337:
1338: /******************************************************************************/
1339:
1340: #endif /* _ADVANSYS_NARROW_LIBRARY_H_ */
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