Annotation of sys/arch/vax/vsa/lcgreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: lcgreg.h,v 1.3 2006/08/22 21:05:03 miod Exp $ */
2: /* $NetBSD: lcgreg.h,v 1.4 2005/12/11 12:19:34 christos Exp $ */
3:
4: /*-
5: * Copyright (c) 2000 The NetBSD Foundation, Inc.
6: * All rights reserved.
7: *
8: * This code is derived from software contributed to The NetBSD Foundation
9: * by Matt Thomas of 3am Software Foundry.
10: *
11: * Redistribution and use in source and binary forms, with or without
12: * modification, are permitted provided that the following conditions
13: * are met:
14: * 1. Redistributions of source code must retain the above copyright
15: * notice, this list of conditions and the following disclaimer.
16: * 2. Redistributions in binary form must reproduce the above copyright
17: * notice, this list of conditions and the following disclaimer in the
18: * documentation and/or other materials provided with the distribution.
19: * 3. All advertising materials mentioning features or use of this software
20: * must display the following acknowledgement:
21: * This product includes software developed by the NetBSD
22: * Foundation, Inc. and its contributors.
23: * 4. Neither the name of The NetBSD Foundation nor the names of its
24: * contributors may be used to endorse or promote products derived
25: * from this software without specific prior written permission.
26: *
27: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37: * POSSIBILITY OF SUCH DAMAGE.
38: */
39:
40: /*
41: * The registers of the LCG used in the VS4000/60 and VS4000/VLC.
42: * All relative to 0x20100000
43: */
44:
45: /* Memory Control, Flow Control, Configuration Registers
46: */
47: #define LCG_REG_MEM_CONFIG 0x001800
48: #define LCG_REG_MEM_STATUS 0x001804
49: #define LCG_REG_MEM_CURRENT_STATE 0x001808
50: #define LCG_REG_MEM_ERROR 0x00180c
51: #define LCG_REG_SLOW_CONTROL_STATUS 0x001810
52:
53: /* Video Control Registers
54: */
55: #define LCG_REG_VIDEO_CONFIG 0x001e00
56: #define VIDEO_VSTATE 0xc0000000
57: #define VIDEO_VFRONT_PORCH 0x00000000
58: #define VIDEO_VSYNC 0x40000000
59: #define VIDEO_VBACK_PORCH 0x80000000
60: #define VIDEO_VACTIVE 0xc0000000
61: #define VIDEO_HSTATE 0x30000000
62: #define VIDEO_HFRONT_PORCH 0x00000000
63: #define VIDEO_HSYNC 0x10000000
64: #define VIDEO_HBACK_PORCH 0x20000000
65: #define VIDEO_HACTIVE 0x30000000
66: #define VIDEO_CONSOLE_LUT 0x02000000
67: #define VIDEO_CONTROL_LUT 0x01000000
68: #define VIDEO_CURSOR_ACTIVE 0x00400000
69: #define VIDEO_CURSOR_SCANLINE 0x003f0000
70: #define VIDEO_RESET 0x00008000
71: #define VIDEO_LUT_LOAD_SIZE 0x00002000
72: #define VIDEO_SYNC_ENABLE 0x00001000
73: #define VIDEO_LUT_SHIFT_SEL 0x00000800
74: #define VIDEO_CLOCK_SEL 0x00000400
75: #define VIDEO_MEM_REFRESH_SEL_MASK 0x00000300
76: #define VIDEO_MEM_REFRESH_SEL_SHIFT 8
77: #define VIDEO_REFRESH_SEL 0x000000c0
78: #define VIDEO_SHIFT_SEL 0x00000020
79: #define VIDEO_CURSOR_PIN_TYPE 0x00000010
80: #define VIDEO_LUT_LOAD_ENABLE 0x00000008
81: #define VIDEO_CURSOR_ENABLE 0x00000004
82: #define VIDEO_ENABLE_VIDEO 0x00000002
83: #define VIDEO_TIMING_ENABLE 0x00000001
84: #define LCG_REG_VIDEO_HTIMING 0x001e10
85: #define LCG_REG_VIDEO_VTIMING 0x001e14
86: #define LCG_REG_VIDEO_TIMING 0x001e18
87: #define LCG_REG_VIDEO_X 0x000e30
88: #define LCG_REG_VIDEO_Y 0x000e30
89: #define LCG_REG_VIDEO_REFRESH_BASE 0x000e34
90: #define LCG_REG_VIDEO_REFRESH_SHIFT 0x000e40
91: #define LCG_REG_VIDEO_LUT_LOAD_COUNT 0x000e40
92: #define LCG_REG_CURSOR_SCANLINE_LW0 0x000e50
93: #define LCG_REG_CURSOR_SCANLINE_LW1 0x000e54
94: #define LCG_REG_CURSOR_SCANLINE_LW2 0x000e58
95: #define LCG_REG_CURSOR_SCANLINE_LW3 0x000e5c
96: #define LCG_REG_CURSOR_BASE 0x000e80
97: #define LCG_REG_CURSOR_XY 0x000e84
98: #define LCG_REG_CURSOR_X 0x000e84
99: #define LCG_REG_CURSOR_Y 0x000e84
100: #define LCG_REG_LUT_CONSOLE_SEL 0x000ee0
101: #define LUT_SEL_CONSOLE 0x00000000
102: #define LUT_SEL_COLOR 0x00000001
103: #define LCG_REG_LUT_COLOR_BASE_W 0x0006e4
104: #define LCG_REG_LUT_COLOR_BASE_R 0x0006e4
105: #define LCG_REG_LUT_CONTROL_BASE 0x000ee8
106: #define LCG_REG_VIDEO_COUNTER_TEST 0x000f00
107: #define LCG_REG_MEM_REFRESH_BASE 0x000f04
108:
109: /* Graphics Control and VM Registers
110: */
111: #define LCG_REG_LCG_GO 0x000c80
112: #define GO_VM 0x00000008
113: #define GO_AG 0x00000002
114: #define GO_FIFO 0x00000001
115: #define LCG_REG_NEXT_ADDRESS 0x001334
116: #define LCG_REG_PA_SPTE_PTE 0x001338
117: #define LCG_REG_TB_INVALIDATE_SINGLE 0x001a00
118: #define LCG_REG_TB_INVALIDATE_ALL 0x001a08
119: #define LCG_REG_TB_INVALIDATE_STATUS 0x001a10
120: #define LCG_REG_TB_STATUS 0x001c00
121: #define LCG_REG_TB_VPN_COUNT 0x001c04
122: #define LCG_REG_TB_DEST_VPN 0x001c14
123: #define LCG_REG_TB_SOURCE_VPN 0x001c18
124: #define LCG_REG_TB_STENCIL_VPN 0x001c1c
125: #define LCG_REG_TB_DEST_DATA_PFN_R 0x001c24
126: #define LCG_REG_TB_DEST_DATA_PFN_W 0x001c24
127: #define LCG_REG_TB_SOURCE_DATA_PFN_R 0x001c28
128: #define LCG_REG_TB_SOURCE_DATA_PFN_W 0x001c28
129: #define LCG_REG_TB_STENCIL_DATA_PFN_R 0x001c2c
130: #define LCG_REG_TB_STENCIL_DATA_PFN_W 0x001c2c
131: #define LCG_REG_TB_DEST_PRE_PFN_R 0x001c34
132: #define LCG_REG_TB_DEST_PRE_PFN_W 0x001c34
133: #define LCG_REG_TB_SOURCE_PTE_PFN_R 0x001c38
134: #define LCG_REG_TB_SOURCE_PTE_PFN_W 0x001c38
135: #define LCG_REG_TB_STENCIL_PTE_PFN_R 0x001c3c
136: #define LCG_REG_TB_STENCIL_PTE_PFN_W 0x001c3c
137: #define LCG_REG_GRAPHICS_CONFIG 0x001c90
138: #define LCG_REG_GRAPHICS_INT_STATUS 0x001c94
139: #define LCG_REG_GRAPHICS_INT_SET_ENABLE 0x001c98
140: #define LCG_REG_GRAPHICS_INT_CLR_ENABLE 0x001c9c
141: #define LCG_REG_GRAPHICS_SUB_STATUS 0x001ca0
142: #define GSS_AG_BUSY 0x80000000
143: #define GSS_SHORT_CIRCUIT 0x20000000
144: #define GSS_VALID_PACKET 0x10000000
145: #define GSS_1ST_LONGWORD 0x08000000
146: #define GSS_FIFO_ARBITRATE 0x04000000
147: #define GSS_FIFO_COMMANDER 0x03000000
148: #define GSS_AG_BACKWARDS 0x00800000
149: #define GSS_AG_VIRTUAL 0x00400000
150: #define GSS_AG_ARBITRATE 0x00200000
151: #define GSS_AG_READ_ID 0x00100000
152: #define GSS_AG_ACCESS_TYPE 0x000c0000
153: #define GSS_AG_ACCESS_SIZE 0x00030000
154: #define GSS_RESIDUE_LW0 0x00008000
155: #define GSS_RESIDUE_LW1 0x00004000
156: #define GSS_RESIDUE_LW2 0x00002000
157: #define GSS_FIFO_TAIL_BITS 0x00001800
158: #define GSS_FIFO_IDU 0x00000400
159: #define GSS_EXECUTING_CLIP 0x00000200
160: #define GSS_FIFO_BPT_STALL 0x00000100
161: #define GSS_FIFO_WFSYNC_STALL 0x00000080
162: #define GSS_FIFO_AGBUSY_STALL 0x00000040
163: #define GSS_ADRS_BPT_VIRTUAL 0x00000010
164: #define GSS_VM 0x00000008
165: #define GSS_FIFO_IDLE 0x00000004
166: #define GSS_AG_ACCESS 0x00000002
167: #define GSS_FIFO 0x00000001
168: #define LCG_REG_GRAPHICS_CONTROL 0x001ca4
169: #define CTRL_RESET 0x80000000
170: #define CTRL_AG 0x40000000
171: #define CTRL_CLIP_LIST 0x20000000
172: #define CTRL_FIFO 0x10000000
173: #define CTRL_SHORT_CIRCUIT 0x08000000
174: #define CTRL_VM 0x04000000
175: #define CTRL_VM_PROTECTION 0x02000000
176: #define CTRL_OPT_INTERFACE 0x01000000
177: #define CTRL_OPT_TIMEOUT_SEL 0x00c00000
178: #define CTRL_OPT_RESET 0x00200000
179: #define CTRL_OPTION_NORESET 0x00100000
180: #define CTRL_AG_ACCESS_BPT_ARM 0x00000800
181: #define CTRL_PACKET_BPT_ARM 0x00000200
182: #define CTRL_ADDRESS_BPT_ARM 0x00000100
183: #define LCG_REG_BREAKPT_ADDRESS 0x001cb0
184: #define LCG_REG_BREAKPT_VIRTUAL 0x001cb0
185: #define LCG_REG_WRITE_PROTECT_LOW_HIGH 0x001cc0
186: #define LCG_REG_WRITE_PROTECT_LOW 0x001cc0
187: #define LCG_REG_WRITE_PROTECT_HIGH 0x001cc0
188: #define LCG_REG_MAX_VIRTUAL_ADDRESS 0x002350
189: #define LCG_REG_PA_SPTE_POBR 0x002354
190:
191: /* Clip List / Command FIFO Registers
192: */
193: #define LCG_REG_CLIP_LIST_OFFSET 0x0004e4
194: #define LCG_REG_CLIP_LIST_BASE 0x0004e4
195: #define LCG_REG_CLIP_LIST 0x0004e4
196: #define LCG_REG_FIFO_MASKS 0x000570
197: #define FIFO_16K 0x00000000
198: #define FIFO_32K 0x00004000
199: #define FIFO_64K 0x0000c000
200: #define FIFO_AFULL_AT_64 0x00000000
201: #define FIFO_AFULL_AT_128 0x00002000
202: #define FIFO_AFULL_AT_256 0x00003000
203: #define FIFO_AFULL_AT_512 0x00003800
204: #define FIFO_AFULL_AT_1024 0x00003c00
205: #define FIFO_AFULL_AT_2048 0x00003e00
206: #define FIFO_AFULL_AT_4096 0x00003f00
207: #define FIFO_AEMPTY_AT_32 0x00000000
208: #define FIFO_AEMPTY_AT_64 0x00000080
209: #define FIFO_AEMPTY_AT_128 0x00000040
210: #define FIFO_AEMPTY_AT_256 0x00000020
211: #define FIFO_AEMPTY_AT_512 0x00000010
212: #define FIFO_AEMPTY_AT_1024 0x00000008
213: #define FIFO_AEMPTY_AT_2048 0x00000004
214: #define FIFO_AEMPTY_AT_4096 0x00000002
215: #define FIFO_AEMPTY_AT_8192 0x00000001
216: #define LCG_REG_FIFO_HEAD_OFFSET 0x000574
217: #define LCG_REG_FIFO_BASE 0x000574
218: #define LCG_REG_FIFO_HEAD 0x000574
219: #define LCG_REG_FIFO_TAIL_OFFSET 0x000578
220: #define LCG_REG_FIFO_BASE2 0x000578
221: #define LCG_REG_FIFO_TAIL 0x000578
222: #define LCG_REG_CLIP_LIST_SAVE_OFFSET 0x000ce4
223: #define LCG_REG_FIFO_RESIDUE_LW0 0x000d04
224: #define LCG_REG_FIFO_RESIDUE_LW1 0x000d08
225: #define LCG_REG_FIFO_RESIDUE_LW2 0x000d0c
226: #define LCG_REG_FIFO_LENGTH 0x000d70
227: #define LCG_REG_FIFO_SAVE_HEAD_OFFSET 0x000d74
228: #define LCG_REG_FIFO_WINDOW_BASE 0x080000
229: #define LCG_REG_FIFO_WINDOW_END 0x100000
230:
231: /* Graphics Data Buffer and Pixel SLU Registers
232: */
233: #define LCG_REG_LOGICAL_FUNCTION 0x000220
234: #define LCG_REG_PLANE_MASK 0x000234
235: #define LCG_REG_SOURCE_PLANE_INDEX 0x00026c
236: #define LCG_REG_FOREGROUND_PIXEL 0x0002c0
237: #define LCG_REG_BACKGROUND_PIXEL 0x0004c0
238: #define LCG_REG_GDB_LW0 0x000d80
239: #define LCG_REG_GDB_LW1 0x000d84
240: #define LCG_REG_GDB_LW2 0x000d88
241: #define LCG_REG_GDB_LW3 0x000d8c
242: #define LCG_REG_GDB_LW4 0x000d90
243: #define LCG_REG_GDB_LW5 0x000d94
244: #define LCG_REG_GDB_LW6 0x000d98
245: #define LCG_REG_GDB_LW7 0x000d9c
246: #define LCG_REG_SLU_STATE 0x000da0
247:
248: /* Address Generator Registers
249: */
250: #define LCG_REG_CLIP_MIN_Y 0x000244
251: #define LCG_REG_CLIP_MIN_MAX_X 0x000248
252: #define LCG_REG_CLIP_MIN_X 0x000248
253: #define LCG_REG_CLIP_MAX_X 0x000248
254: #define LCG_REG_CLIP_MAX_Y 0x00024c
255: #define LCG_REG_DEST_X_BIAS 0x000250
256: #define LCG_REG_DEST_Y_ORIGIN 0x000254
257: #define LCG_REG_DEST_Y_STEP 0x000258
258: #define LCG_REG_SOURCE_X_BIAS 0x000260
259: #define LCG_REG_SOURCE_Y_BASE 0x000264
260: #define LCG_REG_SOURCE_Y_STEP_WIDTH 0x000268
261: #define LCG_REG_SOURCE_Y_STEP 0x000268
262: #define LCG_REG_SOURCE_WIDTH 0x000268
263: #define LCG_REG_STENCIL_X_BIAS 0x000270
264: #define LCG_REG_STENCIL_Y_BASE 0x000274
265: #define LCG_REG_STENCIL_Y_STEP 0x000278
266: #define LCG_REG_DEST_Y_BASE 0x000284
267: #define LCG_REG_DEST_X 0x000290
268: #define LCG_REG_DEST_WIDTH_HEIGHT 0x000294
269: #define LCG_REG_DEST_WIDTH 0x000294
270: #define LCG_REG_DEST_HEIGHT 0x000294
271: #define LCG_REG_AG_STATUS2 0x000320
272: #define LCG_REG_AG_CURRENT_STATE 0x000320
273: #define LCG_REG_CURRENT_OPCODE 0x000320
274: #define LCG_REG_OP_ACTION_CODE 0x000320
275: #define LCG_REG_AG_STATUS 0x000324
276: #define LCG_REG_NEXT_X 0x000330
277: #define LCG_REG_CLIP_X_DIFF 0x000330
278: #define LCG_REG_SOURCE_X_BIAS0 0x000460
279: #define LCG_REG_SOURCE_WIDTH0 0x000468
280: #define LCG_REG_DEST_X0 0x000490
281: #define LCG_REG_DEST_WIDTH0 0x000494
282: #define LCG_REG_TILE_ROTATION 0x000660
283: #define LCG_REG_TILE_WIDTH 0x000668
284:
285: /*
286: * LUT data bits
287: */
288: #define LUT_ADRS_REG 0x00 /* write to address register */
289: #define LUT_COLOR_AUTOINC 0x01 /* write to LUT and autoincrement */
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