Annotation of sys/arch/vax/vax/ka680.c, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: ka680.c,v 1.10 2002/09/21 13:42:43 hugh Exp $ */
2: /* $NetBSD: ka680.c,v 1.3 2001/01/28 21:01:53 ragge Exp $ */
3: /*
4: * Copyright (c) 2002 Hugh Graham.
5: * Copyright (c) 2000 Ludd, University of Lule}, Sweden.
6: * All rights reserved.
7: *
8: * Redistribution and use in source and binary forms, with or without
9: * modification, are permitted provided that the following conditions
10: * are met:
11: * 1. Redistributions of source code must retain the above copyright
12: * notice, this list of conditions and the following disclaimer.
13: * 2. Redistributions in binary form must reproduce the above copyright
14: * notice, this list of conditions and the following disclaimer in the
15: * documentation and/or other materials provided with the distribution.
16: * 3. All advertising materials mentioning features or use of this software
17: * must display the following acknowledgement:
18: * This product includes software developed at Ludd, University of
19: * Lule}, Sweden and its contributors.
20: * 4. The name of the author may not be used to endorse or promote products
21: * derived from this software without specific prior written permission
22: *
23: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33: */
34:
35: /* Done by Michael Kukat (michael@unixiron.org) */
36: /* minor modifications for KA690 cache support by isildur@vaxpower.org */
37:
38: #include <sys/param.h>
39: #include <sys/types.h>
40: #include <sys/device.h>
41: #include <sys/kernel.h>
42: #include <sys/systm.h>
43:
44: #include <machine/pte.h>
45: #include <machine/cpu.h>
46: #include <machine/mtpr.h>
47: #include <machine/sid.h>
48: #include <machine/nexus.h>
49: #include <machine/uvax.h>
50: #include <machine/ka680.h>
51: #include <machine/clock.h>
52: #include <machine/scb.h>
53:
54: static void ka680_conf(void);
55: static void ka680_cache_enable(void);
56: static void ka680_softmem(void *);
57: static void ka680_hardmem(void *);
58: static void ka680_steal_pages(void);
59: static void ka680_memerr(void);
60: static int ka680_mchk(caddr_t);
61:
62: /*
63: * KA680-specific IPRs. KA680 has the funny habit to control all caches
64: * via IPRs.
65: */
66: #define PR_CCTL 0xa0
67: #define CCTL_ENABLE 0x00000001
68: #define CCTL_SW_ETM 0x40000000
69: #define CCTL_HW_ETM 0x80000000
70:
71: #define PR_BCETSTS 0xa3
72: #define PR_BCEDSTS 0xa6
73: #define PR_NESTS 0xae
74:
75: #define PR_VMAR 0xd0
76: #define PR_VTAG 0xd1
77: #define PR_ICSR 0xd3
78: #define ICSR_ENABLE 0x01
79:
80: #define PR_PCCTL 0xf8
81: #define PCCTL_P_EN 0x10
82: #define PCCTL_I_EN 0x02
83: #define PCCTL_D_EN 0x01
84:
85:
86: /*
87: * Declaration of KA680-specific calls.
88: */
89: struct cpu_dep ka680_calls = {
90: ka680_steal_pages,
91: ka680_mchk,
92: ka680_memerr,
93: ka680_conf,
94: generic_clkread,
95: generic_clkwrite,
96: 24, /* ~VUPS */
97: 2, /* SCB pages */
98: generic_halt,
99: generic_reboot,
100: };
101:
102: void
103: ka680_conf()
104: {
105: char *cpuname;
106:
107: /* Don't ask why, but we seem to need this... */
108:
109: volatile int *hej = (void *)mfpr(PR_ISP);
110: *hej = *hej;
111: hej[-1] = hej[-1];
112:
113: cpmbx = (struct cpmbx *)vax_map_physmem(0x20140400, 1);
114:
115: switch(vax_boardtype) {
116: case VAX_BTYP_1301:
117: switch((vax_siedata & 0xff00) >> 8) {
118: case VAX_STYP_675:
119: cpuname = "KA675";
120: break;
121: case VAX_STYP_680:
122: cpuname = "KA680";
123: break;
124: case VAX_STYP_690:
125: cpuname = "KA690";
126: break;
127: default:
128: cpuname = "unknown NVAX 1301";
129: }
130: break;
131: case VAX_BTYP_1305:
132: switch((vax_siedata & 0xff00) >> 8) {
133: case VAX_STYP_681:
134: cpuname = "KA681";
135: break;
136: case VAX_STYP_691:
137: cpuname = "KA691";
138: break;
139: case VAX_STYP_694:
140: if (vax_cpudata & 0x1000)
141: cpuname = "KA694";
142: else
143: cpuname = "KA692";
144: break;
145: default:
146: cpuname = "unknown NVAX 1305";
147: }
148: }
149: printf("cpu0: %s, ucode rev %d\n", cpuname, vax_cpudata & 0xff);
150: }
151:
152: void
153: ka680_cache_enable()
154: {
155: int start, pslut, fslut, cslut, havevic;
156:
157: /*
158: * Turn caches off.
159: */
160: mtpr(0, PR_ICSR);
161: mtpr(0, PR_PCCTL);
162: mtpr(mfpr(PR_CCTL) | CCTL_SW_ETM, PR_CCTL);
163:
164: /*
165: * Invalidate caches.
166: */
167: mtpr(mfpr(PR_CCTL) | 6, PR_CCTL); /* Set cache size and speed */
168: mtpr(mfpr(PR_BCETSTS), PR_BCETSTS); /* Clear error bits */
169: mtpr(mfpr(PR_BCEDSTS), PR_BCEDSTS); /* Clear error bits */
170: mtpr(mfpr(PR_NESTS), PR_NESTS); /* Clear error bits */
171:
172: switch((vax_siedata & 0xff00) >> 8) {
173: case VAX_STYP_680:
174: case VAX_STYP_681: /* XXX untested */
175: fslut = 0x01420000;
176: cslut = 0x01020000;
177: havevic = 1;
178: break;
179: case VAX_STYP_690:
180: fslut = 0x01440000;
181: cslut = 0x01040000;
182: havevic = 1;
183: break;
184: case VAX_STYP_691: /* XXX untested */
185: fslut = 0x01420000;
186: cslut = 0x01020000;
187: havevic = 1;
188: break;
189: case VAX_STYP_694: /* XXX untested */
190: fslut = 0x01440000;
191: cslut = 0x01040000;
192: havevic = 1;
193: break;
194: case VAX_STYP_675:
195: default: /* unknown cpu; cross fingers */
196: fslut = 0x01420000;
197: cslut = 0x01020000;
198: havevic = 0;
199: break;
200: }
201:
202: start = 0x01400000;
203:
204: /* Flush cache lines */
205: for (; start < fslut; start += 0x20)
206: mtpr(0, start);
207:
208: mtpr((mfpr(PR_CCTL) & ~(CCTL_SW_ETM|CCTL_ENABLE)) | CCTL_HW_ETM,
209: PR_CCTL);
210:
211: start = 0x01000000;
212:
213: /* clear tag and valid */
214: for (; start < cslut; start += 0x20)
215: mtpr(0, start);
216:
217: mtpr(mfpr(PR_CCTL) | 6 | CCTL_ENABLE, PR_CCTL); /* enab. bcache */
218:
219: start = 0x01800000;
220: pslut = 0x01802000;
221:
222: /* Clear primary cache */
223: for (; start < pslut; start += 0x20)
224: mtpr(0, start);
225:
226: /* Flush the pipes (via REI) */
227: asm("movpsl -(sp); movab 1f,-(sp); rei; 1:;");
228:
229: /* Enable primary cache */
230: mtpr(PCCTL_P_EN|PCCTL_I_EN|PCCTL_D_EN, PR_PCCTL);
231:
232: /* Enable the VIC */
233: if (havevic) {
234: int slut;
235:
236: start = 0;
237: slut = 0x800;
238: for (; start < slut; start += 0x20) {
239: mtpr(start, PR_VMAR);
240: mtpr(0, PR_VTAG);
241: }
242: mtpr(ICSR_ENABLE, PR_ICSR);
243: }
244: }
245:
246: /*
247: * Why may we get memory errors during startup???
248: */
249:
250: void
251: ka680_hardmem(void *arg)
252: {
253: if (cold == 0)
254: printf("Hard memory error\n");
255: splhigh();
256: }
257:
258: void
259: ka680_softmem(void *arg)
260: {
261: if (cold == 0)
262: printf("Soft memory error\n");
263: splhigh();
264: }
265:
266: void
267: ka680_steal_pages()
268: {
269: /*
270: * Get the soft and hard memory error vectors now.
271: */
272: scb_vecalloc(0x54, ka680_softmem, NULL, 0, NULL);
273: scb_vecalloc(0x60, ka680_hardmem, NULL, 0, NULL);
274:
275: /* Turn on caches (to speed up execution a bit) */
276: ka680_cache_enable();
277: }
278:
279: void
280: ka680_memerr()
281: {
282: printf("Memory err!\n");
283: }
284:
285: int
286: ka680_mchk(caddr_t addr)
287: {
288: panic("Machine check");
289: return 0;
290: }
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