Annotation of sys/arch/vax/vax/ka53.c, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: ka53.c,v 1.5 2002/09/21 13:42:43 hugh Exp $ */
2: /* $NetBSD: ka53.c,v 1.2 2000/06/04 02:19:27 matt Exp $ */
3: /*
4: * Copyright (c) 2002 Hugh Graham.
5: * Copyright (c) 2000 Ludd, University of Lule}, Sweden.
6: * All rights reserved.
7: *
8: * Redistribution and use in source and binary forms, with or without
9: * modification, are permitted provided that the following conditions
10: * are met:
11: * 1. Redistributions of source code must retain the above copyright
12: * notice, this list of conditions and the following disclaimer.
13: * 2. Redistributions in binary form must reproduce the above copyright
14: * notice, this list of conditions and the following disclaimer in the
15: * documentation and/or other materials provided with the distribution.
16: * 3. All advertising materials mentioning features or use of this software
17: * must display the following acknowledgement:
18: * This product includes software developed at Ludd, University of
19: * Lule}, Sweden and its contributors.
20: * 4. The name of the author may not be used to endorse or promote products
21: * derived from this software without specific prior written permission
22: *
23: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33: */
34:
35: #include <sys/param.h>
36: #include <sys/device.h>
37: #include <sys/systm.h>
38: #include <sys/kernel.h>
39:
40: #include <machine/clock.h>
41: #include <machine/cpu.h>
42: #include <machine/scb.h>
43: #include <machine/sid.h>
44: #include <machine/mtpr.h>
45:
46: static void ka53_conf(void);
47: static void ka53_memerr(void);
48: static int ka53_mchk(caddr_t);
49: static void ka53_softmem(void *);
50: static void ka53_hardmem(void *);
51: static void ka53_steal_pages(void);
52: static void ka53_cache_enable(void);
53:
54: /*
55: * Declaration of 680-specific calls.
56: */
57: struct cpu_dep ka53_calls = {
58: ka53_steal_pages,
59: ka53_mchk,
60: ka53_memerr,
61: ka53_conf,
62: generic_clkread,
63: generic_clkwrite,
64: 32, /* ~VUPS */
65: 2, /* SCB pages */
66: generic_halt,
67: generic_reboot,
68: };
69:
70: void
71: ka53_conf()
72: {
73: char *cpuname;
74:
75: /* This initialises ISP, avoiding interrupt exceptions */
76: {volatile int *hej = (void *)mfpr(PR_ISP); *hej = *hej; hej[-1] = hej[-1];}
77:
78: /* This vector (qbus related?) comes out of nowhere, ignore it for now */
79: scb_vecalloc(0x0, (void *)nullop, NULL, SCB_ISTACK, NULL);
80:
81: cpmbx = (struct cpmbx *)vax_map_physmem(0x20140400, 1);
82:
83: switch((vax_siedata >> 8) & 0xFF) {
84: case VAX_STYP_50:
85: cpuname = "KA50";
86: break;
87: case VAX_STYP_51:
88: cpuname = "KA51";
89: break;
90: case VAX_STYP_52:
91: cpuname = "KA52";
92: break;
93: case VAX_STYP_53:
94: cpuname = "KA53";
95: break;
96: default:
97: cpuname = "unknown NVAX";
98: }
99: printf("cpu0: %s, ucode rev %d\n", cpuname, vax_cpudata & 0xff);
100: }
101:
102: /*
103: * Why may we get memory errors during startup???
104: */
105:
106: void
107: ka53_hardmem(void *arg)
108: {
109: if (cold == 0)
110: printf("Hard memory error\n");
111: splhigh();
112: }
113:
114: void
115: ka53_softmem(void *arg)
116: {
117: if (cold == 0)
118: printf("Soft memory error\n");
119: splhigh();
120: }
121:
122:
123: /*
124: * KA53-specific IPRs. KA53 has the funny habit to control all caches
125: * via IPRs.
126: */
127: #define PR_CCTL 0xa0
128: #define CCTL_ENABLE 0x00000001
129: #define CCTL_SW_ETM 0x40000000
130: #define CCTL_HW_ETM 0x80000000
131:
132: #define PR_BCETSTS 0xa3
133: #define PR_BCEDSTS 0xa6
134: #define PR_NESTS 0xae
135:
136: #define PR_VMAR 0xd0
137: #define PR_VTAG 0xd1
138: #define PR_ICSR 0xd3
139: #define ICSR_ENABLE 0x01
140:
141: #define PR_PCCTL 0xf8
142: #define PCCTL_P_EN 0x10
143: #define PCCTL_I_EN 0x02
144: #define PCCTL_D_EN 0x01
145:
146: void
147: ka53_cache_enable()
148: {
149: int start, slut;
150:
151: /*
152: * Turn caches off.
153: */
154: mtpr(0, PR_ICSR);
155: mtpr(0, PR_PCCTL);
156: mtpr(mfpr(PR_CCTL) | CCTL_SW_ETM, PR_CCTL);
157:
158: /*
159: * Invalidate caches.
160: */
161: mtpr(mfpr(PR_CCTL) | 6, PR_CCTL); /* Set cache size and speed */
162: mtpr(mfpr(PR_BCETSTS), PR_BCETSTS); /* Clear error bits */
163: mtpr(mfpr(PR_BCEDSTS), PR_BCEDSTS); /* Clear error bits */
164: mtpr(mfpr(PR_NESTS), PR_NESTS); /* Clear error bits */
165:
166:
167: start = 0x01400000;
168: slut = 0x01420000;
169:
170: /* Flush cache lines */
171: for (; start < slut; start += 0x20)
172: mtpr(0, start);
173:
174: mtpr((mfpr(PR_CCTL) & ~(CCTL_SW_ETM|CCTL_ENABLE)) | CCTL_HW_ETM,
175: PR_CCTL);
176:
177: start = 0x01000000;
178: slut = 0x01020000;
179:
180: /* clear tag and valid */
181: for (; start < slut; start += 0x20)
182: mtpr(0, start);
183:
184: mtpr(mfpr(PR_CCTL) | 6 | CCTL_ENABLE, PR_CCTL); /* enab. bcache */
185:
186: start = 0x01800000;
187: slut = 0x01802000;
188:
189: /* Clear primary cache */
190: for (; start < slut; start += 0x20)
191: mtpr(0, start);
192:
193: /* Flush the pipes (via REI) */
194: asm("movpsl -(sp); movab 1f,-(sp); rei; 1:;");
195:
196: /* Enable primary cache */
197: mtpr(PCCTL_P_EN|PCCTL_I_EN|PCCTL_D_EN, PR_PCCTL);
198:
199: /* Enable the VIC */
200: start = 0;
201: slut = 0x800;
202: for (; start < slut; start += 0x20) {
203: mtpr(start, PR_VMAR);
204: mtpr(0, PR_VTAG);
205: }
206: mtpr(ICSR_ENABLE, PR_ICSR);
207: }
208:
209: void
210: ka53_memerr()
211: {
212: printf("Memory err!\n");
213: }
214:
215: int
216: ka53_mchk(caddr_t addr)
217: {
218: mtpr(0x00, PR_MCESR);
219: printf("Machine Check\n");
220: return 0;
221: }
222:
223: void
224: ka53_steal_pages()
225: {
226:
227: /*
228: * Get the soft and hard memory error vectors now.
229: */
230:
231: scb_vecalloc(0x54, ka53_softmem, NULL, 0, NULL);
232: scb_vecalloc(0x60, ka53_hardmem, NULL, 0, NULL);
233:
234:
235: /* Turn on caches (to speed up execution a bit) */
236: ka53_cache_enable();
237: }
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