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Revision 1.1.1.1 (vendor branch), Tue Mar 4 16:08:46 2008 UTC (16 years, 3 months ago) by nbrk
Branch: OPENBSD_4_2_BASE, MAIN
CVS Tags: jornada-partial-support-wip, HEAD
Changes since 1.1: +0 -0 lines

Import of OpenBSD 4.2 release kernel tree with initial code to support 
Jornada 720/728, StrongARM 1110-based handheld PC.
At this point kernel roots on NFS and boots into vfs_mountroot() and traps.
What is supported:
- glass console, Jornada framebuffer (jfb) works in 16bpp direct color mode
(needs some palette tweaks for non black/white/blue colors, i think)
- saic, SA11x0 interrupt controller (needs cleanup)
- sacom, SA11x0 UART (supported only as boot console for now)
- SA11x0 GPIO controller fully supported (but can't handle multiple interrupt
handlers on one gpio pin)
- sassp, SSP port on SA11x0 that attaches spibus
- Jornada microcontroller (jmcu) to control kbd, battery, etc throught
the SPI bus (wskbd attaches on jmcu, but not tested)
- tod functions seem work
- initial code for SA-1111 (chip companion) : this is TODO

Next important steps, i think:
- gpio and intc on sa1111
- pcmcia support for sa11x0 (and sa1111 help logic)
- REAL root on nfs when we have PCMCIA support (we may use any of supported pccard NICs)
- root on wd0! (using already supported PCMCIA-ATA)

/*	$OpenBSD: crl.h,v 1.3 2000/04/27 01:10:11 bjc Exp $	*/
/*	$NetBSD: crl.h,v 1.2 1999/04/12 20:57:52 pk Exp $	*/
/* 
 * @(#)crl.h	7.1 (Berkeley) 6/5/86
 */

/****************************************************************
 *                                                              *
 *        Licensed from Digital Equipment Corporation           *
 *                       Copyright (c)                          *
 *               Digital Equipment Corporation                  *
 *                   Maynard, Massachusetts                     *
 *                         1985, 1986                           *
 *                    All rights reserved.                      *
 *                                                              *
 *        The Information in this software is subject to change *
 *   without notice and should not be construed as a commitment *
 *   by  Digital  Equipment  Corporation.   Digital   makes  no *
 *   representations about the suitability of this software for *
 *   any purpose.  It is supplied "As Is" without expressed  or *
 *   implied  warranty.                                         *
 *                                                              *
 *        If the Regents of the University of California or its *
 *   licensees modify the software in a manner creating         *
 *   derivative copyright rights, appropriate copyright         *
 *   legends may be placed on  the derivative work in addition  *
 *   to that set forth above.                                   *
 ****************************************************************/

/*
 * Console RL02 status of current transfer (read only)
 */
#define CRL_S_XCMPLT	1		/* transaction complete */
#define CRL_S_XCONT	2		/* continue transaction */
#define CRL_S_ABORT	3		/* transation abort */
#define CRL_S_RETSTS	4		/* return device status */
#define CRL_S_HNDSHK	0x80		/* handshake err during transaction */
#define CRL_S_HWERR	0x81		/* hardware err during transaction */

/*
 * Console RL02 function codes
 */
#define CRL_F_NOOP	0		/* No operation */
#define CRL_F_RSTSTS	2		/* reset and return device status */
#define CRL_F_ABORT	3		/* abort transfer */
#define CRL_F_RETSTS	4		/* read device status */
#define CRL_F_WRITE	5		/* write block data */
#define CRL_F_READ	6		/* read block data */

/*
 * Console sectoring information.
 * The console understands the rl02 as having 512 byte sectors.
 */
#define	CRLBYSEC 512			/* bytes/sector */
#define	MAXSEC 20480		 	/* sectors/rl02 */

/*
 * STXCS bit definitions
 */
#define STXCS_RDY	0x00000080	/* ready bit */
#define STXCS_IE	0x00000040	/* interrupt enable */

#define	CRLERRS		5	/* number of retries before quitting */

/*
 * The state byte is used to retain exclusivity,
 * and contains the busy flag.
 */
#define	CRL_IDLE	0
#define	CRL_OPEN	1
#define	CRL_BUSY	2


#define	CRLDS_BITS \
"\20\20WDE\17CHE\16WL\15SKTO\14SPE\13WGE\12VC\11DSE\
\10DT\7HS\6CO\5HO\4BH\3STC\2STB\1STA"

#define	CRLCS_BITS \
"\20\20CE\17DE\16NXM\15DLT\14DCRC\13OPI\1DRDY"