Annotation of sys/arch/vax/uba/ubareg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: ubareg.h,v 1.11 2003/11/10 21:05:06 miod Exp $ */
! 2: /* $NetBSD: ubareg.h,v 1.11 2000/01/24 02:40:36 matt Exp $ */
! 3:
! 4: /*-
! 5: * Copyright (c) 1982, 1986 The Regents of the University of California.
! 6: * All rights reserved.
! 7: * (c) UNIX System Laboratories, Inc.
! 8: * All or some portions of this file are derived from material licensed
! 9: * to the University of California by American Telephone and Telegraph
! 10: * Co. or Unix System Laboratories, Inc. and are reproduced herein with
! 11: * the permission of UNIX System Laboratories, Inc.
! 12: *
! 13: * Redistribution and use in source and binary forms, with or without
! 14: * modification, are permitted provided that the following conditions
! 15: * are met:
! 16: * 1. Redistributions of source code must retain the above copyright
! 17: * notice, this list of conditions and the following disclaimer.
! 18: * 2. Redistributions in binary form must reproduce the above copyright
! 19: * notice, this list of conditions and the following disclaimer in the
! 20: * documentation and/or other materials provided with the distribution.
! 21: * 3. Neither the name of the University nor the names of its contributors
! 22: * may be used to endorse or promote products derived from this software
! 23: * without specific prior written permission.
! 24: *
! 25: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
! 26: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
! 27: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
! 28: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
! 29: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
! 30: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
! 31: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
! 32: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
! 33: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
! 34: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
! 35: * SUCH DAMAGE.
! 36: *
! 37: * @(#)ubareg.h 7.8 (Berkeley) 5/9/91
! 38: */
! 39:
! 40: /*
! 41: * VAX UNIBUS adapter registers
! 42: */
! 43:
! 44: /*
! 45: * "UNIBUS" adaptor types.
! 46: * This code is used for both UNIBUSes and Q-buses
! 47: * with different types of adaptors.
! 48: * Definition of a type includes support code for that type.
! 49: */
! 50:
! 51: #if VAX780 || VAX8600
! 52: #define DW780 1 /* has adaptor regs, sr: 780/785/8600 */
! 53: #else
! 54: #undef DW780
! 55: #endif
! 56:
! 57:
! 58: #if VAX750
! 59: #define DW750 2 /* has adaptor regs, no sr: 750, 730 */
! 60: #endif
! 61:
! 62: #if VAX730
! 63: #define DW730 3 /* has adaptor regs, no sr: 750, 730 */
! 64: #endif
! 65:
! 66: #if VAX630 || VAX650 || VAX660 || VAX670
! 67: #define QBA 4 /* 22-bit Q-bus, no adaptor regs: uVAX II */
! 68: #endif
! 69:
! 70: /*
! 71: * Size of unibus memory address space in pages
! 72: * (also number of map registers).
! 73: * QBAPAGES should be 8192, but we don't need nearly that much
! 74: * address space, and the return from the allocation routine
! 75: * can accommodate at most 2047 (ubavar.h: UBA_MAXMR);
! 76: * QBAPAGES must be at least UBAPAGES. Choose pragmatically.
! 77: *
! 78: * Is there ever any need to have QBAPAGES != UBAPAGES???
! 79: * Wont work now anyway, QBAPAGES _must_ be .eq. UBAPAGES.
! 80: */
! 81: #define UBAPAGES 496
! 82: #define NUBMREG 496
! 83: #define QBAPAGES 1024
! 84: #define UBAIOADDR 0760000 /* start of I/O page */
! 85: #define UBAIOPAGES 16
! 86:
! 87: #ifndef _LOCORE
! 88: /*
! 89: * DW780/DW750 hardware registers
! 90: */
! 91: struct uba_regs {
! 92: int uba_cnfgr; /* configuration register */
! 93: int uba_cr; /* control register */
! 94: int uba_sr; /* status register */
! 95: int uba_dcr; /* diagnostic control register */
! 96: int uba_fmer; /* failed map entry register */
! 97: int uba_fubar; /* failed UNIBUS address register */
! 98: int pad1[2];
! 99: int uba_brsvr[4];
! 100: int uba_brrvr[4]; /* receive vector registers */
! 101: int uba_dpr[16]; /* buffered data path register */
! 102: int pad2[480];
! 103: pt_entry_t uba_map[UBAPAGES]; /* unibus map register */
! 104: int pad3[UBAIOPAGES]; /* no maps for device address space */
! 105: };
! 106: #endif
! 107:
! 108: #ifdef DW780
! 109: /* uba_cnfgr */
! 110: #define UBACNFGR_UBINIT 0x00040000 /* unibus init asserted */
! 111: #define UBACNFGR_UBPDN 0x00020000 /* unibus power down */
! 112: #define UBACNFGR_UBIC 0x00010000 /* unibus init complete */
! 113:
! 114: #define UBACNFGR_BITS \
! 115: "\40\40PARFLT\37WSQFLT\36URDFLT\35ISQFLT\34MXTFLT\33XMTFLT\30ADPDN\27ADPUP\23UBINIT\22UBPDN\21UBIC"
! 116:
! 117: /* uba_cr */
! 118: #define UBACR_MRD16 0x40000000 /* map reg disable bit 4 */
! 119: #define UBACR_MRD8 0x20000000 /* map reg disable bit 3 */
! 120: #define UBACR_MRD4 0x10000000 /* map reg disable bit 2 */
! 121: #define UBACR_MRD2 0x08000000 /* map reg disable bit 1 */
! 122: #define UBACR_MRD1 0x04000000 /* map reg disable bit 0 */
! 123: #define UBACR_IFS 0x00000040 /* interrupt field switch */
! 124: #define UBACR_BRIE 0x00000020 /* BR interrupt enable */
! 125: #define UBACR_USEFIE 0x00000010 /* UNIBUS to SBI error field IE */
! 126: #define UBACR_SUEFIE 0x00000008 /* SBI to UNIBUS error field IE */
! 127: #define UBACR_CNFIE 0x00000004 /* configuration IE */
! 128: #define UBACR_UPF 0x00000002 /* UNIBUS power fail */
! 129: #define UBACR_ADINIT 0x00000001 /* adapter init */
! 130:
! 131: /* uba_sr */
! 132: #define UBASR_BR7FULL 0x08000000 /* BR7 receive vector reg full */
! 133: #define UBASR_BR6FULL 0x04000000 /* BR6 receive vector reg full */
! 134: #define UBASR_BR5FULL 0x02000000 /* BR5 receive vector reg full */
! 135: #define UBASR_BR4FULL 0x01000000 /* BR4 receive vector reg full */
! 136: #define UBASR_RDTO 0x00000400 /* UNIBUS to SBI read data timeout */
! 137: #define UBASR_RDS 0x00000200 /* read data substitute */
! 138: #define UBASR_CRD 0x00000100 /* corrected read data */
! 139: #define UBASR_CXTER 0x00000080 /* command transmit error */
! 140: #define UBASR_CXTMO 0x00000040 /* command transmit timeout */
! 141: #define UBASR_DPPE 0x00000020 /* data path parity error */
! 142: #define UBASR_IVMR 0x00000010 /* invalid map register */
! 143: #define UBASR_MRPF 0x00000008 /* map register parity failure */
! 144: #define UBASR_LEB 0x00000004 /* lost error */
! 145: #define UBASR_UBSTO 0x00000002 /* UNIBUS select timeout */
! 146: #define UBASR_UBSSYNTO 0x00000001 /* UNIBUS slave sync timeout */
! 147:
! 148: #define UBASR_BITS \
! 149: "\20\13RDTO\12RDS\11CRD\10CXTER\7CXTMO\6DPPE\5IVMR\4MRPF\3LEB\2UBSTO\1UBSSYNTO"
! 150:
! 151: /* uba_brrvr[] */
! 152: #define UBABRRVR_AIRI 0x80000000 /* adapter interrupt request */
! 153: #define UBABRRVR_DIV 0x0000ffff /* device interrupt vector field */
! 154: #endif
! 155:
! 156: /* uba_dpr */
! 157: #ifdef DW780
! 158: #define UBADPR_BNE 0x80000000 /* buffer not empty - purge */
! 159: #define UBADPR_BTE 0x40000000 /* buffer transfer error */
! 160: #define UBADPR_DPF 0x20000000 /* DP function (RO) */
! 161: #define UBADPR_BS 0x007f0000 /* buffer state field */
! 162: #define UBADPR_BUBA 0x0000ffff /* buffered UNIBUS address */
! 163: #endif
! 164: #ifdef DW750
! 165: #define UBADPR_ERROR 0x80000000 /* error occurred */
! 166: #define UBADPR_NXM 0x40000000 /* nxm from memory */
! 167: #define UBADPR_UCE 0x20000000 /* uncorrectable error */
! 168: #define UBADPR_PURGE 0x00000001 /* purge bdp */
! 169: #endif
! 170:
! 171: /* uba_mr[] */
! 172: #define UBAMR_MRV 0x80000000 /* map register valid */
! 173: #define UBAMR_BO 0x02000000 /* byte offset bit */
! 174: #define UBAMR_DPDB 0x01e00000 /* data path designator field */
! 175: #define UBAMR_SBIPFN 0x001fffff /* SBI page address field */
! 176:
! 177: #define UBAMR_DPSHIFT 21 /* shift to data path designator */
! 178:
! 179: /*
! 180: * Number of unibus buffered data paths and possible uba's per cpu type.
! 181: */
! 182: #define NBDP8600 15
! 183: #define NBDP780 15
! 184: #define NBDPBUA 5
! 185: #define NBDP750 3
! 186: #define NBDP730 0
! 187: #define MAXNBDP 15
! 188:
! 189: /*
! 190: * Symbolic BUS addresses for UBAs.
! 191: */
! 192:
! 193: #if VAX630 || VAX650
! 194: #define QBAMAP 0x20088000
! 195: #define QMEM 0x30000000
! 196: #define QIOPAGE 0x20000000
! 197: /*
! 198: * Q-bus control registers
! 199: */
! 200: #define QIPCR 0x1f40 /* from start of iopage */
! 201: /* bits in QIPCR */
! 202: #define Q_DBIRQ 0x0001 /* doorbell interrupt request */
! 203: #define Q_LMEAE 0x0020 /* local mem external access enable */
! 204: #define Q_DBIIE 0x0040 /* doorbell interrupt enable */
! 205: #define Q_AUXHLT 0x0100 /* auxiliary processor halt */
! 206: #define Q_DMAQPE 0x8000 /* Q22 bus address space parity error */
! 207: #endif
! 208:
! 209: #if VAX730
! 210: #define UMEM730 0xfc0000
! 211: #endif
! 212:
! 213: #if VAX750
! 214: #define UMEM750(i) (0xfc0000-(i)*0x40000)
! 215: #endif
! 216:
! 217: #if VAX780
! 218: #define UMEM780(i) (0x20100000+(i)*0x40000)
! 219: #endif
! 220:
! 221: #if VAX8200 /* BEWARE, argument is node, not ubanum */
! 222: #define UMEM8200(i) (0x20400000+(i)*0x40000)
! 223: #endif
! 224:
! 225: #if VAX8600 || VAX780
! 226: #define UMEMA8600(i) (0x20100000+(i)*0x40000)
! 227: #define UMEMB8600(i) (0x22100000+(i)*0x40000)
! 228: #endif
! 229:
! 230: /*
! 231: * Macro to offset a UNIBUS device address, often expressed as
! 232: * something like 0172520, by forcing it into the last 8K
! 233: * of UNIBUS memory space.
! 234: */
! 235: #define ubdevreg(addr) ((addr) & 017777)
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