Annotation of sys/arch/vax/qbus/uda.c, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: uda.c,v 1.6 2005/11/12 03:44:24 pedro Exp $ */
2: /* $NetBSD: uda.c,v 1.36 2000/06/04 06:17:05 matt Exp $ */
3: /*
4: * Copyright (c) 1996 Ludd, University of Lule}, Sweden.
5: * Copyright (c) 1988 Regents of the University of California.
6: * All rights reserved.
7: *
8: * This code is derived from software contributed to Berkeley by
9: * Chris Torek.
10: *
11: * Redistribution and use in source and binary forms, with or without
12: * modification, are permitted provided that the following conditions
13: * are met:
14: * 1. Redistributions of source code must retain the above copyright
15: * notice, this list of conditions and the following disclaimer.
16: * 2. Redistributions in binary form must reproduce the above copyright
17: * notice, this list of conditions and the following disclaimer in the
18: * documentation and/or other materials provided with the distribution.
19: * 3. Neither the name of the University nor the names of its contributors
20: * may be used to endorse or promote products derived from this software
21: * without specific prior written permission.
22: *
23: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
24: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
27: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33: * SUCH DAMAGE.
34: *
35: * @(#)uda.c 7.32 (Berkeley) 2/13/91
36: */
37:
38: /*
39: * UDA50 disk device driver
40: */
41:
42: #include <sys/param.h>
43: #include <sys/kernel.h>
44: #include <sys/systm.h>
45: #include <sys/device.h>
46: #include <sys/buf.h>
47: #include <sys/malloc.h>
48:
49: #include <machine/bus.h>
50: #include <machine/sid.h>
51:
52: #include <arch/vax/qbus/ubavar.h>
53: #include <arch/vax/mscp/mscp.h>
54: #include <arch/vax/mscp/mscpreg.h>
55: #include <arch/vax/mscp/mscpvar.h>
56:
57: /*
58: * Software status, per controller.
59: */
60: struct uda_softc {
61: struct device sc_dev; /* Autoconfig info */
62: struct evcount sc_intrcnt; /* Interrupt counting */
63: int sc_cvec;
64: struct uba_unit sc_unit; /* Struct common for UBA to communicate */
65: struct mscp_pack *sc_uuda; /* Unibus address of uda struct */
66: struct mscp_pack sc_uda; /* Struct for uda communication */
67: bus_dma_tag_t sc_dmat;
68: bus_space_tag_t sc_iot;
69: bus_space_handle_t sc_iph;
70: bus_space_handle_t sc_sah;
71: bus_dmamap_t sc_cmap;/* Control structures */
72: struct mscp *sc_mscp; /* Keep pointer to active mscp */
73: struct mscp_softc *sc_softc; /* MSCP info (per mscpvar.h) */
74: int sc_wticks; /* watchdog timer ticks */
75: int sc_inq;
76: };
77:
78: static int udamatch(struct device *, struct cfdata *, void *);
79: static void udaattach(struct device *, struct device *, void *);
80: static void udareset(struct device *);
81: static void udaintr(void *);
82: int udaready(struct uba_unit *);
83: void udactlrdone(struct device *);
84: int udaprint(void *, const char *);
85: void udasaerror(struct device *, int);
86: void udago(struct device *, struct mscp_xi *);
87:
88: struct cfattach mtc_ca = {
89: sizeof(struct uda_softc), (cfmatch_t)udamatch, udaattach
90: };
91:
92: struct cfdriver mtc_cd = {
93: NULL, "mtc", DV_TAPE
94: };
95:
96: struct cfattach uda_ca = {
97: sizeof(struct uda_softc), (cfmatch_t)udamatch, udaattach
98: };
99:
100: struct cfdriver uda_cd = {
101: NULL, "uda", DV_DISK
102: };
103:
104: /*
105: * More driver definitions, for generic MSCP code.
106: */
107: struct mscp_ctlr uda_mscp_ctlr = {
108: udactlrdone,
109: udago,
110: udasaerror,
111: };
112:
113: /*
114: * Miscellaneous private variables.
115: */
116: static int ivec_no;
117:
118: int
119: udaprint(aux, name)
120: void *aux;
121: const char *name;
122: {
123: if (name)
124: printf("%s: mscpbus", name);
125: return UNCONF;
126: }
127:
128: /*
129: * Poke at a supposed UDA50 to see if it is there.
130: */
131: int
132: udamatch(parent, cf, aux)
133: struct device *parent;
134: struct cfdata *cf;
135: void *aux;
136: {
137: struct uba_attach_args *ua = aux;
138: struct mscp_softc mi; /* Nice hack */
139: struct uba_softc *ubasc;
140: int tries;
141:
142: /* Get an interrupt vector. */
143: ubasc = (void *)parent;
144: ivec_no = ubasc->uh_lastiv - 4;
145:
146: mi.mi_iot = ua->ua_iot;
147: mi.mi_iph = ua->ua_ioh;
148: mi.mi_sah = ua->ua_ioh + 2;
149: mi.mi_swh = ua->ua_ioh + 2;
150:
151: /*
152: * Initialise the controller (partially). The UDA50 programmer's
153: * manual states that if initialisation fails, it should be retried
154: * at least once, but after a second failure the port should be
155: * considered `down'; it also mentions that the controller should
156: * initialise within ten seconds. Or so I hear; I have not seen
157: * this manual myself.
158: */
159: tries = 0;
160: again:
161:
162: bus_space_write_2(mi.mi_iot, mi.mi_iph, 0, 0); /* Start init */
163: if (mscp_waitstep(&mi, MP_STEP1, MP_STEP1) == 0)
164: return 0; /* Nothing here... */
165:
166: bus_space_write_2(mi.mi_iot, mi.mi_sah, 0,
167: MP_ERR | (NCMDL2 << 11) | (NRSPL2 << 8) | MP_IE | (ivec_no >> 2));
168:
169: if (mscp_waitstep(&mi, MP_STEP2, MP_STEP2) == 0) {
170: printf("udaprobe: init step2 no change. sa=%x\n",
171: bus_space_read_2(mi.mi_iot, mi.mi_sah, 0));
172: goto bad;
173: }
174:
175: /* should have interrupted by now */
176: return 1;
177: bad:
178: if (++tries < 2)
179: goto again;
180: return 0;
181: }
182:
183: void
184: udaattach(parent, self, aux)
185: struct device *parent, *self;
186: void *aux;
187: {
188: struct uda_softc *sc = (void *)self;
189: struct uba_attach_args *ua = aux;
190: struct uba_softc *uh = (void *)parent;
191: struct mscp_attach_args ma;
192: int ctlr, error, rseg;
193: bus_dma_segment_t seg;
194:
195: printf("\n");
196:
197: uh->uh_lastiv -= 4; /* remove dynamic interrupt vector */
198:
199: uba_intr_establish(ua->ua_icookie, ua->ua_cvec,
200: udaintr, sc, &sc->sc_intrcnt);
201: uba_reset_establish(udareset, &sc->sc_dev);
202: sc->sc_cvec = ua->ua_cvec;
203: evcount_attach(&sc->sc_intrcnt, sc->sc_dev.dv_xname,
204: (void *)&sc->sc_cvec, &evcount_intr);
205:
206: sc->sc_iot = ua->ua_iot;
207: sc->sc_iph = ua->ua_ioh;
208: sc->sc_sah = ua->ua_ioh + 2;
209: sc->sc_dmat = ua->ua_dmat;
210: ctlr = sc->sc_dev.dv_unit;
211:
212: /*
213: * Fill in the uba_unit struct, so we can communicate with the uba.
214: */
215: sc->sc_unit.uu_softc = sc; /* Backpointer to softc */
216: sc->sc_unit.uu_ready = udaready;/* go routine called from adapter */
217: sc->sc_unit.uu_keepbdp = vax_cputype == VAX_750 ? 1 : 0;
218:
219: /*
220: * Map the communication area and command and
221: * response packets into Unibus space.
222: */
223: if ((error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct mscp_pack),
224: NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
225: printf("Alloc ctrl area %d\n", error);
226: return;
227: }
228: if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
229: sizeof(struct mscp_pack), (caddr_t *) &sc->sc_uda,
230: BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
231: printf("Map ctrl area %d\n", error);
232: err: bus_dmamem_free(sc->sc_dmat, &seg, rseg);
233: return;
234: }
235: if ((error = bus_dmamap_create(sc->sc_dmat, sizeof(struct mscp_pack),
236: 1, sizeof(struct mscp_pack), 0, BUS_DMA_NOWAIT, &sc->sc_cmap))) {
237: printf("Create DMA map %d\n", error);
238: err2: bus_dmamem_unmap(sc->sc_dmat, (caddr_t)&sc->sc_uda,
239: sizeof(struct mscp_pack));
240: goto err;
241: }
242: if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmap,
243: &sc->sc_uda, sizeof(struct mscp_pack), 0, BUS_DMA_NOWAIT))) {
244: printf("Load ctrl map %d\n", error);
245: bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmap);
246: goto err2;
247: }
248:
249: bzero(&sc->sc_uda, sizeof (struct mscp_pack));
250:
251: /*
252: * The only thing that differ UDA's and Tape ctlr's is
253: * their vcid. Beacuse there are no way to determine which
254: * ctlr type it is, we check what is generated and later
255: * set the correct vcid.
256: */
257: ma.ma_type = (strcmp(self->dv_cfdata->cf_driver->cd_name,
258: mtc_cd.cd_name) ? MSCPBUS_DISK : MSCPBUS_TAPE);
259:
260: ma.ma_mc = &uda_mscp_ctlr;
261: ma.ma_type |= MSCPBUS_UDA;
262: ma.ma_uda = &sc->sc_uda;
263: ma.ma_softc = &sc->sc_softc;
264: ma.ma_iot = sc->sc_iot;
265: ma.ma_iph = sc->sc_iph;
266: ma.ma_sah = sc->sc_sah;
267: ma.ma_swh = sc->sc_sah;
268: ma.ma_dmat = sc->sc_dmat;
269: ma.ma_dmam = sc->sc_cmap;
270: ma.ma_ivec = ivec_no;
271: ma.ma_ctlrnr = (ua->ua_iaddr == 0172150 ? 0 : 1); /* XXX */
272: ma.ma_adapnr = uh->uh_nr;
273: config_found(&sc->sc_dev, &ma, udaprint);
274: }
275:
276: /*
277: * Start a transfer if there are free resources available, otherwise
278: * let it go in udaready, forget it for now.
279: * Called from mscp routines.
280: */
281: void
282: udago(usc, mxi)
283: struct device *usc;
284: struct mscp_xi *mxi;
285: {
286: struct uda_softc *sc = (void *)usc;
287: struct uba_unit *uu;
288: struct buf *bp = mxi->mxi_bp;
289: int err;
290:
291: /*
292: * If we already have transfers queued, don't try to load
293: * the map again.
294: */
295: if (sc->sc_inq == 0) {
296: err = bus_dmamap_load(sc->sc_dmat, mxi->mxi_dmam, bp->b_data,
297: bp->b_bcount, (bp->b_flags & B_PHYS ? bp->b_proc : NULL),
298: BUS_DMA_NOWAIT);
299: if (err == 0) {
300: mscp_dgo(sc->sc_softc, mxi);
301: return;
302: }
303: }
304: uu = malloc(sizeof(struct uba_unit), M_DEVBUF, M_NOWAIT);
305: if (uu == 0)
306: panic("udago: no mem");
307: uu->uu_ready = udaready;
308: uu->uu_softc = sc;
309: uu->uu_ref = mxi;
310: uba_enqueue(uu);
311: sc->sc_inq++;
312: }
313:
314: /*
315: * Called if we have been blocked for resources, and resources
316: * have been freed again. Return 1 if we could start all
317: * transfers again, 0 if we still are waiting.
318: * Called from uba resource free routines.
319: */
320: int
321: udaready(uu)
322: struct uba_unit *uu;
323: {
324: struct uda_softc *sc = uu->uu_softc;
325: struct mscp_xi *mxi = uu->uu_ref;
326: struct buf *bp = mxi->mxi_bp;
327: int err;
328:
329: err = bus_dmamap_load(sc->sc_dmat, mxi->mxi_dmam, bp->b_data,
330: bp->b_bcount, (bp->b_flags & B_PHYS ? bp->b_proc : NULL),
331: BUS_DMA_NOWAIT);
332: if (err)
333: return 0;
334: mscp_dgo(sc->sc_softc, mxi);
335: sc->sc_inq--;
336: free(uu, M_DEVBUF);
337: return 1;
338: }
339:
340: static struct saerr {
341: int code; /* error code (including UDA_ERR) */
342: char *desc; /* what it means: Efoo => foo error */
343: } saerr[] = {
344: { 0100001, "Eunibus packet read" },
345: { 0100002, "Eunibus packet write" },
346: { 0100003, "EUDA ROM and RAM parity" },
347: { 0100004, "EUDA RAM parity" },
348: { 0100005, "EUDA ROM parity" },
349: { 0100006, "Eunibus ring read" },
350: { 0100007, "Eunibus ring write" },
351: { 0100010, " unibus interrupt master failure" },
352: { 0100011, "Ehost access timeout" },
353: { 0100012, " host exceeded command limit" },
354: { 0100013, " unibus bus master failure" },
355: { 0100014, " DM XFC fatal error" },
356: { 0100015, " hardware timeout of instruction loop" },
357: { 0100016, " invalid virtual circuit id" },
358: { 0100017, "Eunibus interrupt write" },
359: { 0104000, "Efatal sequence" },
360: { 0104040, " D proc ALU" },
361: { 0104041, "ED proc control ROM parity" },
362: { 0105102, "ED proc w/no BD#2 or RAM parity" },
363: { 0105105, "ED proc RAM buffer" },
364: { 0105152, "ED proc SDI" },
365: { 0105153, "ED proc write mode wrap serdes" },
366: { 0105154, "ED proc read mode serdes, RSGEN & ECC" },
367: { 0106040, "EU proc ALU" },
368: { 0106041, "EU proc control reg" },
369: { 0106042, " U proc DFAIL/cntl ROM parity/BD #1 test CNT" },
370: { 0106047, " U proc const PROM err w/D proc running SDI test" },
371: { 0106055, " unexpected trap" },
372: { 0106071, "EU proc const PROM" },
373: { 0106072, "EU proc control ROM parity" },
374: { 0106200, "Estep 1 data" },
375: { 0107103, "EU proc RAM parity" },
376: { 0107107, "EU proc RAM buffer" },
377: { 0107115, " test count wrong (BD 12)" },
378: { 0112300, "Estep 2" },
379: { 0122240, "ENPR" },
380: { 0122300, "Estep 3" },
381: { 0142300, "Estep 4" },
382: { 0, " unknown error code" }
383: };
384:
385: /*
386: * If the error bit was set in the controller status register, gripe,
387: * then (optionally) reset the controller and requeue pending transfers.
388: */
389: void
390: udasaerror(usc, doreset)
391: struct device *usc;
392: int doreset;
393: {
394: struct uda_softc *sc = (void *)usc;
395: int code = bus_space_read_2(sc->sc_iot, sc->sc_sah, 0);
396: struct saerr *e;
397:
398: if ((code & MP_ERR) == 0)
399: return;
400: for (e = saerr; e->code; e++)
401: if (e->code == code)
402: break;
403: printf("%s: controller error, sa=0%o (%s%s)\n",
404: sc->sc_dev.dv_xname, code, e->desc + 1,
405: *e->desc == 'E' ? " error" : "");
406: #if 0 /* XXX we just avoid panic when autoconfig non-existent KFQSA devices */
407: if (doreset) {
408: mscp_requeue(sc->sc_softc);
409: /* (void) udainit(sc); XXX */
410: }
411: #endif
412: }
413:
414: /*
415: * Interrupt routine. Depending on the state of the controller,
416: * continue initialisation, or acknowledge command and response
417: * interrupts, and process responses.
418: */
419: static void
420: udaintr(arg)
421: void *arg;
422: {
423: struct uda_softc *sc = arg;
424: struct uba_softc *uh;
425: struct mscp_pack *ud;
426:
427: sc->sc_wticks = 0; /* reset interrupt watchdog */
428:
429: /* ctlr fatal error */
430: if (bus_space_read_2(sc->sc_iot, sc->sc_sah, 0) & MP_ERR) {
431: udasaerror(&sc->sc_dev, 1);
432: return;
433: }
434: ud = &sc->sc_uda;
435: /*
436: * Handle buffer purge requests.
437: * XXX - should be done in bus_dma_sync().
438: */
439: uh = (void *)sc->sc_dev.dv_parent;
440: if (ud->mp_ca.ca_bdp) {
441: if (uh->uh_ubapurge)
442: (*uh->uh_ubapurge)(uh, ud->mp_ca.ca_bdp);
443: ud->mp_ca.ca_bdp = 0;
444: /* signal purge complete */
445: bus_space_write_2(sc->sc_iot, sc->sc_sah, 0, 0);
446: }
447:
448: mscp_intr(sc->sc_softc);
449: }
450:
451: /*
452: * A Unibus reset has occurred on UBA uban. Reinitialise the controller(s)
453: * on that Unibus, and requeue outstanding I/O.
454: */
455: static void
456: udareset(struct device *dev)
457: {
458: struct uda_softc *sc = (void *)dev;
459: /*
460: * Our BDP (if any) is gone; our command (if any) is
461: * flushed; the device is no longer mapped; and the
462: * UDA50 is not yet initialised.
463: */
464: if (sc->sc_unit.uu_bdp) {
465: /* printf("<%d>", UBAI_BDP(sc->sc_unit.uu_bdp)); */
466: sc->sc_unit.uu_bdp = 0;
467: }
468:
469: /* reset queues and requeue pending transfers */
470: mscp_requeue(sc->sc_softc);
471:
472: /*
473: * If it fails to initialise we will notice later and
474: * try again (and again...). Do not call udastart()
475: * here; it will be done after the controller finishes
476: * initialisation.
477: */
478: /* XXX if (udainit(sc)) */
479: printf(" (hung)");
480: }
481:
482: void
483: udactlrdone(usc)
484: struct device *usc;
485: {
486: struct uda_softc *sc = (void *)usc;
487:
488: uba_done((struct uba_softc *)sc->sc_dev.dv_parent);
489: }
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