Annotation of sys/arch/vax/qbus/qdreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: qdreg.h,v 1.5 2007/05/25 21:27:15 krw Exp $ */
2: /* $NetBSD: qdreg.h,v 1.1 1998/03/21 10:02:39 ragge Exp $ */
3: /*-
4: * Copyright (c) 1982, 1986 The Regents of the University of California.
5: * All rights reserved.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: * 3. Neither the name of the University nor the names of its contributors
16: * may be used to endorse or promote products derived from this software
17: * without specific prior written permission.
18: *
19: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
20: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
23: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29: * SUCH DAMAGE.
30: *
31: * @(#)qdreg.h 7.1 (Berkeley) 5/9/91
32: */
33:
34: /************************************************************************
35: * *
36: * Copyright (c) 1985, 1986 by *
37: * Digital Equipment Corporation, Maynard, MA *
38: * All rights reserved. *
39: * *
40: * This software is furnished under a license and may be used and *
41: * copied only in accordance with the terms of such license and *
42: * with the inclusion of the above copyright notice. This *
43: * software or any other copies thereof may not be provided or *
44: * otherwise made available to any other person. No title to and *
45: * ownership of the software is hereby transferred. *
46: * *
47: * The information in this software is subject to change without *
48: * notice and should not be construed as a commitment by Digital *
49: * Equipment Corporation. *
50: * *
51: * Digital assumes no responsibility for the use or reliability *
52: * of its software on equipment which is not supplied by Digital. *
53: * *
54: ************************************************************************/
55:
56: /* Dragon ADDER reg map */
57: /* ADDER register bit definitions */
58: /* Y_SCROLL_CONSTANT */
59:
60: #define SCROLL_ERASE 0x2000
61: #define ADDER_SCROLL_DOWN 0x1000
62:
63: /* ADDER status and interrupt enable registers [1], [2], [3] */
64:
65: #define DISABLE 0x0000
66: #define PAUSE_COMPLETE 0x0001
67: #define FRAME_SYNC 0x0002
68: #define INIT_COMPLETE 0x0004
69: #define RASTEROP_COMPLETE 0x0008
70:
71: #define ADDRESS_COMPLETE 0x0010
72: #define RX_READY 0x0020
73: #define TX_READY 0x0040
74: #define ID_SCROLL_READY 0x0080
75:
76: #define TOP_CLIP 0x0100
77: #define BOTTOM_CLIP 0x0200
78: #define LEFT_CLIP 0x0400
79: #define RIGHT_CLIP 0x0800
80: #define NO_CLIP 0x1000
81: #define VSYNC 0x2000
82:
83: /* ADDER command register [8], [10] */
84:
85: #define OCR_zero 0x0000
86: #define Z_BLOCK0 0x0000
87: #define OCRA 0x0000
88: #define OCRB 0x0004
89: #define RASTEROP 0x02c0
90: #define PBT 0x03c0
91: #define BTPZ 0x0bb0
92: #define PTBZ 0x07a0
93: #define DTE 0x0400
94: #define S1E 0x0800
95: #define S2E 0x1000
96: #define VIPER_Z_LOAD 0x01A0
97: #define ID_LOAD 0x0100
98: #define CANCEL 0x0000
99: #define LF_R1 0x0000
100: #define LF_R2 0x0010
101: #define LF_R3 0x0020
102: #define LF_R4 0x0030
103:
104: /* ADDER rasterop mode register [9] */
105:
106: #define NORMAL 0x0000
107: #define LINEAR_PATTERN 0x0002
108: #define X_FILL 0x0003
109: #define Y_FILL 0x0007
110: #define BASELINE 0x0008
111: #define HOLE_ENABLE 0x0010
112: #define SRC_1_INDEX_ENABLE 0x0020
113: #define DST_INDEX_ENABLE 0x0040
114: #define DST_WRITE_ENABLE 0x0080
115:
116: /* ADDER source 2 size register */
117:
118: #define NO_TILE 0x0080
119:
120: /* External registers base addresses */
121:
122: #define CS_UPDATE_MASK 0x0060
123: #define CS_SCROLL_MASK 0x0040
124:
125: /* VIPER registers */
126:
127: #define RESOLUTION_MODE 0x0080
128: #define MEMORY_BUS_WIDTH 0x0081
129: #define PLANE_ADDRESS 0x0083
130: #define LU_FUNCTION_R1 0x0084
131: #define LU_FUNCTION_R2 0x0085
132: #define LU_FUNCTION_R3 0x0086
133: #define LU_FUNCTION_R4 0x0087
134: #define MASK_1 0x0088
135: #define MASK_2 0x0089
136: #define SOURCE 0x008a
137: #define SOURCE_Z 0x0000
138: #define BACKGROUND_COLOR 0x008e
139: #define BACKGROUND_COLOR_Z 0x000C
140: #define FOREGROUND_COLOR 0x008f
141: #define FOREGROUND_COLOR_Z 0x0004
142: #define SRC1_OCR_A 0x0090
143: #define SRC2_OCR_A 0x0091
144: #define DST_OCR_A 0x0092
145: #define SRC1_OCR_B 0x0094
146: #define SRC2_OCR_B 0x0095
147: #define DST_OCR_B 0x0096
148:
149: /* VIPER scroll registers */
150:
151: #define SCROLL_CONSTANT 0x0082
152: #define SCROLL_FILL 0x008b
153: #define SCROLL_FILL_Z 0x0008
154: #define LEFT_SCROLL_MASK 0x008c
155: #define RIGHT_SCROLL_MASK 0x008d
156:
157: /* VIPER register bit definitions */
158:
159: #define EXT_NONE 0x0000
160: #define EXT_SOURCE 0x0001
161: #define EXT_M1_M2 0x0002
162: #define INT_NONE 0x0000
163: #define INT_SOURCE 0x0004
164: #define INT_M1_M2 0x0008
165: #define ID 0x0010
166: #define NO_ID 0x0000
167: #define WAIT 0x0020
168: #define NO_WAIT 0x0000
169: #define BAR_SHIFT_DELAY WAIT
170: #define NO_BAR_SHIFT_DELAY NO_WAIT
171:
172:
173: /* VIPER logical function unit codes */
174:
175: #define LF_ZEROS 0x0000
176: #define LF_NOT_D 0x0003
177: #define LF_D_XOR_S 0x0006
178: #define LF_D 0x000c
179: #define LF_SOURCE 0x000a
180: #define LF_D_OR_S 0x000d
181: #define LF_ONES 0x000f
182: #define INV_M1_M2 0x0030
183: #define FULL_SRC_RESOLUTION 0X00C0 /* makes second pass like first pass */
184:
185: /* VIPER scroll register [2] */
186:
187: #define SCROLL_DISABLE 0x0040
188: #define SCROLL_ENABLE 0x0020
189: #define VIPER_LEFT 0x0000
190: #define VIPER_RIGHT 0x0010
191: #define VIPER_UP 0x0040
192: #define VIPER_DOWN 0x0000
193:
194: /* Adder scroll register */
195:
196: #define ADDER_UP 0x0000
197: #define ADDER_DOWN 0x1000
198:
199: /* Misc scroll definitions */
200:
201: #define UP 0
202: #define DOWN 1
203: #define LEFT 2
204: #define RIGHT 3
205: #define NODIR 4
206: #define SCROLL_VMAX 31
207: #define SCROLL_HMAX 15
208: #define NEW 2
209: #define OLD 1
210: #define BUSY 1
211: #define DRAG 1
212: #define SCROLL 0
213:
214: /* miscellaneous defines */
215:
216: #define ALL_PLANES 0xffffffff
217: #define UNITY 0x1fff /* Adder scale factor */
218: #define MAX_SCREEN_X 1024
219: #define MAX_SCREEN_Y 864
220: #define FONT_HEIGHT 32
221:
222: struct adder {
223:
224: /* adder control registers */
225:
226: u_short register_address; /* ADDER reg pntr for use by DGA */
227: u_short request_enable; /* DMA request enables */
228: u_short interrupt_enable; /* interrupt enables */
229: u_short status; /* ADDER status bits */
230: u_short reserved1; /* test function only */
231: u_short spare1; /* spare address (what else?) */
232:
233: u_short reserved2; /* test function only */
234: u_short id_data; /* data path to I/D bus */
235: u_short command; /* ADDER chip command register */
236: u_short rasterop_mode; /* sets rasterop execution modes */
237: u_short cmd; /* duplicate path to above cmd reg */
238: u_short reserved3; /* test function only */
239:
240: /* scroll registers */
241:
242: u_short ID_scroll_data; /* I/D bus scroll data */
243: u_short ID_scroll_command; /* I/D bus scroll command */
244: u_short scroll_x_min; /* X scroll min - left boundary */
245: u_short scroll_x_max; /* X scroll max - right boundary */
246: u_short scroll_y_min; /* Y scroll min - upper boundary */
247: u_short scroll_y_max; /* Y scroll max - lower boundary */
248: u_short pause; /* Y coord to set stat when scanned */
249: u_short y_offset_pending; /* vertical scroll control */
250: u_short y_scroll_constant;
251:
252: /* update control registers */
253:
254: u_short x_index_pending; /* x pending index */
255: u_short y_index_pending; /* y pending index */
256: u_short x_index_new; /* new x index */
257: u_short y_index_new; /* new y index */
258: u_short x_index_old; /* old x index */
259: u_short y_index_old; /* old y index */
260: u_short x_clip_min; /* left clipping boundary */
261: u_short x_clip_max; /* right clipping boundary */
262: u_short y_clip_min; /* upper clipping boundary */
263: u_short y_clip_max; /* lower clipping boundary */
264: u_short spare2; /* spare address (another!) */
265:
266: /* rasterop control registers */
267:
268: u_short source_1_dx; /* source #1 x vector */
269: u_short source_1_dy; /* source #1 y vector*/
270: u_short source_1_x; /* source #1 x origin */
271: u_short source_1_y; /* source #1 y origin */
272: u_short destination_x; /* destination x origin */
273: u_short destination_y; /* destination y origin */
274: u_short fast_dest_dx; /* destination x fast vector */
275: u_short fast_dest_dy; /* destination y fast vector */
276: u_short slow_dest_dx; /* destination x slow vector */
277: u_short slow_dest_dy; /* destination y slow vector */
278: u_short fast_scale; /* scale factor for fast vector */
279: u_short slow_scale; /* scale factor for slow vector */
280: u_short source_2_x; /* source #2 x origin */
281: u_short source_2_y; /* source #2 y origin */
282: u_short source_2_size; /* source #2 height & width */
283: u_short error_1; /* error regs (?) */
284: u_short error_2;
285:
286: /* screen format control registers */
287:
288: u_short y_scan_count_0; /* y scan counts for vert timing */
289: u_short y_scan_count_1;
290: u_short y_scan_count_2;
291: u_short y_scan_count_3;
292: u_short x_scan_conf; /* x scan configuration */
293: u_short x_limit;
294: u_short y_limit;
295: u_short x_scan_count_0; /* x scan count for horiz timing */
296: u_short x_scan_count_1;
297: u_short x_scan_count_2;
298: u_short x_scan_count_3;
299: u_short x_scan_count_4;
300: u_short x_scan_count_5;
301: u_short x_scan_count_6;
302: u_short sync_phase_adj; /* sync phase (horiz sync count) */
303: };
304:
305: /*---------------------
306: * DUART definitions */
307:
308: /* command definitions */
309:
310: #define EN_RCV 0x01
311: #define DIS_RCV 0x02
312: #define EN_XMT 0x04
313: #define DIS_XMT 0x08
314: #define RESET_M 0x10
315: #define RESET_RCV 0x20
316: #define RESET_XMT 0x30
317: #define RESET_ERR 0x40
318: #define RESET_BD 0x50
319: #define START_BREAK 0x60
320: #define STOP_BREAK 0x70
321:
322: /* interrupt bit definitions */
323:
324: #define EI_XMT_A 0x01
325: #define EI_RCV_A 0x02
326: #define EI_XMT_B 0x10
327: #define EI_RCV_B 0x20
328:
329: #define XMT_RDY_A 0x01
330: #define RCV_RDY_A 0x02
331: #define XMT_RDY_B 0x10
332: #define RCV_RDY_B 0x20
333:
334: /* status register bit definitions */
335:
336: #define RCV_RDY 0x01
337: #define FIFO_FULL 0x02
338: #define XMT_RDY 0x04
339: #define XMT_EMT 0x08
340: #define OVER_ERR 0x10
341: #define ERR_PARITY 0x20
342: #define FRAME_ERR 0x40
343: #define RCVD_BREAK 0x80
344:
345:
346: struct duart {
347:
348: /* channel A - LK201 */
349:
350: short modeA; /* ch.A mode reg (read/write) */
351: short statusA; /* ch.A status reg (read) */
352: #define clkselA statusA /* ch.A clock slect reg (write) */
353: short cmdA; /* ch.A command reg (write) */
354: short dataA; /* rcv/xmt data ch.A (read/write) */
355: short inchng; /* input change state reg (read) */
356: #define auxctl inchng /* auxiliary control reg (write) */
357: short istatus; /* interrupt status reg (read) */
358: #define imask istatus /* interrupt mask reg (write) */
359: short CThi; /* counter/timer hi byte (read) */
360: #define CTRhi CThi /* counter/timer hi reg (write) */
361: short CTlo; /* counter/timer lo byte (read) */
362: #define CTRlo CTlo /* counter/timer lo reg (write) */
363:
364: /* channel B - pointing device */
365:
366: short modeB; /* ch.B mode reg (read/write) */
367: short statusB; /* ch.B status reg (read) */
368: #define clkselB statusB /* ch.B clock select reg (write) */
369: short cmdB; /* ch.B command reg (write) */
370: short dataB; /* ch.B rcv/xmt data (read/write) */
371: short rsrvd;
372: short inport; /* input port (read) */
373: #define outconf inport /* output port config reg (write) */
374: short strctr; /* start counter command (read) */
375: #define setbits setctr /* output bits set command (write) */
376: short stpctr; /* stop counter command (read) */
377: #define resetbits stpctr /* output bits reset cmd (write) */
378:
379: };
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