Annotation of sys/arch/vax/qbus/if_dereg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: if_dereg.h,v 1.2 2003/06/02 23:27:58 millert Exp $ */
! 2: /* $NetBSD: if_dereg.h,v 1.2 2000/05/28 17:23:44 ragge Exp $ */
! 3:
! 4: /*
! 5: * Copyright (c) 1982, 1986 Regents of the University of California.
! 6: * All rights reserved.
! 7: *
! 8: * Redistribution and use in source and binary forms, with or without
! 9: * modification, are permitted provided that the following conditions
! 10: * are met:
! 11: * 1. Redistributions of source code must retain the above copyright
! 12: * notice, this list of conditions and the following disclaimer.
! 13: * 2. Redistributions in binary form must reproduce the above copyright
! 14: * notice, this list of conditions and the following disclaimer in the
! 15: * documentation and/or other materials provided with the distribution.
! 16: * 3. Neither the name of the University nor the names of its contributors
! 17: * may be used to endorse or promote products derived from this software
! 18: * without specific prior written permission.
! 19: *
! 20: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
! 21: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
! 22: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
! 23: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
! 24: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
! 25: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
! 26: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
! 27: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
! 28: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
! 29: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
! 30: * SUCH DAMAGE.
! 31: *
! 32: * @(#)if_dereg.h 7.3 (Berkeley) 6/28/90
! 33: */
! 34:
! 35: /*
! 36: * DEC DEUNA interface
! 37: */
! 38: #ifdef notdef
! 39: struct dedevice {
! 40: union {
! 41: short p0_w;
! 42: char p0_b[2];
! 43: } u_p0;
! 44: #define pcsr0 u_p0.p0_w
! 45: #define pclow u_p0.p0_b[0]
! 46: #define pchigh u_p0.p0_b[1]
! 47: short pcsr1;
! 48: short pcsr2;
! 49: short pcsr3;
! 50: };
! 51: #endif
! 52:
! 53: #define DE_PCSR0 0
! 54: #define DE_PCSR1 2
! 55: #define DE_PCSR2 4
! 56: #define DE_PCSR3 6
! 57:
! 58: /*
! 59: * PCSR 0 bit descriptions
! 60: */
! 61: #define PCSR0_SERI 0x8000 /* Status error interrupt */
! 62: #define PCSR0_PCEI 0x4000 /* Port command error interrupt */
! 63: #define PCSR0_RXI 0x2000 /* Receive done interrupt */
! 64: #define PCSR0_TXI 0x1000 /* Transmit done interrupt */
! 65: #define PCSR0_DNI 0x0800 /* Done interrupt */
! 66: #define PCSR0_RCBI 0x0400 /* Receive buffer unavail intrpt */
! 67: #define PCSR0_FATI 0x0100 /* Fatal error interrupt */
! 68: #define PCSR0_INTR 0x0080 /* Interrupt summary */
! 69: #define PCSR0_INTE 0x0040 /* Interrupt enable */
! 70: #define PCSR0_RSET 0x0020 /* DEUNA reset */
! 71: #define PCSR0_CMASK 0x000f /* command mask */
! 72:
! 73: #define PCSR0_BITS "\20\20SERI\17PCEI\16RXI\15TXI\14DNI\13RCBI\11FATI\10INTR\7INTE\6RSET"
! 74:
! 75: /* bits 0-3 are for the PORT_COMMAND */
! 76: #define CMD_NOOP 0x0
! 77: #define CMD_GETPCBB 0x1 /* Get PCB Block */
! 78: #define CMD_GETCMD 0x2 /* Execute command in PCB */
! 79: #define CMD_STEST 0x3 /* Self test mode */
! 80: #define CMD_START 0x4 /* Reset xmit and receive ring ptrs */
! 81: #define CMD_BOOT 0x5 /* Boot DEUNA */
! 82: #define CMD_PDMD 0x8 /* Polling demand */
! 83: #define CMD_TMRO 0x9 /* Sanity timer on */
! 84: #define CMD_TMRF 0xa /* Sanity timer off */
! 85: #define CMD_RSTT 0xb /* Reset sanity timer */
! 86: #define CMD_STOP 0xf /* Suspend operation */
! 87:
! 88: /*
! 89: * PCSR 1 bit descriptions
! 90: */
! 91: #define PCSR1_XPWR 0x8000 /* Transceiver power BAD */
! 92: #define PCSR1_ICAB 0x4000 /* Interconnect cabling BAD */
! 93: #define PCSR1_STCODE 0x3f00 /* Self test error code */
! 94: #define PCSR1_PCTO 0x0080 /* Port command timed out */
! 95: #define PCSR1_ILLINT 0x0040 /* Illegal interrupt */
! 96: #define PCSR1_TIMEOUT 0x0020 /* Timeout */
! 97: #define PCSR1_POWER 0x0010 /* Power fail */
! 98: #define PCSR1_RMTC 0x0008 /* Remote console reserved */
! 99: #define PCSR1_STMASK 0x0007 /* State */
! 100:
! 101: /* bit 0-3 are for STATE */
! 102: #define STAT_RESET 0x0
! 103: #define STAT_PRIMLD 0x1 /* Primary load */
! 104: #define STAT_READY 0x2
! 105: #define STAT_RUN 0x3
! 106: #define STAT_UHALT 0x5 /* UNIBUS halted */
! 107: #define STAT_NIHALT 0x6 /* NI halted */
! 108: #define STAT_NIUHALT 0x7 /* NI and UNIBUS Halted */
! 109:
! 110: #define PCSR1_BITS "\20\20XPWR\17ICAB\10PCTO\7ILLINT\6TIMEOUT\5POWER\4RMTC"
! 111:
! 112: /*
! 113: * Port Control Block Base
! 114: */
! 115: struct de_pcbb {
! 116: int16_t pcbb0; /* function */
! 117: int16_t pcbb2; /* command specific */
! 118: int16_t pcbb4;
! 119: int16_t pcbb6;
! 120: };
! 121:
! 122: /* PCBB function codes */
! 123: #define FC_NOOP 0x00 /* NO-OP */
! 124: #define FC_LSUADDR 0x01 /* Load and start microaddress */
! 125: #define FC_RDDEFAULT 0x02 /* Read default physical address */
! 126: #define FC_RDPHYAD 0x04 /* Read physical address */
! 127: #define FC_WTPHYAD 0x05 /* Write physical address */
! 128: #define FC_RDMULTI 0x06 /* Read multicast address list */
! 129: #define FC_WTMULTI 0x07 /* Read multicast address list */
! 130: #define FC_RDRING 0x08 /* Read ring format */
! 131: #define FC_WTRING 0x09 /* Write ring format */
! 132: #define FC_RDCNTS 0x0a /* Read counters */
! 133: #define FC_RCCNTS 0x0b /* Read and clear counters */
! 134: #define FC_RDMODE 0x0c /* Read mode */
! 135: #define FC_WTMODE 0x0d /* Write mode */
! 136: #define FC_RDSTATUS 0x0e /* Read port status */
! 137: #define FC_RCSTATUS 0x0f /* Read and clear port status */
! 138: #define FC_DUMPMEM 0x10 /* Dump internal memory */
! 139: #define FC_LOADMEM 0x11 /* Load internal memory */
! 140: #define FC_RDSYSID 0x12 /* Read system ID parameters */
! 141: #define FC_WTSYSID 0x13 /* Write system ID parameters */
! 142: #define FC_RDSERAD 0x14 /* Read load server address */
! 143: #define FC_WTSERAD 0x15 /* Write load server address */
! 144:
! 145: /*
! 146: * Unibus Data Block Base (UDBB) for ring buffers
! 147: */
! 148: struct de_udbbuf {
! 149: int16_t b_tdrbl; /* Transmit desc ring base low 16 bits */
! 150: int8_t b_tdrbh; /* Transmit desc ring base high 2 bits */
! 151: int8_t b_telen; /* Length of each transmit entry */
! 152: int16_t b_trlen; /* Number of entries in the XMIT desc ring */
! 153: int16_t b_rdrbl; /* Receive desc ring base low 16 bits */
! 154: int8_t b_rdrbh; /* Receive desc ring base high 2 bits */
! 155: int8_t b_relen; /* Length of each receive entry */
! 156: int16_t b_rrlen; /* Number of entries in the RECV desc ring */
! 157: };
! 158:
! 159: /*
! 160: * Transmit/Receive Ring Entry
! 161: */
! 162: struct de_ring {
! 163: int16_t r_slen; /* Segment length */
! 164: int16_t r_segbl; /* Segment address (low 16 bits) */
! 165: int8_t r_segbh; /* Segment address (hi 2 bits) */
! 166: u_int8_t r_flags; /* Status flags */
! 167: u_int16_t r_tdrerr; /* Errors */
! 168: #define r_lenerr r_tdrerr
! 169: };
! 170:
! 171: #define XFLG_OWN 0x80 /* If 0 then owned by driver */
! 172: #define XFLG_ERRS 0x40 /* Error summary */
! 173: #define XFLG_MTCH 0x20 /* Address match on xmit request */
! 174: #define XFLG_MORE 0x10 /* More than one entry required */
! 175: #define XFLG_ONE 0x08 /* One collision encountered */
! 176: #define XFLG_DEF 0x04 /* Transmit deferred */
! 177: #define XFLG_STP 0x02 /* Start of packet */
! 178: #define XFLG_ENP 0x01 /* End of packet */
! 179:
! 180: #define XFLG_BITS "\10\10OWN\7ERRS\6MTCH\5MORE\4ONE\3DEF\2STP\1ENP"
! 181:
! 182: #define XERR_BUFL 0x8000 /* Buffer length error */
! 183: #define XERR_UBTO 0x4000 /* UNIBUS tiemout */
! 184: #define XERR_LCOL 0x1000 /* Late collision */
! 185: #define XERR_LCAR 0x0800 /* Loss of carrier */
! 186: #define XERR_RTRY 0x0400 /* Failed after 16 retries */
! 187: #define XERR_TDR 0x03ff /* TDR value */
! 188:
! 189: #define XERR_BITS "\20\20BUFL\17UBTO\15LCOL\14LCAR\13RTRY"
! 190:
! 191: #define RFLG_OWN 0x80 /* If 0 then owned by driver */
! 192: #define RFLG_ERRS 0x40 /* Error summary */
! 193: #define RFLG_FRAM 0x20 /* Framing error */
! 194: #define RFLG_OFLO 0x10 /* Message overflow */
! 195: #define RFLG_CRC 0x08 /* CRC error */
! 196: #define RFLG_STP 0x02 /* Start of packet */
! 197: #define RFLG_ENP 0x01 /* End of packet */
! 198:
! 199: #define RFLG_BITS "\10\10OWN\7ERRS\6FRAM\5OFLO\4CRC\2STP\1ENP"
! 200:
! 201: #define RERR_BUFL 0x8000 /* Buffer length error */
! 202: #define RERR_UBTO 0x4000 /* UNIBUS tiemout */
! 203: #define RERR_NCHN 0x2000 /* No data chaining */
! 204: #define RERR_MLEN 0x0fff /* Message length */
! 205:
! 206: #define RERR_BITS "\20\20BUFL\17UBTO\16NCHN"
! 207:
! 208: /* mode description bits */
! 209: #define MOD_HDX 0x0001 /* Half duplex mode */
! 210: #define MOD_LOOP 0x0004 /* Enable internal loopback */
! 211: #define MOD_DTCR 0x0008 /* Disables CRC generation */
! 212: #define MOD_DMNT 0x0200 /* Disable maintenance features */
! 213: #define MOD_ECT 0x0400 /* Enable collision test */
! 214: #define MOD_TPAD 0x1000 /* Transmit message pad enable */
! 215: #define MOD_DRDC 0x2000 /* Disable data chaining */
! 216: #define MOD_ENAL 0x4000 /* Enable all multicast */
! 217: #define MOD_PROM 0x8000 /* Enable promiscuous mode */
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