Annotation of sys/arch/vax/qbus/dzreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: dzreg.h,v 1.3 2006/07/31 18:51:06 miod Exp $ */
2: /* $NetBSD: dzreg.h,v 1.4 1999/05/27 16:03:13 ragge Exp $ */
3: /*
4: * Copyright (c) 1996 Ken C. Wellsch. All rights reserved.
5: *
6: * Redistribution and use in source and binary forms, with or without
7: * modification, are permitted provided that the following conditions
8: * are met:
9: * 1. Redistributions of source code must retain the above copyright
10: * notice, this list of conditions and the following disclaimer.
11: * 2. The name of the author may not be used to endorse or promote products
12: * derived from this software without specific prior written permission
13: *
14: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24: */
25:
26: struct dz_regs {
27: bus_addr_t dr_csr;
28: bus_addr_t dr_rbuf;
29: #define dr_lpr dr_rbuf
30: bus_addr_t dr_dtr;
31: bus_addr_t dr_break;
32: bus_addr_t dr_tbuf;
33: bus_addr_t dr_tcr;
34: bus_addr_t dr_tcrw;
35: bus_addr_t dr_ring;
36: bus_addr_t dr_dcd;
37: };
38: #define DZ_UBA_CSR 0
39: #define DZ_UBA_RBUF 2
40: #define DZ_UBA_DTR 5
41: #define DZ_UBA_BREAK 7
42: #define DZ_UBA_TBUF 6
43: #define DZ_UBA_TCR 4
44: #define DZ_UBA_DCD 7
45: #define DZ_UBA_RING 6
46:
47: /* CSR bits */
48:
49: #define DZ_CSR_TX_READY 0100000 /* Transmitter Ready */
50: #define DZ_CSR_TXIE 0040000 /* Transmitter Interrupt Enable */
51: #define DZ_CSR_SA 0020000 /* Silo Alarm */
52: #define DZ_CSR_SAE 0010000 /* Silo Alarm Enable */
53: #define DZ_CSR_TX_LINE_MASK 0007400 /* Which TX line */
54:
55: #define DZ_CSR_RX_DONE 0000200 /* Receiver Done */
56: #define DZ_CSR_RXIE 0000100 /* Receiver Interrupt Enable */
57: #define DZ_CSR_MSE 0000040 /* Master Scan Enable */
58: #define DZ_CSR_RESET 0000020 /* Clear (reset) Controller */
59: #define DZ_CSR_MAINTENANCE 0000010
60: #define DZ_CSR_UNUSED 0000007
61:
62: /* RBUF bits */
63:
64: #define DZ_RBUF_DATA_VALID 0100000
65: #define DZ_RBUF_OVERRUN_ERR 0040000
66: #define DZ_RBUF_FRAMING_ERR 0020000
67: #define DZ_RBUF_PARITY_ERR 0010000
68: #define DZ_RBUF_RX_LINE_MASK 0007400
69:
70: /* LPR bits */
71:
72: #define DZ_LPR_UNUSED 0160000
73: #define DZ_LPR_RX_ENABLE 0010000
74:
75: #define DZ_LPR_B50 0x0
76: #define DZ_LPR_B75 0x1
77: #define DZ_LPR_B110 0x2
78: #define DZ_LPR_B134 0x3
79: #define DZ_LPR_B150 0x4
80: #define DZ_LPR_B300 0x5
81: #define DZ_LPR_B600 0x6
82: #define DZ_LPR_B1200 0x7
83: #define DZ_LPR_B1800 0x8
84: #define DZ_LPR_B2000 0x9
85: #define DZ_LPR_B2400 0xA
86: #define DZ_LPR_B3600 0xB
87: #define DZ_LPR_B4800 0xC
88: #define DZ_LPR_B7200 0xD
89: #define DZ_LPR_B9600 0xE
90: #define DZ_LPR_B19200 0xF
91:
92: #define DZ_LPR_OPAR 0000200
93: #define DZ_LPR_PARENB 0000100
94: #define DZ_LPR_2_STOP 0000040
95:
96: #define DZ_LPR_5_BIT_CHAR 0000000
97: #define DZ_LPR_6_BIT_CHAR 0000010
98: #define DZ_LPR_7_BIT_CHAR 0000020
99: #define DZ_LPR_8_BIT_CHAR 0000030
100:
101: #define DZ_LPR_CHANNEL_MASK 0000007
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