Annotation of sys/arch/vax/qbus/dz_uba.c, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: dz_uba.c,v 1.6 2006/07/29 17:06:27 miod Exp $ */
! 2: /* $NetBSD: dz_uba.c,v 1.11 2000/06/04 06:17:02 matt Exp $ */
! 3: /*
! 4: * Copyright (c) 1998 Ludd, University of Lule}, Sweden. All rights reserved.
! 5: * Copyright (c) 1996 Ken C. Wellsch. All rights reserved.
! 6: *
! 7: * Redistribution and use in source and binary forms, with or without
! 8: * modification, are permitted provided that the following conditions
! 9: * are met:
! 10: * 1. Redistributions of source code must retain the above copyright
! 11: * notice, this list of conditions and the following disclaimer.
! 12: * 2. Redistributions in binary form must reproduce the above copyright
! 13: * notice, this list of conditions and the following disclaimer in the
! 14: * documentation and/or other materials provided with the distribution.
! 15: * 3. All advertising materials mentioning features or use of this software
! 16: * must display the following acknowledgement:
! 17: * This product includes software developed at Ludd, University of
! 18: * Lule}, Sweden and its contributors.
! 19: * 4. The name of the author may not be used to endorse or promote products
! 20: * derived from this software without specific prior written permission
! 21: *
! 22: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
! 23: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
! 24: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
! 25: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
! 26: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
! 27: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
! 28: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
! 29: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
! 30: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
! 31: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
! 32: */
! 33:
! 34: #include <sys/param.h>
! 35: #include <sys/systm.h>
! 36: #include <sys/ioctl.h>
! 37: #include <sys/tty.h>
! 38: #include <sys/proc.h>
! 39: #include <sys/buf.h>
! 40: #include <sys/conf.h>
! 41: #include <sys/file.h>
! 42: #include <sys/uio.h>
! 43: #include <sys/kernel.h>
! 44: #include <sys/syslog.h>
! 45: #include <sys/device.h>
! 46:
! 47: #include <machine/bus.h>
! 48: #include <machine/pte.h>
! 49: #include <machine/trap.h>
! 50: #include <machine/scb.h>
! 51:
! 52: #include <arch/vax/qbus/ubavar.h>
! 53:
! 54: #include <arch/vax/qbus/dzreg.h>
! 55: #include <arch/vax/qbus/dzvar.h>
! 56:
! 57: static int dz_uba_match(struct device *, struct cfdata *, void *);
! 58: static void dz_uba_attach(struct device *, struct device *, void *);
! 59:
! 60: struct cfattach dz_uba_ca = {
! 61: sizeof(struct dz_softc), (cfmatch_t)dz_uba_match, dz_uba_attach
! 62: };
! 63:
! 64: /* Autoconfig handles: setup the controller to interrupt, */
! 65: /* then complete the housecleaning for full operation */
! 66:
! 67: static int
! 68: dz_uba_match(parent, cf, aux)
! 69: struct device *parent;
! 70: struct cfdata *cf;
! 71: void *aux;
! 72: {
! 73: struct uba_attach_args *ua = aux;
! 74: #ifdef notdef
! 75: bus_space_tag_t iot = ua->ua_iot;
! 76: #endif
! 77: bus_space_handle_t ioh = ua->ua_ioh;
! 78: int n;
! 79:
! 80: /* Reset controller to initialize, enable TX interrupts */
! 81: /* to catch floating vector info elsewhere when completed */
! 82:
! 83: bus_space_write_2(iot, ioh, DZ_UBA_CSR, DZ_CSR_MSE | DZ_CSR_TXIE);
! 84: bus_space_write_1(iot, ioh, DZ_UBA_TCR, 1);
! 85:
! 86: DELAY(100000); /* delay 1/10 second */
! 87:
! 88: bus_space_write_2(iot, ioh, DZ_UBA_CSR, DZ_CSR_RESET);
! 89:
! 90: /* Now wait up to 3 seconds for reset/clear to complete. */
! 91:
! 92: for (n = 0; n < 300; n++) {
! 93: DELAY(10000);
! 94: if ((bus_space_read_2(iot, ioh, DZ_UBA_CSR)&DZ_CSR_RESET) == 0)
! 95: break;
! 96: }
! 97:
! 98: /* If the RESET did not clear after 3 seconds, */
! 99: /* the controller must be broken. */
! 100:
! 101: if (n >= 300)
! 102: return (0);
! 103:
! 104: /* Register the TX interrupt handler */
! 105:
! 106:
! 107: return (1);
! 108: }
! 109:
! 110: static void
! 111: dz_uba_attach(parent, self, aux)
! 112: struct device *parent, *self;
! 113: void *aux;
! 114: {
! 115: struct dz_softc *sc = (void *)self;
! 116: struct uba_attach_args *ua = aux;
! 117:
! 118: sc->sc_iot = ua->ua_iot;
! 119: sc->sc_ioh = ua->ua_ioh;
! 120:
! 121: sc->sc_dr.dr_csr = DZ_UBA_CSR;
! 122: sc->sc_dr.dr_rbuf = DZ_UBA_RBUF;
! 123: sc->sc_dr.dr_dtr = DZ_UBA_DTR;
! 124: sc->sc_dr.dr_break = DZ_UBA_BREAK;
! 125: sc->sc_dr.dr_tbuf = DZ_UBA_TBUF;
! 126: sc->sc_dr.dr_tcr = DZ_UBA_TCR;
! 127: sc->sc_dr.dr_dcd = DZ_UBA_DCD;
! 128: sc->sc_dr.dr_ring = DZ_UBA_RING;
! 129:
! 130: sc->sc_type = DZ_DZ;
! 131:
! 132: /* Now register the TX & RX interrupt handlers */
! 133: sc->sc_tcvec = ua->ua_cvec;
! 134: uba_intr_establish(ua->ua_icookie, sc->sc_tcvec,
! 135: dzxint, sc, &sc->sc_tintrcnt);
! 136: sc->sc_rcvec = ua->ua_cvec - 4;
! 137: uba_intr_establish(ua->ua_icookie, sc->sc_rcvec,
! 138: dzrint, sc, &sc->sc_rintrcnt);
! 139: uba_reset_establish(dzreset, self);
! 140:
! 141: evcount_attach(&sc->sc_rintrcnt, sc->sc_dev.dv_xname,
! 142: (void *)&sc->sc_rcvec, &evcount_intr);
! 143: evcount_attach(&sc->sc_tintrcnt, sc->sc_dev.dv_xname,
! 144: (void *)&sc->sc_tcvec, &evcount_intr);
! 145:
! 146: dzattach(sc);
! 147: }
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