Annotation of sys/arch/vax/qbus/dhureg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: dhureg.h,v 1.4 2003/04/06 01:33:32 hugh Exp $ */
2: /* $NetBSD: dhureg.h,v 1.4 1999/05/28 20:17:29 ragge Exp $ */
3: /*
4: * Copyright (c) 1996 Ken C. Wellsch. All rights reserved.
5: *
6: * Redistribution and use in source and binary forms, with or without
7: * modification, are permitted provided that the following conditions
8: * are met:
9: * 1. Redistributions of source code must retain the above copyright
10: * notice, this list of conditions and the following disclaimer.
11: * 2. Redistributions in binary form must reproduce the above copyright
12: * notice, this list of conditions and the following disclaimer in the
13: * documentation and/or other materials provided with the distribution.
14: * 3. All advertising materials mentioning features or use of this software
15: * must display the following acknowledgement:
16: * This product includes software developed by the University of
17: * California, Berkeley and its contributors.
18: * 4. Neither the name of the University nor the names of its contributors
19: * may be used to endorse or promote products derived from this software
20: * without specific prior written permission.
21: *
22: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32: * SUCH DAMAGE.
33: */
34:
35: #ifdef notdef
36: union w_b
37: {
38: u_short word;
39: struct {
40: u_char byte_lo;
41: u_char byte_hi;
42: } bytes;
43: };
44:
45: struct DHUregs
46: {
47: volatile union w_b u_csr; /* Control/Status Register (R/W) */
48: volatile u_short dhu_rbuf; /* Receive Buffer (R only) */
49: #define dhu_txchar dhu_rbuf /* Transmit Character (W only) */
50: volatile u_short dhu_lpr; /* Line Parameter Register (R/W) */
51: volatile u_short dhu_stat; /* Line Status (R only) */
52: volatile u_short dhu_lnctrl; /* Line Control (R/W) */
53: volatile u_short dhu_tbufad1; /* Transmit Buffer Address 1 (R/W) */
54: volatile u_short dhu_tbufad2; /* Transmit Buffer Address 2 (R/W) */
55: volatile u_short dhu_tbufcnt; /* Transmit Buffer Count (R/W) */
56: };
57:
58: #define dhu_csr u_csr.word
59: #define dhu_csr_lo u_csr.bytes.byte_lo
60: #define dhu_csr_hi u_csr.bytes.byte_hi
61:
62: typedef struct DHUregs dhuregs;
63: #endif
64:
65: #define DHU_UBA_CSR 0
66: #define DHU_UBA_CSR_HI 1
67: #define DHU_UBA_RBUF 2
68: #define DHU_UBA_TXCHAR 2
69: #define DHU_UBA_RXTIME DHU_UBA_TXCHAR /* on a real dhu only */
70: #define DHU_UBA_LPR 4
71: #define DHU_UBA_STAT 6
72: #define DHU_UBA_FIFO DHU_UBA_STAT /* on a real dhu only */
73: #define DHU_UBA_LNCTRL 8
74: #define DHU_UBA_TBUFAD1 10
75: #define DHU_UBA_TBUFAD2 12
76: #define DHU_UBA_TBUFCNT 14
77:
78: /* CSR bits */
79:
80: #define DHU_CSR_TX_ACTION 0100000
81: #define DHU_CSR_TXIE 0040000
82: #define DHU_CSR_DIAG_FAIL 0020000
83: #define DHU_CSR_TX_DMA_ERROR 0010000
84: #define DHU_CSR_TX_LINE_MASK 0007400
85: #define DHU_CSR_RX_DATA_AVAIL 0000200
86: #define DHU_CSR_RXIE 0000100
87: #define DHU_CSR_MASTER_RESET 0000040
88: #define DHU_CSR_UNUSED 0000020
89: #define DHU_CSR_CHANNEL_MASK 0000017
90:
91: /* RBUF bits */
92:
93: #define DHU_RBUF_DATA_VALID 0100000
94: #define DHU_RBUF_OVERRUN_ERR 0040000
95: #define DHU_RBUF_FRAMING_ERR 0020000
96: #define DHU_RBUF_PARITY_ERR 0010000
97: #define DHU_RBUF_RX_LINE_MASK 0007400
98:
99: #define DHU_DIAG_CODE 0070001
100: #define DHU_MODEM_CODE 0070000
101:
102: /* TXCHAR bits */
103:
104: #define DHU_TXCHAR_DATA_VALID 0100000
105:
106: /* LPR bits */
107:
108: #define DHU_LPR_B50 0x0
109: #define DHU_LPR_B75 0x1
110: #define DHU_LPR_B110 0x2
111: #define DHU_LPR_B134 0x3
112: #define DHU_LPR_B150 0x4
113: #define DHU_LPR_B300 0x5
114: #define DHU_LPR_B600 0x6
115: #define DHU_LPR_B1200 0x7
116: #define DHU_LPR_B1800 0x8
117: #define DHU_LPR_B2000 0x9
118: #define DHU_LPR_B2400 0xA
119: #define DHU_LPR_B4800 0xB
120: #define DHU_LPR_B7200 0xC
121: #define DHU_LPR_B9600 0xD
122: #define DHU_LPR_B19200 0xE
123: #define DHU_LPR_B38400 0xF
124:
125: #define DHU_LPR_5_BIT_CHAR 0000000
126: #define DHU_LPR_6_BIT_CHAR 0000010
127: #define DHU_LPR_7_BIT_CHAR 0000020
128: #define DHU_LPR_8_BIT_CHAR 0000030
129: #define DHU_LPR_PARENB 0000040
130: #define DHU_LPR_EPAR 0000100
131: #define DHU_LPR_2_STOP 0000200
132:
133: /* STAT bits */
134:
135: #define DHU_STAT_DSR 0100000
136: #define DHU_STAT_RI 0020000
137: #define DHU_STAT_DCD 0010000
138: #define DHU_STAT_CTS 0004000
139: #define DHU_STAT_MDL 0001000
140: #define DHU_STAT_DHU 0000400
141:
142: /* LNCTRL bits */
143:
144: #define DHU_LNCTRL_DMA_ABORT 0000001
145: #define DHU_LNCTRL_IAUTO 0000002
146: #define DHU_LNCTRL_RX_ENABLE 0000004
147: #define DHU_LNCTRL_BREAK 0000010
148: #define DHU_LNCTRL_OAUTO 0000020
149: #define DHU_LNCTRL_FORCE_XOFF 0000040
150: #define DHU_LNCTRL_LINK_TYPE 0000400
151: #define DHU_LNCTRL_DTR 0001000
152: #define DHU_LNCTRL_RTS 0010000
153:
154: /* TBUFAD2 bits */
155:
156: #define DHU_TBUFAD2_DMA_START 0000200
157: #define DHU_TBUFAD2_TX_ENABLE 0100000
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