Annotation of sys/arch/vax/include/mtpr.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: mtpr.h,v 1.5 2000/04/26 03:08:42 bjc Exp $ */
! 2: /* $NetBSD: mtpr.h,v 1.12 1999/06/06 19:06:29 ragge Exp $ */
! 3:
! 4: /*
! 5: * Copyright (c) 1994 Ludd, University of Lule}, Sweden.
! 6: * All rights reserved.
! 7: *
! 8: * Redistribution and use in source and binary forms, with or without
! 9: * modification, are permitted provided that the following conditions
! 10: * are met:
! 11: * 1. Redistributions of source code must retain the above copyright
! 12: * notice, this list of conditions and the following disclaimer.
! 13: * 2. Redistributions in binary form must reproduce the above copyright
! 14: * notice, this list of conditions and the following disclaimer in the
! 15: * documentation and/or other materials provided with the distribution.
! 16: * 3. All advertising materials mentioning features or use of this software
! 17: * must display the following acknowledgement:
! 18: * This product includes software developed at Ludd, University of Lule}.
! 19: * 4. The name of the author may not be used to endorse or promote products
! 20: * derived from this software without specific prior written permission
! 21: *
! 22: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
! 23: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
! 24: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
! 25: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
! 26: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
! 27: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
! 28: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
! 29: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
! 30: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
! 31: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
! 32: */
! 33:
! 34: /* All bugs are subject to removal without further notice */
! 35:
! 36: #ifndef _VAX_MTPR_H_
! 37: #define _VAX_MTPR_H_
! 38:
! 39: /******************************************************************************
! 40:
! 41: Processor register numbers in the VAX /IC
! 42:
! 43: ******************************************************************************/
! 44:
! 45:
! 46: #define PR_KSP 0 /* Kernel Stack Pointer */
! 47: #define PR_ESP 1 /* Executive Stack Pointer */
! 48: #define PR_SSP 2 /* Supervisor Stack Pointer */
! 49: #define PR_USP 3 /* User Stack Pointer */
! 50: #define PR_ISP 4 /* Interrupt Stack Pointer */
! 51:
! 52: #define PR_P0BR 8 /* P0 Base Register */
! 53: #define PR_P0LR 9 /* P0 Length Register */
! 54: #define PR_P1BR 10 /* P1 Base Register */
! 55: #define PR_P1LR 11 /* P1 Length Register */
! 56: #define PR_SBR 12 /* System Base Register */
! 57: #define PR_SLR 13 /* System Limit Register */
! 58: #define PR_PCBB 16 /* Process Control Block Base */
! 59: #define PR_SCBB 17 /* System Control Block Base */
! 60: #define PR_IPL 18 /* Interrupt Priority Level */
! 61: #define PR_ASTLVL 19 /* AST Level */
! 62: #define PR_SIRR 20 /* Software Interrupt Request */
! 63: #define PR_SISR 21 /* Software Interrupt Summary */
! 64: #define PR_IPIR 22 /* KA820 Interprocessor register */
! 65: #define PR_MCSR 23 /* Machine Check Status Register 11/750 */
! 66: #define PR_ICCS 24 /* Interval Clock Control */
! 67: #define PR_NICR 25 /* Next Interval Count */
! 68: #define PR_ICR 26 /* Interval Count */
! 69: #define PR_TODR 27 /* Time Of Year (optional) */
! 70: #define PR_CSRS 28 /* Console Storage R/S */
! 71: #define PR_CSRD 29 /* Console Storage R/D */
! 72: #define PR_CSTS 30 /* Console Storage T/S */
! 73: #define PR_CSTD 31 /* Console Storage T/D */
! 74: #define PR_RXCS 32 /* Console Receiver C/S */
! 75: #define PR_RXDB 33 /* Console Receiver D/B */
! 76: #define PR_TXCS 34 /* Console Transmit C/S */
! 77: #define PR_TXDB 35 /* Console Transmit D/B */
! 78: #define PR_TBDR 36 /* Translation Buffer Group Disable Register 11/750 */
! 79: #define PR_CADR 37 /* Cache Disable Register 11/750 */
! 80: #define PR_MCESR 38 /* Machiune Check Error Summary Register 11/750 */
! 81: #define PR_CAER 39 /* Cache Error Register 11/750 */
! 82: #define PR_ACCS 40 /* Accelerator control register */
! 83: #define PR_SAVISP 41 /* Console Saved ISP */
! 84: #define PR_SAVPC 42 /* Console Saved PC */
! 85: #define PR_SAVPSL 43 /* Console Saved PSL */
! 86: #define PR_WCSA 44 /* WCS Address */
! 87: #define PR_WCSB 45 /* WCS Data */
! 88: #define PR_SBIFS 48 /* SBI Fault/Status */
! 89: #define PR_SBIS 49 /* SBI Silo */
! 90: #define PR_SBISC 50 /* SBI Silo Comparator */
! 91: #define PR_SBIMT 51 /* SBI Silo Maintenance */
! 92: #define PR_SBIER 52 /* SBI Error Register */
! 93: #define PR_SBITA 53 /* SBI Timeout Address Register */
! 94: #define PR_SBIQC 54 /* SBI Quadword Clear */
! 95: #define PR_IUR 55 /* Initialize Unibus Register 11/750 */
! 96: #define PR_MAPEN 56 /* Memory Management Enable */
! 97: #define PR_TBIA 57 /* Trans. Buf. Invalidate All */
! 98: #define PR_TBIS 58 /* Trans. Buf. Invalidate Single */
! 99: #define PR_TBDATA 59 /* Translation Buffer Data */
! 100: #define PR_MBRK 60 /* Microprogram Break */
! 101: #define PR_PMR 61 /* Performance Monnitor Enable */
! 102: #define PR_SID 62 /* System ID Register */
! 103: #define PR_TBCHK 63 /* Translation Buffer Check */
! 104:
! 105: #define PR_PAMACC 64 /* Physical Address Memory Map Access (KA86) */
! 106: #define PR_PAMLOC 65 /* Physical Address Memory Map Location (KA86) */
! 107: #define PR_CSWP 66 /* Cache Sweep (KA86) */
! 108: #define PR_MDECC 67 /* MBOX Data Ecc Register (KA86) */
! 109: #define PR_MENA 68 /* MBOX Error Enable Register (KA86) */
! 110: #define PR_MDCTL 69 /* MBOX Data Control Register (KA86) */
! 111: #define PR_MCCTL 70 /* MBOX Mcc Control Register (KA86) */
! 112: #define PR_MERG 71 /* MBOX Error Generator Register (KA86) */
! 113: #define PR_CRBT 72 /* Console Reboot (KA86) */
! 114: #define PR_DFI 73 /* Diagnostic Fault Insertion Register (KA86) */
! 115: #define PR_EHSR 74 /* Error Handling Status Register (KA86) */
! 116: #define PR_STXCS 76 /* Console Storage C/S (KA86) */
! 117: #define PR_STXDB 77 /* Console Storage D/B (KA86) */
! 118: #define PR_ESPA 78 /* EBOX Scratchpad Address (KA86) */
! 119: #define PR_ESPD 79 /* EBOX Scratchpad Data (KA86) */
! 120:
! 121: #define PR_RXCS1 80 /* Serial-Line Unit 1 Receive CSR (KA820) */
! 122: #define PR_RXDB1 81 /* Serial-Line Unit 1 Receive Data Buffer (KA820) */
! 123: #define PR_TXCS1 82 /* Serial-Line Unit 1 Transmit CSR (KA820) */
! 124: #define PR_TXDB1 83 /* Serial-Line Unit 1 Transmit Data Buffer (KA820) */
! 125: #define PR_RXCS2 84 /* Serial-Line Unit 2 Receive CSR (KA820) */
! 126: #define PR_RXDB2 85 /* Serial-Line Unit 2 Receive Data Buffer (KA820) */
! 127: #define PR_TXCS2 86 /* Serial-Line Unit 2 Transmit CSR (KA820) */
! 128: #define PR_TXDB2 87 /* Serial-Line Unit 2 Transmit Data Buffer (KA820) */
! 129: #define PR_RXCS3 88 /* Serial-Line Unit 3 Receive CSR (KA820) */
! 130: #define PR_RXDB3 89 /* Serial-Line Unit 3 Receive Data Buffer (KA820) */
! 131: #define PR_TXCS3 90 /* Serial-Line Unit 3 Transmit CSR (KA820) */
! 132: #define PR_TXDB3 91 /* Serial-Line Unit 3 Transmit Data Buffer (KA820) */
! 133: #define PR_RXCD 92 /* Receive Console Data from another cpu (KA820) */
! 134: #define PR_CACHEX 93 /* Cache invalidate Register (KA820) */
! 135: #define PR_BINID 94 /* VAXBI node ID Register (KA820) */
! 136: #define PR_BISTOP 95 /* VAXBI Stop Register (KA820) */
! 137:
! 138: #define PR_BCBTS 113 /* Backup Cache Tag Store (KA670) */
! 139: #define PR_BCP1TS 114 /* Primary Tag Store 1st half (KA670) */
! 140: #define PR_BCP2TS 115 /* Primary Tag Store 2st half (KA670) */
! 141: #define PR_BCRFR 116 /* Refresh Register (KA670) */
! 142: #define PR_BCIDX 117 /* Index Register (KA670) */
! 143: #define PR_BCSTS 118 /* Status (KA670) */
! 144: #define PR_BCCTL 119 /* Control Register (KA670) */
! 145: #define PR_BCERR 120 /* Error Address (KA670) */
! 146: #define PR_BCFBTS 121 /* Flush backup tag store (KA670) */
! 147: #define PR_BCFPTS 122 /* Flush primary tag store (KA670) */
! 148:
! 149: #define PR_VINTSR 123 /* vector i/f error status (KA43/KA46) */
! 150: #define PR_PCTAG 124 /* primary cache tag store (KA43/KA46) */
! 151: #define PR_PCIDX 125 /* primary cache index (KA43/KA46) */
! 152: #define PR_PCERR 126 /* primary cache error address (KA43/KA46) */
! 153: #define PR_PCSTS 127 /* primary cache status (KA43/KA46) */
! 154:
! 155: /* Definitions for AST */
! 156: #define AST_NO 4
! 157: #define AST_OK 3
! 158:
! 159: #ifndef _LOCORE
! 160:
! 161: #define mtpr(val,reg) \
! 162: { \
! 163: __asm__ __volatile ("mtpr %0,%1" \
! 164: : /* No output */ \
! 165: : "g" (val), "g" (reg)); \
! 166: }
! 167:
! 168: #define mfpr(reg) \
! 169: ({ \
! 170: register int val; \
! 171: __asm__ __volatile ("mfpr %1,%0" \
! 172: : "=g" (val) \
! 173: : "g" (reg)); \
! 174: val; \
! 175: })
! 176: #endif /* _LOCORE */
! 177:
! 178: #endif /* _VAX_MTPR_H_ */
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