Annotation of sys/arch/vax/include/ka820.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: ka820.h,v 1.5 2003/06/02 23:27:57 millert Exp $ */
2: /* $NetBSD: ka820.h,v 1.3 2000/01/24 02:40:32 matt Exp $ */
3: /*
4: * Copyright (c) 1988 Regents of the University of California.
5: * All rights reserved.
6: *
7: * This code is derived from software contributed to Berkeley by
8: * Chris Torek.
9: *
10: * Redistribution and use in source and binary forms, with or without
11: * modification, are permitted provided that the following conditions
12: * are met:
13: * 1. Redistributions of source code must retain the above copyright
14: * notice, this list of conditions and the following disclaimer.
15: * 2. Redistributions in binary form must reproduce the above copyright
16: * notice, this list of conditions and the following disclaimer in the
17: * documentation and/or other materials provided with the distribution.
18: * 3. Neither the name of the University nor the names of its contributors
19: * may be used to endorse or promote products derived from this software
20: * without specific prior written permission.
21: *
22: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32: * SUCH DAMAGE.
33: *
34: * @(#)ka820.h 7.3 (Berkeley) 6/28/90
35: */
36:
37: /*
38: * Definitions specific to the ka820 cpu.
39: */
40:
41: /*
42: * Device addresses.
43: */
44: #define KA820_PORTADDR 0x20088000 /* port controller */
45: #define KA820_BRAMADDR 0x20090000 /* boot ram */
46: #define KA820_EEPROMADDR 0x20098000 /* eeprom */
47: #define KA820_RX50ADDR 0x200b0000 /* rcx50 */
48: #define KA820_CLOCKADDR 0x200b8000 /* watch chip */
49:
50: /*
51: * Sizes. The port controller, RCX50, and watch chip are all one page.
52: */
53: #define KA820_BRPAGES 16 /* 8K */
54: #define KA820_EEPAGES 64 /* 32K */
55:
56: /* port controller CSR bit values */
57: #define KA820PORT_RSTHALT 0x80000000 /* restart halt */
58: #define KA820PORT_LCONS 0x40000000 /* logical console */
59: #define KA820PORT_LCONSEN 0x20000000 /* logical console enable */
60: #define KA820PORT_BIRESET 0x10000000 /* BI reset */
61: #define KA820PORT_BISTF 0x08000000 /* ??? */
62: #define KA820PORT_ENBAPT 0x04000000 /* ??? */
63: #define KA820PORT_STPASS 0x02000000 /* self test pass */
64: #define KA820PORT_RUN 0x01000000 /* run */
65: #define KA820PORT_WWPE 0x00800000 /* ??? parity even? */
66: #define KA820PORT_EVLCK 0x00400000 /* event lock */
67: #define KA820PORT_WMEM 0x00200000 /* write mem */
68: #define KA820PORT_EV4 0x00100000 /* event 4 */
69: #define KA820PORT_EV3 0x00080000 /* event 3 */
70: #define KA820PORT_EV2 0x00040000 /* event 2 */
71: #define KA820PORT_EV1 0x00020000 /* event 1 */
72: #define KA820PORT_EV0 0x00010000 /* event 0 */
73: #define KA820PORT_WWPO 0x00008000 /* ??? parity odd? */
74: #define KA820PORT_PERH 0x00004000 /* parity error H */
75: #define KA820PORT_ENBPIPE 0x00002000 /* enable? pipe */
76: #define KA820PORT_TIMEOUT 0x00001000 /* timeout */
77: #define KA820PORT_RSVD 0x00000800 /* reserved */
78: #define KA820PORT_CONSEN 0x00000400 /* console interrupt enable */
79: #define KA820PORT_CONSCLR 0x00000200 /* clear console interrupt */
80: #define KA820PORT_CONSINTR 0x00000100 /* console interrupt req */
81: #define KA820PORT_RXIE 0x00000080 /* RX50 interrupt enable */
82: #define KA820PORT_RXCLR 0x00000040 /* clear RX50 interrupt */
83: #define KA820PORT_RXIRQ 0x00000020 /* RX50 interrupt request */
84: #define KA820PORT_IPCLR 0x00000010 /* clear IP interrupt */
85: #define KA820PORT_IPINTR 0x00000008 /* IP interrupt request */
86: #define KA820PORT_CRDEN 0x00000004 /* enable CRD interrupts */
87: #define KA820PORT_CRDCLR 0x00000002 /* clear CRD interrupt */
88: #define KA820PORT_CRDINTR 0x00000001 /* CRD interrupt request */
89:
90: /* interrupt vectors unique for this CPU */
91: #define KA820_INT_RXCD 0x58
92:
93: /* what the heck */
94: #define KA820PORT_BITS \
95: "\20\40RSTHALT\37LCONS\36LCONSEN\35BIRESET\34BISTF\33ENBAPT\32STPASS\31RUN\
96: \30WWPE\27EVLCK\26WMEM\25EV4\24EV3\23EV2\22EV1\21EV\20WWPO\17PERH\16ENBPIPE\
97: \15TIMEOUT\13CONSEN\12CONSCLR\11CONSINTR\10RXIE\7RXCLR\6RXIRQ\5IPCLR\4IPINTR\
98: \3CRDEN\2CLRCLR\1CRDINTR"
99:
100: /* clock CSR bit values, per csr */
101: #define KA820CLK_0_BUSY 0x01 /* busy (time changing) */
102: #define KA820CLK_1_GO 0x0c /* run */
103: #define KA820CLK_1_SET 0x0d /* set the time */
104: #define KA820CLK_3_VALID 0x01 /* clock is valid */
105:
106: #ifndef LOCORE
107: struct ka820port {
108: u_long csr;
109: /* that seems to be all.... */
110: };
111:
112: struct ka820clock {
113: u_char sec;
114: u_char pad0;
115: u_char secalrm;
116: u_char pad1;
117: u_char min;
118: u_char pad2;
119: u_char minalrm;
120: u_char pad3;
121: u_char hr;
122: u_char pad4;
123: u_char hralrm;
124: u_char pad5;
125: u_char dayofwk;
126: u_char pad6;
127: u_char day;
128: u_char pad7;
129: u_char mon;
130: u_char pad8;
131: u_char yr;
132: u_char pad9;
133: u_short csr0;
134: u_short csr1;
135: u_short csr2;
136: u_short csr3;
137: };
138:
139: void crxintr(void *arg);
140: #endif
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