Annotation of sys/arch/vax/include/ka650.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: ka650.h,v 1.10 2003/06/02 23:27:57 millert Exp $ */
! 2: /* $NetBSD: ka650.h,v 1.6 1997/07/26 10:12:43 ragge Exp $ */
! 3: /*
! 4: * Copyright (c) 1988 The Regents of the University of California.
! 5: * All rights reserved.
! 6: *
! 7: * This code is derived from software contributed to Berkeley by
! 8: * Mt. Xinu.
! 9: *
! 10: * Redistribution and use in source and binary forms, with or without
! 11: * modification, are permitted provided that the following conditions
! 12: * are met:
! 13: * 1. Redistributions of source code must retain the above copyright
! 14: * notice, this list of conditions and the following disclaimer.
! 15: * 2. Redistributions in binary form must reproduce the above copyright
! 16: * notice, this list of conditions and the following disclaimer in the
! 17: * documentation and/or other materials provided with the distribution.
! 18: * 3. Neither the name of the University nor the names of its contributors
! 19: * may be used to endorse or promote products derived from this software
! 20: * without specific prior written permission.
! 21: *
! 22: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
! 23: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
! 24: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
! 25: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
! 26: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
! 27: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
! 28: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
! 29: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
! 30: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
! 31: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
! 32: * SUCH DAMAGE.
! 33: *
! 34: * @(#)ka650.h 7.5 (Berkeley) 6/28/90
! 35: */
! 36:
! 37: /*
! 38: *
! 39: * Definitions specific to the ka650 (uVAX 3600/3602) cpu card.
! 40: */
! 41:
! 42: /*
! 43: * CAER: Memory System Error Register (IPR 39)
! 44: */
! 45: #define CAER_DAL 0x00000040 /* CDAL or level 2 cache data parity */
! 46: #define CAER_MCD 0x00000020 /* mcheck due to DAL parity error */
! 47: #define CAER_MCC 0x00000010 /* mcheck due to 1st lev cache parity */
! 48: #define CAER_DAT 0x00000002 /* data parity in 1st level cache */
! 49: #define CAER_TAG 0x00000001 /* tag parity in 1st level cache */
! 50:
! 51: /*
! 52: * CADR: Cache Disable Register (IPR 37)
! 53: */
! 54: #define CADR_STMASK 0x000000f0 /* 1st level cache state mask */
! 55: #define CADR_SEN2 0x00000080 /* 1st level cache set 2 enabled */
! 56: #define CADR_SEN1 0x00000040 /* 1st level cache set 1 enabled */
! 57: #define CADR_CENI 0x00000020 /* 1st level I-stream caching enabled */
! 58: #define CADR_CEND 0x00000010 /* 1st level D-stream caching enabled */
! 59:
! 60: /*
! 61: * Internal State Info 2: (for mcheck recovery)
! 62: */
! 63: #define IS2_VCR 0x00008000 /* VAX Can't Restart flag */
! 64:
! 65: /*
! 66: * DMA System Error Register (merr_dser)
! 67: */
! 68: #define DSER_QNXM 0x00000080 /* Q-22 Bus NXM */
! 69: #define DSER_QPE 0x00000020 /* Q-22 Bus parity Error */
! 70: #define DSER_MEM 0x00000010 /* Main mem err due to ext dev DMA */
! 71: #define DSER_LOST 0x00000008 /* Lost error: DSER <7,5,4,0> set */
! 72: #define DSER_NOGRANT 0x00000004 /* No Grant timeout on cpu demand R/W */
! 73: #define DSER_DNXM 0x00000001 /* DMA NXM */
! 74: #define DSER_CLEAR (DSER_QNXM | DSER_QPE | DSER_MEM | \
! 75: DSER_LOST | DSER_NOGRANT | DSER_DNXM)
! 76: #define DMASER_BITS \
! 77: "\20\20BHALT\17DCNEG\10QBNXM\6QBPE\5MEMERR\4LOSTERR\3NOGRANT\1DMANXM"
! 78:
! 79: #ifndef _LOCORE
! 80: /*
! 81: * Local registers (in I/O space)
! 82: * This is done in disjoint sections. Map names are set in locore.s
! 83: * and they are mapped in routine configcpu()
! 84: */
! 85:
! 86: /*
! 87: * memory error & configuration registers
! 88: */
! 89: struct ka650_merr {
! 90: u_long merr_scr; /* System Config Register */
! 91: u_long merr_dser; /* DMA System Error Register */
! 92: u_long merr_qbear; /* QBus Error Address Register */
! 93: u_long merr_dear; /* DMA Error Address Register */
! 94: u_long merr_qbmbr; /* Q Bus Map Base address Register */
! 95: u_long pad[59];
! 96: u_long merr_csr[16]; /* Main Memory Config Regs (16 banks) */
! 97: u_long merr_errstat; /* Main Memory Error Status */
! 98: u_long merr_cont; /* Main Memory Control */
! 99: };
! 100: #define KA650_MERR 0x20080000
! 101:
! 102: /*
! 103: * Main Memory Error Status Register (merr_errstat)
! 104: */
! 105: #define MEM_EMASK 0xe0000180 /* mask of all err bits */
! 106: #define MEM_RDS 0x80000000 /* uncorrectable main memory */
! 107: #define MEM_RDSHIGH 0x40000000 /* high rate RDS errors */
! 108: #define MEM_CRD 0x20000000 /* correctable main memory */
! 109: #define MEM_DMA 0x00000100 /* DMA read or write error */
! 110: #define MEM_CDAL 0x00000080 /* CDAL Parity error on write */
! 111: #define MEM_PAGE 0x1ffffe00 /* Offending Page Number */
! 112: #define MEM_PAGESHFT 9 /* Shift to normalize page number */
! 113:
! 114: /*
! 115: * Main Memory Control & Diag Status Reg (merr_cont)
! 116: */
! 117: #define MEM_CRDINT 0x00001000 /* CRD interrupts enabled */
! 118: #define MEM_REFRESH 0x00000800 /* Forced memory refresh */
! 119: #define MEM_ERRDIS 0x00000400 /* error detect disable */
! 120: #define MEM_DIAG 0x00000080 /* Diagnostics mode */
! 121: #define MEM_CHECK 0x0000007f /* check bits for diagnostic mode */
! 122:
! 123: /*
! 124: * Main Memory Config Regs (merr_csr[0-15])
! 125: */
! 126: #define MEM_BNKENBLE 0x80000000 /* Bank Enable */
! 127: #define MEM_BNKNUM 0x03c00000 /* Physical map Bank number */
! 128: #define MEM_BNKUSAGE 0x00000003 /* Bank Usage */
! 129:
! 130: /*
! 131: * Cache Control & Boot/Diag registers
! 132: */
! 133: struct ka650_cbd {
! 134: u_char cbd_cacr; /* Low byte: Cache Enable & Parity Err detect */
! 135: u_char cbd_cdf1; /* Cache diagnostic field (unused) */
! 136: u_char cbd_cdf2; /* Cache diagnostic field (unused) */
! 137: u_char pad;
! 138: u_long cbd_bdr; /* Boot & Diagnostic Register (unused) */
! 139: };
! 140: #define KA650_CBD 0x20084000
! 141:
! 142: /*
! 143: * CACR: Cache Control Register (2nd level cache) (cbd_cacr)
! 144: */
! 145: #define CACR_CEN 0x00000010 /* Cache enable */
! 146: #define CACR_CPE 0x00000020 /* Cache Parity Error */
! 147:
! 148: /*
! 149: * System Support Chip (SSC) registers
! 150: */
! 151: struct ka650_ssc {
! 152: u_long ssc_sscbr; /* SSC Base Addr Register */
! 153: u_long pad1[3];
! 154: u_long ssc_ssccr; /* SSC Configuration Register */
! 155: u_long pad2[3];
! 156: u_long ssc_cbtcr; /* CDAL Bus Timeout Control Register */
! 157: u_long pad3[55];
! 158: u_long ssc_tcr0; /* timer control reg 0 */
! 159: u_long ssc_tir0; /* timer interval reg 0 */
! 160: u_long ssc_tnir0; /* timer next interval reg 0 */
! 161: u_long ssc_tivr0; /* timer interrupt vector reg 0 */
! 162: u_long ssc_tcr1; /* timer control reg 1 */
! 163: u_long ssc_tir1; /* timer interval reg 1 */
! 164: u_long ssc_tnir1; /* timer next interval reg 1 */
! 165: u_long ssc_tivr1; /* timer interrupt vector reg 1 */
! 166: u_long pad4[184];
! 167: u_char ssc_cpmbx; /* Console Program Mail Box: Lang & Hact */
! 168: u_char ssc_terminfo; /* TTY info: Video Dev, MCS, CRT & ROM flags */
! 169: u_char ssc_keyboard; /* Keyboard code */
! 170: };
! 171: #define KA650_SSC 0x20140000
! 172:
! 173: /*
! 174: * CBTCR: CDAL Bus Timeout Control Register (ssc_cbtcr)
! 175: */
! 176: #define CBTCR_BTO 0x80000000 /* r/w unimp IPR or unack intr */
! 177: #define CBTCR_RWT 0x40000000 /* CDAL Bus Timeout on CPU or DMA */
! 178:
! 179: /*
! 180: * TCR0/TCR1: Programable Timer Control Registers (ssc_tcr[01])
! 181: * (The rest of the bits are the same as in the standard VAX
! 182: * Interval timer and are defined in clock.h)
! 183: */
! 184: #define TCR_STP 0x00000004 /* Stop after time-out */
! 185:
! 186: /*
! 187: * Flags for Console Program Mail Box
! 188: */
! 189: #define CPMB650_HALTACT 0x03 /* Field for halt action */
! 190: #define CPMB650_RESTART 0x01 /* Restart */
! 191: #define CPMB650_REBOOT 0x02 /* Reboot */
! 192: #define CPMB650_HALT 0x03 /* Halt */
! 193: #define CPMB650_BIP 0x04 /* Bootstrap in progress */
! 194: #define CPMB650_RIP 0x08 /* Restart in progress */
! 195: #define CPMB650_DOTHIS 0x30 /* Execute sommand */
! 196: #define CPMB650_LANG 0xf0 /* Language field */
! 197:
! 198: /*
! 199: * Inter Processor Communication Register
! 200: * To determine if memory error was from QBUS device DMA (as opposed to cpu).
! 201: */
! 202: struct ka650_ipcr {
! 203: u_long pad[80];
! 204: u_short ipcr0; /* InterProcessor Comm Reg for arbiter */
! 205: };
! 206: #define KA650_IPCR 0x20001e00
! 207:
! 208: #endif /* _LOCORE */
! 209:
! 210: /*
! 211: * Physical start address of the Qbus memory.
! 212: * The q-bus memory size is 4 meg.
! 213: * Physical start address of the I/O space (where the 8Kbyte I/O page is).
! 214: */
! 215: #define KA650_QMEM 0x30000000
! 216: #define KA650_QMEMSIZE (512*8192)
! 217: #define KA650_QDEVADDR 0x20000000
! 218:
! 219: /*
! 220: * Mapping info for Cache Entries, including
! 221: * Size (in bytes) of 2nd Level Cache for cache flush operation
! 222: */
! 223: #define KA650_CACHE 0x10000000
! 224: #define KA650_CACHESIZE (64*1024)
! 225:
! 226: /*
! 227: * Useful ROM addresses
! 228: */
! 229: #define KA650ROM_SIDEX 0x20060004 /* system ID extension */
! 230: #define KA650ROM_GETC 0x20060008 /* (jsb) get character from console */
! 231: #define KA650ROM_PUTS 0x2006000c /* (jsb) put string to console */
! 232: #define KA650ROM_GETS 0x20060010 /* (jsb) read string with prompt */
! 233: #define KA650_CONSTYPE 0x20140401 /* byte at which console type resides */
! 234:
! 235: /*
! 236: * Some useful macros
! 237: */
! 238: #define GETCPUTYPE(x) ((x >> 24) & 0xff)
! 239: #define GETSYSSUBT(x) ((x >> 8) & 0xff)
! 240: #define GETFRMREV(x) ((x >> 16) & 0xff)
! 241: #define GETCODREV(x) (x & 0xff)
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