Annotation of sys/arch/vax/include/ka43.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: ka43.h,v 1.5 2006/07/25 21:11:08 miod Exp $ */
2: /* $NetBSD: ka43.h,v 1.2 1997/04/18 18:53:40 ragge Exp $ */
3: /*
4: * Copyright (c) 1996 Ludd, University of Lule}, Sweden.
5: * All rights reserved.
6: *
7: * This code is derived from software contributed to Ludd by Bertram Barth.
8: *
9: * Redistribution and use in source and binary forms, with or without
10: * modification, are permitted provided that the following conditions
11: * are met:
12: * 1. Redistributions of source code must retain the above copyright
13: * notice, this list of conditions and the following disclaimer.
14: * 2. Redistributions in binary form must reproduce the above copyright
15: * notice, this list of conditions and the following disclaimer in the
16: * documentation and/or other materials provided with the distribution.
17: * 3. All advertising materials mentioning features or use of this software
18: * must display the following acknowledgement:
19: * This product includes software developed at Ludd, University of
20: * Lule}, Sweden and its contributors.
21: * 4. The name of the author may not be used to endorse or promote products
22: * derived from this software without specific prior written permission
23: *
24: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
25: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
26: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
28: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
33: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34: */
35:
36: /*
37: * Definitions for I/O addresses of
38: *
39: * VAXstation 3100 model 76 (RigelMAX)
40: */
41:
42: #define KA43_SIDEX 0x20040004 /* SID extension register */
43:
44: #define KA43_CFGTST 0x20020000 /* Configuration and Test register */
45: #define KA43_IORESET 0x20020000 /* I/O Reset register */
46:
47: #define KA43_ROMGETC 0x20040044
48: #define KA43_ROMPUTC 0x20040058
49: #define KA43_ROMPUTS 0x2004004C
50:
51: #define KA43_CH2_BASE 0x10000000 /* 2nd level cache data area */
52: #define KA43_CH2_END 0x1FFFFFFF
53: #define KA43_CH2_SIZE 0x10000000
54: #define KA43_CT2_BASE 0x21000000 /* 2nd level cache tag area */
55: #define KA43_CT2_END 0x2101FFFF
56: #define KA43_CT2_SIZE 0x20000
57: #define KA43_CH2_CREG 0x21100000 /* 2nd level cache control register */
58:
59: #define KA43_ROM_BASE 0x20040000 /* System module ROM */
60: #define KA43_ROM_END 0x2007FFFF
61: #define KA43_ROM_SIZE 0x40000 /* ??? */
62:
63: #define KA43_IVN_BASE 0x20040020 /* Interrupt Vector Numbers */
64: #define KA43_IVN_END 0x2004003F
65: #define KA43_IVN_SIZE 0x20
66:
67: #define KA43_HLTCOD 0x20080000 /* Halt Code Register */
68: /* #define KA43_MSER 0x20080004 */ /* Memory System Error register */
69: /* #define KA43_MEAR 0x20080008 */ /* Memory Error Address register */
70: #define KA43_INTMSK 0x2008000C /* Interrupt Mask register */
71: #define KA43_VDCORG 0x2008000D /* Video Controller Origin Register */
72: #define KA43_VDCSEL 0x2008000E /* Video Controller Select Register */
73: #define KA43_INTREQ 0x2008000F /* Interrupt Request register */
74: #define KA43_INTCLR 0x2008000F /* Interrupt Request clear register */
75: #define KA43_DIAGDSP 0x20080010 /* Diagnostic display register */
76: #define KA43_PARCTL 0x20080014 /* Parity Control Register */
77: #define KA43_DIAGTME 0x2008001E /* diagnostic time register */
78:
79: #define KA43_PCTL_DPEN 0x00000001 /* DMA parity enable (bit 0) */
80: #define KA43_PCTL_CPEN 0x00000002 /* CPU Parity enable (bit 1) */
81: #define KA43_PCTL_DMA 0x01000000 /* LANCE DMA control (bit 24) */
82:
83: /*
84: * "CH2" and "SESR" are two common names related to Secondary Cache
85: */
86: #define KA43_SESR 0x21100000 /* same as KA43_CH2_CREG */
87:
88: #define KA43_SESR_CENB 0x00000001 /* Cache Enable */
89: #define KA43_SESR_SERR 0x00000002
90: #define KA43_SESR_LERR 0x00000004
91: #define KA43_SESR_CERR 0x00000008
92: #define KA43_SESR_DIRTY 0x00000010
93: #define KA43_SESR_MISS 0x00000020
94: #define KA43_SESR_DPE 0x00000040 /* Dal Parity Error */
95: #define KA43_SESR_TPE 0x00000080 /* Tag Parity Error */
96: #define KA43_SESR_WSB 0x00010000
97: #define KA43_SESR_CIEA 0x7FFC0000
98:
99: #define KA43_SESR_BITS \
100: "\020\010TPE\007DPE\006MISS\005DIRTY\004CERR\003LERR\002SERR\001ENABLE"
101:
102: /*
103: * The following values refer to bits/bitfields within the 4 internal
104: * registers controlling primary cache:
105: * PR_PCTAG(124, tag-register) PR_PCIDX(125, index-register)
106: * PR_PCERR(126, error-register) PR_PCSTS(127, status-register)
107: */
108: #define KA43_PCTAG_TAG 0x1FFFF800 /* bits 11-29 */
109: #define KA43_PCTAG_PARITY 0x40000000
110: #define KA43_PCTAG_VALID 0x80000000
111:
112: #define KA43_PCIDX_INDEX 0x000007F8 /* 0x100 Q-word entries */
113:
114: #define KA43_PCERR_ADDR 0x3FFFFFFF
115:
116: #define KA43_PCS_FORCEHIT 0x00000001 /* Force hit */
117: #define KA43_PCS_ENABLE 0x00000002 /* Enable primary cache */
118: #define KA43_PCS_FLUSH 0x00000004 /* Flush cache */
119: #define KA43_PCS_REFRESH 0x00000008 /* Enable refresh */
120: #define KA43_PCS_HIT 0x00000010 /* Cache hit */
121: #define KA43_PCS_INTERRUPT 0x00000020 /* Interrupt pending */
122: #define KA43_PCS_TRAP2 0x00000040 /* Trap while trap */
123: #define KA43_PCS_TRAP1 0x00000080 /* Micro trap/machine check */
124: #define KA43_PCS_TPERR 0x00000100 /* Tag parity error */
125: #define KA43_PCS_DPERR 0x00000200 /* Dal data parity error */
126: #define KA43_PCS_PPERR 0x00000400 /* P data parity error */
127: #define KA43_PCS_BUSERR 0x00000800 /* Bus error */
128: #define KA43_PCS_BCHIT 0x00001000 /* B cache hit */
129:
130: #define KA43_PCSTS_BITS \
131: "\020\015BCHIT\014BUSERR\013PPERR\012DPERR\011TPERR\010TRAP1" \
132: "\007TRAP2\006INTR\005HIT\004REFRESH\003FLUSH\002ENABLE\001FORCEHIT"
133:
134: /*
135: * Bits in PR_ACCS (Floating Point Accelerator Register)
136: */
137: #define KA43_ACCS_VECTOR (1<<0) /* Vector Unit Present */
138: #define KA43_ACCS_FCHIP (1<<1) /* FPU chip present */
139: #define KA43_ACCS_WEP (1<<31) /* Write Even Parity */
140:
141: /*
142: * Other fixed addresses which should be mapped
143: */
144: #define KA43_CPU_BASE 0x20080000 /* so called "CPU registers" */
145: #define KA43_CPU_END 0x200800FF
146: #define KA43_CPU_SIZE 0x100
147: #define KA43_NWA_BASE 0x20090000 /* Network Address ROM */
148: #define KA43_NWA_END 0x2009007F
149: #define KA43_NWA_SIZE 0x80
150: #define KA43_SER_BASE 0x200A0000 /* Serial line controller */
151: #define KA43_SER_END 0x200A000F
152: #define KA43_SER_SIZE 0x10
153: #define KA43_WAT_BASE 0x200B0000 /* TOY clock and NV-RAM */
154: #define KA43_WAT_END 0x200B00FF
155: #define KA43_WAT_SIZE 0x100
156: #define KA43_SC1_BASE 0x200C0080 /* 1st SCSI Controller Chip */
157: #define KA43_SC1_END 0x200C009F
158: #define KA43_SC1_SIZE 0x20
159: #define KA43_SC2_BASE 0x200C0180 /* 2nd SCSI Controller Chip */
160: #define KA43_SC2_END 0x200C019F
161: #define KA43_SC2_SIZE 0x20
162: #define KA43_SCS_BASE 0x200C0000 /* area occupied by SCSI 1+2 */
163: #define KA43_SCS_END 0x200C01FF
164: #define KA43_SCS_SIZE 0x200
165: #define KA43_LAN_BASE 0x200E0000 /* LANCE chip registers */
166: #define KA43_LAN_END 0x200E0007
167: #define KA43_LAN_SIZE 0x08
168: #define KA43_CUR_BASE 0x200F0000 /* Monochrome video cursor chip */
169: #define KA43_CUR_END 0x200F003C
170: #define KA43_CUR_SIZE 0x40
171: #define KA43_DMA_BASE 0x202D0000 /* 128KB Data Buffer */
172: #define KA43_DMA_END 0x202EFFFF
173: #define KA43_DMA_SIZE 0x20000
174: #define KA43_VME_BASE 0x30000000
175: #define KA43_VME_END 0x3003FFFF
176: #define KA43_VME_SIZE 0x40000
177:
178: #define KA43_DIAGMEM 0x28000000 /* start of diagnostic memory */
179:
180: #define KA43_SC1_DADR 0x200C00A0 /* (1st SCSI) DMA address register */
181: #define KA43_SC1_DCNT 0x200C00C0 /* (1st SCSI) DMA byte count reg. */
182: #define KA43_SC1_DDIR 0x200C00C4 /* (1st SCSI) DMA transfer direction */
183: #define KA43_SC2_DADR 0x200C01A0
184: #define KA43_SC2_DCNT 0x200C01C0
185: #define KA43_SC2_DDIR 0x200C01C4
186:
187: /*
188: * Clock-Chip data in NVRAM
189: */
190: #define KA43_CPMBX 0x200B0038 /* Console Mailbox (1 byte) */
191: #define KA43_CPFLG 0x200B003C /* Console Program Flags (1 byte) */
192: #define KA43_LK201_ID 0x200B0040 /* Keyboard Variation (1 byte) */
193: #define KA43_CONS_ID 0x200B0044 /* Console Device Type (1 byte) */
194: #define KA43_SCR 0x200B0048 /* Console Scratch RAM */
195: #define KA43_TEMP 0x200B0058 /* Used by System Firmware */
196: #define KA43_BAT_CHK 0x200B0088 /* Battery Check Data */
197: #define KA43_PASSWD 0x200B0098 /* ??? */
198: #define KA43_BOOTFLG 0x200B00A8 /* Default Boot Flags (4 bytes) */
199: #define KA43_SCRLEN 0x200B00B8 /* Number of pages of SCR (1 byte) */
200: #define KA43_SCSIPORT 0x200B00BC /* Tape Controller Port Data */
201: #define KA43_RESERVED 0x200B00C0 /* Reserved (16 bytes) */
202:
203: struct ka43_cpu {
204: u_long hltcod; /* Halt Code Register */
205: u_long pad2;
206: u_long pad3;
207: u_char intreg[4]; /* Four 1-byte registers */
208: u_short diagdsp; /* Diagnostic display register */
209: u_short pad4;
210: u_long parctl; /* Parity Control Register */
211: u_short pad5;
212: u_short pad6;
213: u_short pad7;
214: u_short diagtme; /* Diagnostic time register */
215: };
216:
217: struct ka43_clock {
218: u_long :2; u_long sec :8; u_long :22;
219: u_long :2; u_long secalrm :8; u_long :22;
220: u_long :2; u_long min :8; u_long :22;
221: u_long :2; u_long minalrm :8; u_long :22;
222: u_long :2; u_long hr :8; u_long :22;
223: u_long :2; u_long hralrm :8; u_long :22;
224: u_long :2; u_long dayofwk :8; u_long :22;
225: u_long :2; u_long day :8; u_long :22;
226: u_long :2; u_long mon :8; u_long :22;
227: u_long :2; u_long yr :8; u_long :22;
228: u_long :2; u_long csr0 :8; u_long :22;
229: u_long :2; u_long csr1 :8; u_long :22;
230: u_long :2; u_long csr2 :8; u_long :22;
231: u_long :2; u_long csr3 :8; u_long :22;
232: u_long :2; u_long cpmbx :8; u_long :22;
233: };
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