Annotation of sys/arch/vax/include/ka420.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: ka420.h,v 1.4 2006/07/25 21:11:08 miod Exp $ */
2: /* $NetBSD: ka420.h,v 1.2 1998/06/07 18:34:09 ragge Exp $ */
3: /*
4: * Copyright (c) 1996 Ludd, University of Lule}, Sweden.
5: * All rights reserved.
6: *
7: * This code is derived from software contributed to Ludd by Bertram Barth.
8: *
9: * Redistribution and use in source and binary forms, with or without
10: * modification, are permitted provided that the following conditions
11: * are met:
12: * 1. Redistributions of source code must retain the above copyright
13: * notice, this list of conditions and the following disclaimer.
14: * 2. Redistributions in binary form must reproduce the above copyright
15: * notice, this list of conditions and the following disclaimer in the
16: * documentation and/or other materials provided with the distribution.
17: * 3. All advertising materials mentioning features or use of this software
18: * must display the following acknowledgement:
19: * This product includes software developed at Ludd, University of
20: * Lule}, Sweden and its contributors.
21: * 4. The name of the author may not be used to endorse or promote products
22: * derived from this software without specific prior written permission
23: *
24: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
25: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
26: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
28: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
33: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34: */
35:
36: /*
37: * Definitions for I/O addresses of
38: *
39: * VAXstation 3100 models 30, 40 (PVAX)
40: * MicroVAX 3100 models 10, 20 (Teammate II)
41: * MicroVAX 3100 models 10e, 20e (Teammate II)
42: * VAXstation 3100 models 38, 48 (PVAX rev#7)
43: */
44:
45: #define KA420_SIDEX 0x20040004 /* SID extension register */
46:
47: #define KA420_CH2_BASE 0x10000000 /* 2nd level cache data area */
48: #define KA420_CH2_END 0x10007FFF
49: #define KA420_CH2_SIZE 0x8000
50: #define KA420_CT2_BASE 0x10010000 /* 2nd level cache tag area */
51: #define KA420_CT2_END 0x10017FFF
52: #define KA420_CT2_SIZE 0x8000
53: #define KA420_CH2_CREG 0x20084000 /* 2nd level cache control register */
54:
55: #define KA420_CFGTST 0x20020000 /* Configuration and Test register */
56: #define KA420_IORESET 0x20020000 /* I/O Reset register */
57:
58: #define KA420_ROM_BASE 0x20040000 /* System module ROM */
59: #define KA420_ROM_END 0x2007FFFF
60: #define KA420_ROM_SIZE 0x40000 /* ??? */
61:
62: #define KA420_IVN_BASE 0x20040020 /* Interrupt Vector Numbers */
63: #define KA420_IVN_END 0x2004003F
64: #define KA420_IVN_SIZE 0x20
65:
66: #define KA420_HLTCOD 0x20080000 /* Halt Code Register */
67: #define KA420_MSER 0x20080004 /* Memory System Error register */
68: #define KA420_MEAR 0x20080008 /* Memory Error Address register */
69: #define KA420_INTMSK 0x2008000C /* Interrupt Mask register */
70: #define KA420_VDCORG 0x2008000D /* Video Controller Origin Register */
71: #define KA420_VDCSEL 0x2008000E /* Video Controller Select Register */
72: #define KA420_INTREQ 0x2008000F /* Interrupt Request register */
73: #define KA420_INTCLR 0x2008000F /* Interrupt Request clear register */
74:
75: #define KA420_CACR 0x20084000 /* L2 cache ctrl reg */
76:
77: /*
78: * Other fixed addresses which should be mapped
79: */
80: #define KA420_NWA_BASE 0x20090000 /* Network Address ROM */
81: #define KA420_NWA_END 0x2009007F
82: #define KA420_NWA_SIZE 0x80
83: #define KA420_SER_BASE 0x200A0000 /* Serial line controller */
84: #define KA420_SER_END 0x200A000F
85: #define KA420_SER_SIZE 0x10
86: #define KA420_WAT_BASE 0x200B0000 /* TOY clock and NV-RAM */
87: #define KA420_WAT_END 0x200B00FF
88: #define KA420_WAT_SIZE 0x100
89: #define KA420_DKC_BASE 0x200C0000 /* Disk Controller Ports */
90: #define KA420_DKC_END 0x200C0007
91: #define KA420_DKC_SIZE 0x08
92: #define KA420_SCS_BASE 0x200C0080 /* Tape (SCSI) Controller Chip */
93: #define KA420_SCS_END 0x200C009F
94: #define KA420_SCS_SIZE 0x20
95: #define KA420_D16_BASE 0x200D0000 /* 16KB (compatibility) Data Buffer */
96: #define KA420_D16_END 0x200D3FFF
97: #define KA420_D16_SIZE 0x4000
98: #define KA420_LAN_BASE 0x200E0000 /* LANCE chip registers */
99: #define KA420_LAN_END 0x200E0007
100: #define KA420_LAN_SIZE 0x08
101: #define KA420_CUR_BASE 0x200F0000 /* Monochrome video cursor chip */
102: #define KA420_CUR_END 0x200F003F
103: #define KA420_CUR_SIZE 0x40
104: #define KA420_DMA_BASE 0x202D0000 /* 128KB Data Buffer */
105: #define KA420_DMA_END 0x202EFFFF
106: #define KA420_DMA_SIZE 0x20000
107:
108: #define KA420_SCD_DADR 0x200C00A0 /* Tape(SCSI) DMA address register */
109: #define KA420_SCD_DCNT 0x200C00C0 /* Tape(SCSI) DMA byte count reg. */
110: #define KA420_SCD_DDIR 0x200C00C4 /* Tape(SCSI) DMA transfer direction */
111:
112: #define KA420_STC_MODE 0x200C00E0 /* Storage Controller Mode register */
113:
114: /*
115: * Clock-Chip data in NVRAM
116: */
117: #define KA420_CPMBX 0x200B0038 /* Console Mailbox (1 byte) */
118: #define KA420_CPFLG 0x200B003C /* Console Program Flags (1 byte) */
119: #define KA420_LK201_ID 0x200B0040 /* Keyboard Variation (1 byte) */
120: #define KA420_CONS_ID 0x200B0044 /* Console Device Type (1 byte) */
121: #define KA420_SCR 0x200B0048 /* Console Scratch RAM */
122: #define KA420_TEMP 0x200B0058 /* Used by System Firmware */
123: #define KA420_BAT_CHK 0x200B0088 /* Battery Check Data */
124: #define KA420_BOOTDEV 0x200B0098 /* Default Boot Device (4 bytes) */
125: #define KA420_BOOTFLG 0x200B00A8 /* Default Boot Flags (4 bytes) */
126: #define KA420_SCRLEN 0x200B00B8 /* Number of pages of SCR (1 byte) */
127: #define KA420_SCSIPORT 0x200B00BC /* Tape Controller Port Data */
128: #define KA420_RESERVED 0x200B00C0 /* Reserved (16 bytes) */
129:
130: /* Used bits in the CFGTST (20020000) register */
131: #define KA420_CFG_STCMSK 0xc000 /* Storage controller mask */
132: #define KA420_CFG_RB 0x0000 /* RB (ST506/SCSI) present */
133: #define KA420_CFG_RD 0x4000 /* RD (SCSI/SCSI) present */
134: #define KA420_CFG_NONE 0xc000 /* No storage ctlr present */
135: #define KA420_CFG_MULTU 0x80 /* MicroVAX or VAXstation */
136: #define KA420_CFG_CACHPR 0x40 /* Secondary cache present */
137: #define KA420_CFG_L3CON 0x20 /* Console on line #3 of dc */
138: #define KA420_CFG_CURTEST 0x10 /* Cursor Test (monochrom) */
139: #define KA420_CFG_VIDOPT 0x08 /* Video option present */
140:
141: /* Primary cache bits (CADR, IPR 37) */
142: #define KA420_CADR_S2E 0x80 /* set 2 enable */
143: #define KA420_CADR_S1E 0x40 /* set 1 enable */
144: #define KA420_CADR_ISE 0x20 /* insn caching enable */
145: #define KA420_CADR_DSE 0x10 /* data caching enable */
146: #define KA420_CADR_WWP 0x02 /* write wrong parity */
147: #define KA420_CADR_DIA 0x01 /* diagnostic mode */
148:
149: /* Secondary cache bits (CACR, 20084000) */
150: #define KA420_CACR_CP3 0x80000000 /* last parity read */
151: #define KA420_CACR_CP2 0x40000000 /* last parity read */
152: #define KA420_CACR_CP1 0x20000000 /* last parity read */
153: #define KA420_CACR_CP0 0x10000000 /* last parity read */
154: #define KA420_CACR_TPP 0x00100000 /* tag predicted parity */
155: #define KA420_CACR_TGP 0x00080000 /* tag parity read */
156: #define KA420_CACR_TGV 0x00040000 /* valid flag */
157: #define KA420_CACR_TPE 0x00000020 /* tag parity error */
158: #define KA420_CACR_CEN 0x00000010 /* cache enable */
159:
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